Changeset 7c3fb9b in mainline for kernel/arch


Ignore:
Timestamp:
2018-05-17T08:29:01Z (8 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6ff23ff
Parents:
fac0ac7
git-author:
Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)
git-committer:
Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)
Message:

Fix block comment formatting (ccheck).

Location:
kernel/arch
Files:
32 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/include/arch/asm.h

    rfac0ac7 r7c3fb9b  
    4646NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
    4747{
    48         /* On real hardware this should stop processing further
    49            instructions on the CPU (and possibly putting it into
    50            low-power mode) without any possibility of exitting
    51            this function. */
     48        /*
     49         * On real hardware this should stop processing further
     50         * instructions on the CPU (and possibly putting it into
     51         * low-power mode) without any possibility of exitting
     52         * this function.
     53         */
    5254
    5355        while (true)
    … …  
    5759NO_TRACE static inline void cpu_sleep(void)
    5860{
    59         /* On real hardware this should put the CPU into low-power
    60            mode. However, the CPU is free to continue processing
    61            futher instructions any time. The CPU also wakes up
    62            upon an interrupt. */
     61        /*
     62         * On real hardware this should put the CPU into low-power
     63         * mode. However, the CPU is free to continue processing
     64         * futher instructions any time. The CPU also wakes up
     65         * upon an interrupt.
     66         */
    6367}
    6468

  • kernel/arch/abs32le/include/arch/atomic.h

    rfac0ac7 r7c3fb9b  
    4747    REQUIRES(val->count < ATOMIC_COUNT_MAX)
    4848{
    49         /* On real hardware the increment has to be done
    50            as an atomic action. */
     49        /*
     50         * On real hardware the increment has to be done
     51         * as an atomic action.
     52         */
    5153
    5254        val->count++;
    … …  
    5860    REQUIRES(val->count > ATOMIC_COUNT_MIN)
    5961{
    60         /* On real hardware the decrement has to be done
    61            as an atomic action. */
     62        /*
     63         * On real hardware the decrement has to be done
     64         * as an atomic action.
     65         */
    6266
    6367        val->count--;
    … …  
    6973    REQUIRES(val->count < ATOMIC_COUNT_MAX)
    7074{
    71         /* On real hardware both the storing of the previous
    72            value and the increment have to be done as a single
    73            atomic action. */
     75        /*
     76         * On real hardware both the storing of the previous
     77         * value and the increment have to be done as a single
     78         * atomic action.
     79         */
    7480
    7581        atomic_count_t prev = val->count;
    … …  
    8490    REQUIRES(val->count > ATOMIC_COUNT_MIN)
    8591{
    86         /* On real hardware both the storing of the previous
    87            value and the decrement have to be done as a single
    88            atomic action. */
     92        /*
     93         * On real hardware both the storing of the previous
     94         * value and the decrement have to be done as a single
     95         * atomic action.
     96         */
    8997
    9098        atomic_count_t prev = val->count;
    … …  
    101109    REQUIRES_EXTENT_MUTABLE(val)
    102110{
    103         /* On real hardware the retrieving of the original
    104            value and storing 1 have to be done as a single
    105            atomic action. */
     111        /*
     112         * On real hardware the retrieving of the original
     113         * value and storing 1 have to be done as a single
     114         * atomic action.
     115         */
    106116
    107117        atomic_count_t prev = val->count;

  • kernel/arch/abs32le/include/arch/istate.h

    rfac0ac7 r7c3fb9b  
    6565    REQUIRES_EXTENT_MUTABLE(istate)
    6666{
    67         /* On real hardware this checks whether the interrupted
    68            context originated from user space. */
     67        /*
     68         * On real hardware this checks whether the interrupted
     69         * context originated from user space.
     70         */
    6971
    7072        return !(istate->ip & UINT32_C(0x80000000));

  • kernel/arch/abs32le/src/userspace.c

    rfac0ac7 r7c3fb9b  
    4141void userspace(uspace_arg_t *kernel_uarg)
    4242{
    43         /* On real hardware this switches the CPU to user
    44            space mode and jumps to kernel_uarg->uspace_entry. */
     43        /*
     44         * On real hardware this switches the CPU to user
     45         * space mode and jumps to kernel_uarg->uspace_entry.
     46         */
    4547
    4648        while (true)

  • kernel/arch/amd64/include/arch/boot/memmap_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2016 Jakub Jermar
     1/*
     2 * Copyright (c) 2016 Jakub Jermar
    23 * All rights reserved.
    34 *

  • kernel/arch/amd64/include/arch/context_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *
    … …  
    4647
    4748typedef struct context {
    48         /* We include only registers that must be preserved
     49        /*
     50         * We include only registers that must be preserved
    4951         * during function call.
    5052         */

  • kernel/arch/amd64/include/arch/istate_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights reserved.
    34 *

  • kernel/arch/amd64/include/arch/kseg_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2016 Jakub Jermar
     1/*
     2 * Copyright (c) 2016 Jakub Jermar
    23 * All rights reserved.
    34 *

  • kernel/arch/amd64/src/fpu_context.c

    rfac0ac7 r7c3fb9b  
    5757{
    5858        /* TODO: Zero all SSE, MMX etc. registers */
    59         /* Default value of SCR register is 0x1f80,
    60          * it masks all FPU exceptions*/
     59        /*
     60         * Default value of SCR register is 0x1f80,
     61         * it masks all FPU exceptions
     62         */
    6163        asm volatile (
    6264            "fninit\n"

  • kernel/arch/amd64/src/kseg.c

    rfac0ac7 r7c3fb9b  
    4242 * Allocate and initialize a per-CPU structure to be accessible via the
    4343 * GS_KERNEL segment register.
    44  **/
     44 */
    4545void kseg_init(void)
    4646{

  • kernel/arch/amd64/src/pm.c

    rfac0ac7 r7c3fb9b  
    268268                tss_p = &tss;
    269269        } else {
    270                 /* We are going to use malloc, which may return
     270                /*
     271                 * We are going to use malloc, which may return
    271272                 * non boot-mapped pointer, initialize the CR3 register
    272                  * ahead of page_init */
     273                 * ahead of page_init
     274                 */
    273275                write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
    274276

  • kernel/arch/amd64/src/syscall.c

    rfac0ac7 r7c3fb9b  
    5252        /* Setup syscall entry address */
    5353
    54         /* This is _mess_ - the 64-bit CS is argument + 16,
     54        /*
     55         * This is _mess_ - the 64-bit CS is argument + 16,
    5556         * the SS is argument + 8. The order is:
    5657         * +0(KDATA_DES), +8(UDATA_DES), +16(UTEXT_DES)
    … …  
    6061            ((uint64_t) (GDT_SELECTOR(KTEXT_DES) | PL_KERNEL) << 32));
    6162        write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
    62         /* Mask RFLAGS on syscall
     63        /*
     64         * Mask RFLAGS on syscall
    6365         * - disable interrupts, until we exchange the stack register
    6466         *   (mask the IF bit)

  • kernel/arch/arm32/include/arch/context_struct.h

    rfac0ac7 r7c3fb9b  
    3434// XXX: This struct must match assembly code in src/context.S
    3535
    36 /* Thread context containing registers that must be preserved across
     36/*
     37 * Thread context containing registers that must be preserved across
    3738 * function calls.
    3839 */

  • kernel/arch/arm32/include/arch/fpu_context.h

    rfac0ac7 r7c3fb9b  
    4242#define FPU_CONTEXT_ALIGN    8
    4343
    44 /* ARM Architecture reference manual, p B-1529.
     44/*
     45 * ARM Architecture reference manual, p B-1529.
    4546 */
    4647typedef struct {

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    rfac0ac7 r7c3fb9b  
    6464        unsigned should_be_zero : 1;
    6565
    66         /* Pointer to the coarse 2nd level page table (holding entries for small
     66        /*
     67         * Pointer to the coarse 2nd level page table (holding entries for small
    6768         * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
    6869         * tables that may hold even tiny pages (1KB) but they are bigger (4KB
    … …  
    8081        unsigned cacheable : 1;
    8182
    82         /* access permissions for each of 4 subparts of a page
    83          * (for each 1KB when small pages used */
     83        /*
     84         * access permissions for each of 4 subparts of a page
     85         * (for each 1KB when small pages used
     86         */
    8487        unsigned access_permission_0 : 2;
    8588        unsigned access_permission_1 : 2;

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    rfac0ac7 r7c3fb9b  
    6666        unsigned should_be_zero_1 : 1;
    6767
    68         /* Pointer to the coarse 2nd level page table (holding entries for small
     68        /*
     69         * Pointer to the coarse 2nd level page table (holding entries for small
    6970         * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
    7071         * tables that may hold even tiny pages (1KB) but they are bigger (4KB
    … …  
    279280        }
    280281
    281         /* Shareable is ignored for devices (non-cacheable),
    282          * turn it off for normal memory. */
     282        /*
     283         * Shareable is ignored for devices (non-cacheable),
     284         * turn it off for normal memory.
     285         */
    283286        p->shareable = 0;
    284287

  • kernel/arch/arm32/src/cpu/cpu.c

    rfac0ac7 r7c3fb9b  
    147147        /* Unaligned access is supported on armv6+ */
    148148#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
    149         /* Enable unaligned access, RAZ/WI prior to armv6
     149        /*
     150         * Enable unaligned access, RAZ/WI prior to armv6
    150151         * switchable on armv6, RAO/WI writes on armv7,
    151152         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    152          * L.3.1 (p. 2456) */
     153         * L.3.1 (p. 2456)
     154         */
    153155        control_reg |= SCTLR_UNALIGNED_EN_FLAG;
    154         /* Disable alignment checks, this turns unaligned access to undefined,
    155          * unless U bit is set. */
     156        /*
     157         * Disable alignment checks, this turns unaligned access to undefined,
     158         * unless U bit is set.
     159         */
    156160        control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
    157         /* Enable caching, On arm prior to armv7 there is only one level
     161        /*
     162         * Enable caching, On arm prior to armv7 there is only one level
    158163         * of caches. Data cache is coherent.
    159164         * "This means that the behavior of accesses from the same observer to
    … …  
    169174#endif
    170175#ifdef PROCESSOR_ARCH_armv7_a
    171         /* ICache coherency is elaborated on in barrier.h.
     176        /*
     177         * ICache coherency is elaborated on in barrier.h.
    172178         * VIPT and PIPT caches need maintenance only on code modify,
    173179         * so it should be safe for general use.

  • kernel/arch/arm32/src/exception.c

    rfac0ac7 r7c3fb9b  
    6666static void install_handler(unsigned handler_addr, unsigned *vector)
    6767{
    68         /* relative address (related to exc. vector) of the word
     68        /*
     69         * Relative address (related to exc. vector) of the word
    6970         * where handler's address is stored
    7071         */
    … …  
    7273            PREFETCH_OFFSET;
    7374
    74         /* make it LDR instruction and store at exception vector */
     75        /* Make it LDR instruction and store at exception vector */
    7576        *vector = handler_address_ptr | LDR_OPCODE;
    7677        smc_coherence(vector);
    7778
    78         /* store handler's address */
     79        /* Store handler's address */
    7980        *(vector + EXC_VECTORS) = handler_addr;
    8081

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    rfac0ac7 r7c3fb9b  
    106106        omap_irc_init(beagleboard.irc_addr);
    107107
    108         /* Initialize timer. Use timer1, because it is in WKUP power domain
    109          * (always on) and has special capabilities for precise 1ms ticks */
     108        /*
     109         * Initialize timer. Use timer1, because it is in WKUP power domain
     110         * (always on) and has special capabilities for precise 1ms ticks
     111         */
    110112        amdm37x_gpt_timer_ticks_init(&beagleboard.timer,
    111113            AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ);
    … …  
    161163        }
    162164        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
    163          * of ISR. DO this to avoid strange behavior. */
     165         * of ISR. DO this to avoid strange behavior.
     166         */
    164167        omap_irc_irq_ack(beagleboard.irc_addr);
    165168}

  • kernel/arch/arm32/src/mm/page_fault.c

    rfac0ac7 r7c3fb9b  
    153153        }
    154154
    155         /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
    156          * A5.3 (PDF p. 206) */
     155        /*
     156         * See ARM Architecture reference manual ARMv7-A and ARMV7-R edition
     157         * A5.3 (PDF p. 206)
     158         */
    157159        static const struct {
    158160                uint32_t mask;

  • kernel/arch/ia32/include/arch/boot/memmap_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *

  • kernel/arch/ia32/include/arch/context_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *

  • kernel/arch/ia32/include/arch/istate_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *

  • kernel/arch/ia32/src/smp/smp.c

    rfac0ac7 r7c3fb9b  
    156156                 */
    157157
    158                 /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
     158                /*
     159                 * XXX Flag FRAME_LOW_4_GiB was removed temporarily,
    159160                 * it needs to be replaced by a generic fuctionality of
    160161                 * the memory subsystem

  • kernel/arch/ia64/include/arch/context_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *

  • kernel/arch/ia64/include/arch/istate_struct.h

    rfac0ac7 r7c3fb9b  
    1 /* Copyright (c) 2014 Jakub Jermar
     1/*
     2 * Copyright (c) 2014 Jakub Jermar
    23 * All rights preserved.
    34 *

  • kernel/arch/mips32/include/arch/atomic.h

    rfac0ac7 r7c3fb9b  
    4747#define atomic_predec(x)  atomic_add(x, -1)
    4848
    49 /* Atomic addition of immediate value.
     49/** Atomic addition of immediate value.
    5050 *
    5151 * @param val Memory location to which will be the immediate value added.
    … …  
    5353 *
    5454 * @return Value after addition.
    55  *
    5655 */
    5756NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,

  • kernel/arch/mips32/src/exception.c

    rfac0ac7 r7c3fb9b  
    132132        debugger_bpoint(istate);
    133133#else
    134         /* it is necessary to not re-execute BREAK instruction after
    135            returning from Exception handler
    136            (see page 138 in R4000 Manual for more information) */
     134        /*
     135         * It is necessary to not re-execute BREAK instruction after
     136         * returning from Exception handler
     137         * (see page 138 in R4000 Manual for more information)
     138         */
    137139        istate->epc += 4;
    138140#endif

  • kernel/arch/mips32/src/mips32.c

    rfac0ac7 r7c3fb9b  
    4949#include <arch/machine_func.h>
    5050
    51 /* Size of the code jumping to the exception handler code
     51/*
     52 * Size of the code jumping to the exception handler code
    5253 * - J+NOP
    5354 */
    … …  
    7071arch_ops_t *arch_ops = &mips32_ops;
    7172
    72 /* Why the linker moves the variable 64K away in assembler
     73/*
     74 * Why the linker moves the variable 64K away in assembler
    7375 * when not in .text section?
    7476 */

  • kernel/arch/mips32/src/mm/frame.c

    rfac0ac7 r7c3fb9b  
    243243
    244244#if defined(MACHINE_lmalta) || defined(MACHINE_bmalta)
    245         /* Blacklist memory regions used by YAMON.
     245        /*
     246         * Blacklist memory regions used by YAMON.
    246247         *
    247248         * The YAMON User's Manual vaguely says the following physical addresses

  • kernel/arch/ppc32/src/mm/frame.c

    rfac0ac7 r7c3fb9b  
    9393        frame_common_arch_init(true);
    9494
    95         /* First is exception vector, second is 'implementation specific',
    96            third and fourth is reserved, other contain real mode code */
     95        /*
     96         * First is exception vector, second is 'implementation specific',
     97         * third and fourth is reserved, other contain real mode code
     98         */
    9799        frame_mark_unavailable(0, 8);
    98100

  • kernel/arch/sparc64/src/smp/sun4v/smp.c

    rfac0ac7 r7c3fb9b  
    191191
    192192                /*
    193                  * if failed in previous CPUs, don't try
    194                  * to detect physical cores any more
    195                  */
     193                 * if failed in previous CPUs, don't try
     194                 * to detect physical cores any more
     195                 */
    196196                if (exec_unit_assign_error)
    197197                        continue;
    … …  
    250250                            exec_units[i].strand_count : max_core_strands;
    251251
    252                 /* detecting execution unit failed */
     252                        /* detecting execution unit failed */
    253253                } else {
    254254                        exec_unit_assign_error = 1;
    … …  
    260260
    261261        /*
    262          * A fallback code which will be executed if finding out which
    263          * execution units belong to particular CPUs fails. Pretend there
    264          * exists just one execution unit and all CPUs belong to it.
    265          */
     262         * A fallback code which will be executed if finding out which
     263         * execution units belong to particular CPUs fails. Pretend there
     264         * exists just one execution unit and all CPUs belong to it.
     265         */
    266266        if (exec_unit_assign_error) {
    267267                bsp_exec_unit_index = 0;
    … …  
    288288
    289289        /*
    290          * Reorder the execution units array elements and the cpuid array
    291          * elements so that the BSP will always be the very first CPU of
    292          * the very first execution unit.
    293          */
     290         * Reorder the execution units array elements and the cpuid array
     291         * elements so that the BSP will always be the very first CPU of
     292         * the very first execution unit.
     293         */
    294294        exec_unit_t temp_exec_unit = exec_units[0];
    295295        exec_units[0] = exec_units[bsp_exec_unit_index];
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