Changeset 7bdcc45 in mainline for kernel/arch/ia32/src

Timestamp:

2010-12-16T16:38:49Z (15 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7837101

Parents:

8e58f94 (diff), eb221e5 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

kernel/arch/ia32/src

Files:

• bios/bios.c (modified) (2 diffs)
• boot/memmap.c (modified) (1 diff)
• cpu/cpu.c (modified) (2 diffs)
• debug/stacktrace.c (modified) (1 diff)
• drivers/i8254.c (modified) (1 diff)
• drivers/i8259.c (modified) (1 diff)
• drivers/vesa.c (modified) (1 diff)
• ia32.c (modified) (1 diff)
• interrupt.c (modified) (2 diffs)
• mm/frame.c (modified) (1 diff)
• mm/page.c (modified) (1 diff)
• smp/apic.c (modified) (3 diffs)
• smp/mps.c (modified) (1 diff)

kernel/arch/ia32/src/bios/bios.c

@@ -36 +36 @@
 #include <typedefs.h>
 
-#define BIOS_EBDA_PTR  0x40e
+#define BIOS_EBDA_PTR  0x40eU
 
 uintptr_t ebda = 0;
@@ -43 +43 @@
 {
         /* Copy the EBDA address out from BIOS Data Area */
-        ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10;
+        ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U;
 }
 

kernel/arch/ia32/src/boot/memmap.c

@@ -35 +35 @@
 #include <arch/boot/memmap.h>
 
-uint8_t e820counter = 0xff;
+uint8_t e820counter = 0xffU;
 e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS];
 

kernel/arch/ia32/src/cpu/cpu.c

@@ -49 +49 @@
  * Contains only non-MP-Specification specific SMP code.
  */
-#define AMD_CPUID_EBX  0x68747541
-#define AMD_CPUID_ECX  0x444d4163
-#define AMD_CPUID_EDX  0x69746e65
+#define AMD_CPUID_EBX  UINT32_C(0x68747541)
+#define AMD_CPUID_ECX  UINT32_C(0x444d4163)
+#define AMD_CPUID_EDX  UINT32_C(0x69746e65)
 
-#define INTEL_CPUID_EBX  0x756e6547
-#define INTEL_CPUID_ECX  0x6c65746e
-#define INTEL_CPUID_EDX  0x49656e69
+#define INTEL_CPUID_EBX  UINT32_C(0x756e6547)
+#define INTEL_CPUID_ECX  UINT32_C(0x6c65746e)
+#define INTEL_CPUID_EDX  UINT32_C(0x49656e69)
 
 
@@ -140 +140 @@
                 if ((info.cpuid_ebx == AMD_CPUID_EBX)
                     && (info.cpuid_ecx == AMD_CPUID_ECX)
-                        && (info.cpuid_edx == AMD_CPUID_EDX))
+                    && (info.cpuid_edx == AMD_CPUID_EDX))
                         CPU->arch.vendor = VendorAMD;
                 
                 /*
                  * Check for Intel processor.
-                 */             
+                 */
                 if ((info.cpuid_ebx == INTEL_CPUID_EBX)
                     && (info.cpuid_ecx == INTEL_CPUID_ECX)
-                        && (info.cpuid_edx == INTEL_CPUID_EDX))
+                    && (info.cpuid_edx == INTEL_CPUID_EDX))
                         CPU->arch.vendor = VendorIntel;
                 
                 cpuid(INTEL_CPUID_STANDARD, &info);
-                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
-                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
-                CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;                                              
+                CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU;
+                CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU;
+                CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU;
         }
 }

kernel/arch/ia32/src/debug/stacktrace.c

@@ -37 +37 @@
 #include <typedefs.h>
 
-#define FRAME_OFFSET_FP_PREV    0
-#define FRAME_OFFSET_RA         1
+#define FRAME_OFFSET_FP_PREV  0
+#define FRAME_OFFSET_RA       1
 
 bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)

kernel/arch/ia32/src/drivers/i8254.c

@@ -54 +54 @@
 #include <ddi/device.h>
 
-#define CLK_PORT1  ((ioport8_t *) 0x40)
-#define CLK_PORT4  ((ioport8_t *) 0x43)
+#define CLK_PORT1  ((ioport8_t *) 0x40U)
+#define CLK_PORT4  ((ioport8_t *) 0x43U)
 
 #define CLK_CONST     1193180

kernel/arch/ia32/src/drivers/i8259.c

@@ -121 +121 @@
 void pic_eoi(void)
 {
-        pio_write_8((ioport8_t *)0x20, 0x20);
-        pio_write_8((ioport8_t *)0xa0, 0x20);
+        pio_write_8((ioport8_t *) 0x20, 0x20);
+        pio_write_8((ioport8_t *) 0xa0, 0x20);
 }
 

kernel/arch/ia32/src/drivers/vesa.c

@@ -70 +70 @@
 bool vesa_init(void)
 {
-        if ((vesa_width == 0xffff) || (vesa_height == 0xffff))
+        if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU))
                 return false;
         

kernel/arch/ia32/src/ia32.c

@@ -211 +211 @@
  * selector, and the descriptor->base is the correct address.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
         THREAD->arch.tls = addr;

kernel/arch/ia32/src/interrupt.c

@@ -65 +65 @@
 void istate_decode(istate_t *istate)
 {
-        printf("cs =%p\teip=%p\tefl=%p\terr=%p\n",
-            istate->cs, istate->eip, istate->eflags, istate->error_word);
-
-        printf("ds =%p\tes =%p\tfs =%p\tgs =%p\n",
+        printf("cs =%#0" PRIx32 "\teip=%p\t"
+            "efl=%#0" PRIx32 "\terr=%#0" PRIx32 "\n",
+            istate->cs, (void *) istate->eip,
+            istate->eflags, istate->error_word);
+        
+        printf("ds =%#0" PRIx32 "\tes =%#0" PRIx32 "\t"
+            "fs =%#0" PRIx32 "\tgs =%#0" PRIx32 "\n",
             istate->ds, istate->es, istate->fs, istate->gs);
+        
         if (istate_from_uspace(istate))
-                printf("ss =%p\n", istate->ss);
-
-        printf("eax=%p\tebx=%p\tecx=%p\tedx=%p\n",
+                printf("ss =%#0" PRIx32 "\n", istate->ss);
+        
+        printf("eax=%#0" PRIx32 "\tebx=%#0" PRIx32 "\t"
+            "ecx=%#0" PRIx32 "\tedx=%#0" PRIx32 "\n",
             istate->eax, istate->ebx, istate->ecx, istate->edx);
+        
         printf("esi=%p\tedi=%p\tebp=%p\tesp=%p\n",
-            istate->esi, istate->edi, istate->ebp,
-            istate_from_uspace(istate) ? istate->esp : (uintptr_t)&istate->esp);
+            (void *) istate->esi, (void *) istate->edi,
+            (void *) istate->ebp,
+            istate_from_uspace(istate) ? ((void *) istate->esp) :
+            &istate->esp);
 }
 
@@ -139 +147 @@
         );
         
-        fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0.8x.",
-            (unative_t) mxcsr);
-        panic_badtrap(istate, n, "SIMD FP exception, MXCSR=%#0.8x");
+        fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
+            mxcsr);
+        panic_badtrap(istate, n, "SIMD FP exception");
 }
 

kernel/arch/ia32/src/mm/frame.c

@@ -44 +44 @@
 #include <align.h>
 #include <macros.h>
-
 #include <print.h>
 
-#define PHYSMEM_LIMIT32  0x07c000000ull
-#define PHYSMEM_LIMIT64  0x200000000ull
+#define PHYSMEM_LIMIT32  UINT64_C(0x07c000000)
+#define PHYSMEM_LIMIT64  UINT64_C(0x200000000)
 
 size_t hardcoded_unmapped_ktext_size = 0;

kernel/arch/ia32/src/mm/page.c

@@ -82 +82 @@
 {
         if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
-                panic("Unable to map physical memory %p (%d bytes).", physaddr, size);
+                panic("Unable to map physical memory %p (%zu bytes).",
+                    (void *) physaddr, size);
         
         uintptr_t virtaddr = PA2KA(last_frame);

kernel/arch/ia32/src/smp/apic.c

@@ -72 +72 @@
  *
  */
-volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
-volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
+volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
+volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
 
 uint32_t apic_id_mask = 0;
@@ -184 +184 @@
          * Other interrupts will be forwarded to the lowest priority CPU.
          */
-        io_apic_disable_irqs(0xffff);
+        io_apic_disable_irqs(0xffffU);
         
         irq_initialize(&l_apic_timer_irq);
@@ -477 +477 @@
 {
 #ifdef LAPIC_VERBOSE
-        printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n",
+        printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
             CPU->id, l_apic_id());
         

kernel/arch/ia32/src/smp/mps.c

@@ -52 +52 @@
  */
 
-#define FS_SIGNATURE  0x5f504d5f
-#define CT_SIGNATURE  0x504d4350
+#define FS_SIGNATURE  UINT32_C(0x5f504d5f)
+#define CT_SIGNATURE  UINT32_C(0x504d4350)
 
 static struct mps_fs *fs;