Changeset 76cec1e in mainline for arch/mips/src/interrupt.c
- Timestamp:
- 2005-07-15T21:57:30Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- b4a4c5e3
- Parents:
- e41c47e
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips/src/interrupt.c
re41c47e r76cec1e 36 36 pri_t cpu_priority_high(void) 37 37 { 38 39 40 38 pri_t pri = (pri_t) cp0_status_read(); 39 cp0_status_write(pri & ~cp0_status_ie_enabled_bit); 40 return pri; 41 41 } 42 42 43 43 pri_t cpu_priority_low(void) 44 44 { 45 46 47 45 pri_t pri = (pri_t) cp0_status_read(); 46 cp0_status_write(pri | cp0_status_ie_enabled_bit); 47 return pri; 48 48 } 49 49 50 50 void cpu_priority_restore(pri_t pri) 51 51 { 52 52 cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit)); 53 53 } 54 54 55 55 pri_t cpu_priority_read(void) 56 56 { 57 57 return cp0_status_read(); 58 58 } 59 59 … … 85 85 case 7: /* Timer Interrupt */ 86 86 cp0_compare_write(cp0_compare_value); /* clear timer interrupt */ 87 88 cp0_count_write(0); 87 /* start counting over again */ 88 cp0_count_write(0); 89 89 clock(); 90 90 break;
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