Changeset 7328ff4 in mainline for kernel/arch/arm32

Timestamp:

2018-09-06T18:18:52Z (7 years ago)

Author:

Jiří Zárevúcky <jiri.zarevucky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ffa73c6

Parents:

d51cca8

git-author:

Jiří Zárevúcky <jiri.zarevucky@…> (2018-08-13 01:29:17)

git-committer:

Jiří Zárevúcky <jiri.zarevucky@…> (2018-09-06 18:18:52)

Message:

Use builtin memory fences for kernel barriers, and convert smp_coherence() into a regular function

Location:

kernel/arch/arm32

Files:

• Makefile.inc (modified) (1 diff)
• include/arch/barrier.h (modified) (3 diffs)
• include/arch/mm/page.h (modified) (1 diff)
• include/arch/mm/page_armv4.h (modified) (1 diff)
• src/atomic.c (modified) (2 diffs)
• src/mm/tlb.c (modified) (3 diffs)
• src/smc.c (added)

kernel/arch/arm32/Makefile.inc

@@ -57 +57 @@
         arch/$(KARCH)/src/exception.c \
         arch/$(KARCH)/src/userspace.c \
+        arch/$(KARCH)/src/smc.c \
         arch/$(KARCH)/src/debug/stacktrace.c \
         arch/$(KARCH)/src/debug/stacktrace_asm.S \

kernel/arch/arm32/include/arch/barrier.h

@@ -37 +37 @@
 #define KERN_arm32_BARRIER_H_
 
-#ifdef KERNEL
 #include <arch/cache.h>
 #include <arch/cp15.h>
 #include <align.h>
-#else
-#include <libarch/cp15.h>
-#endif
-
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
 #if defined PROCESSOR_ARCH_armv7_a
+
 /*
  * ARMv7 uses instructions for memory barriers see ARM Architecture reference
@@ -57 +51 @@
  * and functionality on armv7 architecture.
  */
-#define memory_barrier()  asm volatile ("dmb" ::: "memory")
-#define read_barrier()    asm volatile ("dsb" ::: "memory")
-#define write_barrier()   asm volatile ("dsb st" ::: "memory")
-#define inst_barrier()    asm volatile ("isb" ::: "memory")
-#elif defined PROCESSOR_ARCH_armv6 | defined KERNEL
+#define dmb()    asm volatile ("dmb" ::: "memory")
+#define dsb()    asm volatile ("dsb" ::: "memory")
+#define isb()    asm volatile ("isb" ::: "memory")
+
+#elif defined PROCESSOR_ARCH_armv6
+
 /*
  * ARMv6 introduced user access of the following commands:
@@ -75 +70 @@
  * CP15 implementation is mandatory only for armv6+.
  */
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-#define memory_barrier()  CP15DMB_write(0)
+#define dmb()    CP15DMB_write(0)
+#define dsb()    CP15DSB_write(0)
+#define isb()    CP15ISB_write(0)
+
 #else
-#define memory_barrier()  CP15DSB_write(0)
-#endif
-#define read_barrier()    CP15DSB_write(0)
-#define write_barrier()   read_barrier()
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-#define inst_barrier()    CP15ISB_write(0)
-#else
-#define inst_barrier()
-#endif
-#else
-/*
- * Older manuals mention syscalls as a way to implement cache coherency and
- * barriers. See for example ARM Architecture Reference Manual Version D
- * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
- */
-// TODO implement on per PROCESSOR basis or via syscalls
-#define memory_barrier()  asm volatile ("" ::: "memory")
-#define read_barrier()    asm volatile ("" ::: "memory")
-#define write_barrier()   asm volatile ("" ::: "memory")
-#define inst_barrier()    asm volatile ("" ::: "memory")
-#endif
 
-#ifdef KERNEL
-
-/*
- * There are multiple ways ICache can be implemented on ARM machines. Namely
- * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
- * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
- * compatibility across processors, ARM recommends that operating systems target
- * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
- * and do not assume the presence of the IVIPT extension. Software that relies
- * on the IVIPT extension might fail in an unpredictable way on an ARMv7
- * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
- * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
- *
- * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
- * maintenance to other places than just smc.
- */
-
-#ifdef KERNEL
-
-/*
- * @note: Cache type register is not available in uspace. We would need
- * to export the cache line value, or use syscall for uspace smc_coherence
- */
-#define smc_coherence(a, l) \
-do { \
-        for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
-            addr += CP15_C7_MVA_ALIGN) \
-                dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
-        write_barrier();               /* Wait for completion */\
-        icache_invalidate();\
-        write_barrier();\
-        inst_barrier();                /* Wait for Inst refetch */\
-} while (0)
+#define dmb()    CP15DSB_write(0)
+#define dsb()    CP15DSB_write(0)
+#define isb()
 
 #endif
-
-#endif  /* KERNEL */
 
 #endif

kernel/arch/arm32/include/arch/mm/page.h

@@ -41 +41 @@
 #include <arch/exception.h>
 #include <barrier.h>
+#include <arch/barrier.h>
 #include <arch/cp15.h>
 #include <trace.h>

kernel/arch/arm32/include/arch/mm/page_armv4.h

@@ -37 +37 @@
 #ifndef KERN_arm32_PAGE_armv4_H_
 #define KERN_arm32_PAGE_armv4_H_
+
+#include <arch/cache.h>
 
 #ifndef KERN_arm32_PAGE_H_

kernel/arch/arm32/src/atomic.c

@@ -35 +35 @@
 
 #include <synch/spinlock.h>
+#include <arch/barrier.h>
 
 
@@ -64 +65 @@
 
         return cur_val;
+}
+
+void __sync_synchronize(void)
+{
+        dsb();
 }
 

kernel/arch/arm32/src/mm/tlb.c

@@ -41 +41 @@
 #include <arch/mm/page.h>
 #include <arch/cache.h>
+#include <arch/barrier.h>
 
 /** Invalidate all entries in TLB.
@@ -59 +60 @@
          * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
          */
-        read_barrier();
-        inst_barrier();
+        dsb();
+        isb();
 }
 
@@ -105 +106 @@
          * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
          */
-        read_barrier();
-        inst_barrier();
+        dsb();
+        isb();
 }