Changeset 6ff23ff in mainline for kernel/arch

Timestamp:

2018-05-17T13:46:56Z (8 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4f8772d4

Parents:

7c3fb9b

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 18:44:36)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 13:46:56)

Message:

More comment fixing (ccheck).

Location:

kernel/arch/arm32

Files:

• include/arch/barrier.h (modified) (4 diffs)
• src/fpu_context.c (modified) (4 diffs)

kernel/arch/arm32/include/arch/barrier.h

@@ -49 +49 @@
 
 #if defined PROCESSOR_ARCH_armv7_a
-/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
+/*
+ * ARMv7 uses instructions for memory barriers see ARM Architecture reference
  * manual for details:
  * DMB: ch. A8.8.43 page A8-376
@@ -69 +70 @@
  * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
  */
-/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
+/*
+ * ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
  * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
  * CP15 implementation is mandatory only for armv6+.
@@ -86 +88 @@
 #endif
 #else
-/* Older manuals mention syscalls as a way to implement cache coherency and
+/*
+ * Older manuals mention syscalls as a way to implement cache coherency and
  * barriers. See for example ARM Architecture Reference Manual Version D
  * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
@@ -123 +126 @@
         inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
-/* @note: Cache type register is not available in uspace. We would need
- * to export the cache line value, or use syscall for uspace smc_coherence */
+/*
+ * @note: Cache type register is not available in uspace. We would need
+ * to export the cache line value, or use syscall for uspace smc_coherence
+ */
 #define smc_coherence_block(a, l) \
 do { \

kernel/arch/arm32/src/fpu_context.c

@@ -117 +117 @@
 static int fpu_have_coprocessor_access(void)
 {
-/*
- * The register containing the information (CPACR) is not available on armv6-
- * rely on user decision to use CONFIG_FPU.
- */
+        /*
+         * The register containing the information (CPACR) is not available
+         * on armv6-. Rely on user decision to use CONFIG_FPU.
+         */
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t cpacr = CPACR_read();
-        /* FPU needs access to coprocessor 10 and 11.
-         * Moreover they need to have same access enabled */
+        /*
+         * FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled
+         */
         if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
             ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
@@ -131 +133 @@
         }
 #endif
+
         return 1;
 }
@@ -147 +150 @@
 static void fpu_enable_coprocessor_access(void)
 {
-/*
- * The register containing the information (CPACR) is not available on armv6-
- * rely on user decision to use CONFIG_FPU.
- */
+        /*
+         * The register containing the information (CPACR) is not available
+         * on armv6-. Rely on user decision to use CONFIG_FPU.
+         */
 #ifdef PROCESSOR_ARCH_armv7_a
         /* Allow coprocessor access */
         uint32_t cpacr = CPACR_read();
-        /* FPU needs access to coprocessor 10 and 11.
-         * Moreover, they need to have same access enabled */
+        /*
+         * FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled
+         */
         cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
         cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
@@ -172 +177 @@
         fpexc_write(0);
         fpu_enable();
-        /* Mask all exception traps,
+        /*
+         * Mask all exception traps,
          * The bits are RAZ/WI on archs that don't support fpu exc traps.
          */