Changeset 69146b93 for kernel – HelenOS

kernel/arch/amd64/Makefile.inc

-              r5d230a30
+              r69146b93
 FPU_NO_CFLAGS = -mno-sse -mno-sse2
+#
+# FIXME:
+#
+# The -fno-optimize-sibling-calls should be removed as soon as a bug
+# in GCC concerning the "large" memory model and tail call optimization
+# is fixed.
+#
+# When GCC generates a code for tail call, instead of generating ..
+#
+#   jmp *fnc
+#
+# it generates an assembly code with an illegal immediate prefix:
+#
+#   jmp *$fnc
+#
+# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48385 for reference.
+#
+CMN1 = -m64 -mcmodel=large -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer -fno-optimize-sibling-calls
+CMN1 = -m64 -mcmodel=large -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer
 GCC_CFLAGS += $(CMN1)
 ICC_CFLAGS += $(CMN1)

kernel/arch/amd64/src/mm/page.c

-              r5d230a30
+              r69146b93
                 access = PF_ACCESS_READ;
+        if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
+                fault_if_from_uspace(istate, "Page fault: %p.", (void *) page);
+                panic_memtrap(istate, access, page, NULL);
+        }
+        as_page_fault(page, access, istate);
+}

kernel/arch/arm32/Makefile.inc

-              r5d230a30
+              r69146b93
 ATSIGN = %
 GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame
+GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
 BITS = 32
 …
 endif
+ifeq ($(MACHINE),beagleboardxm)
+        ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c
+endif
 ifeq ($(CONFIG_PL050),y)
         ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c

kernel/arch/arm32/_link.ld.in

r5d230a30	r69146b93
9	9	#ifdef MACHINE_gta02
10	10	#define KERNEL_LOAD_ADDRESS 0xb0a08000
	11	#elif defined MACHINE_beagleboardxm
	12	#define KERNEL_LOAD_ADDRESS 0x80a00000
11	13	#else
12	14	#define KERNEL_LOAD_ADDRESS 0x80a00000

kernel/arch/arm32/include/asm.h

-              r5d230a30
+              r69146b93
 #include <trace.h>
+/** No such instruction on ARM to sleep CPU. */
+/** No such instruction on old ARM to sleep CPU.
+ *
+ * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
+ * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
+ * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
+ */
 NO_TRACE static inline void cpu_sleep(void)
+{
+#ifdef PROCESSOR_armv7_a
+        asm volatile ( "wfe" :: );
+#elif defined(MACHINE_gta02)
+        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
+#endif
+}

kernel/arch/arm32/include/barrier.h

-              r5d230a30
+              r69146b93
 #define write_barrier()   asm volatile ("" ::: "memory")
+#define smc_coherence(a)
+#define smc_coherence_block(a, l)
+/*
+ * There are multiple ways ICache can be implemented on ARM machines. Namely
+ * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference
+ * Manual B3.11.2 (p. 1383).  However, CortexA8 Manual states: "For maximum
+ * compatibility across processors, ARM recommends that operating systems target
+ * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches,
+ * and do not assume the presence of the IVIPT extension. Software that relies
+ * on the IVIPT extension might fail in an unpredictable way on an ARMv7
+ * implementation that does not include the IVIPT extension." (7.2.6 p. 245).
+ * Only PIPT invalidates cache for all VA aliases if one block is invalidated.
+ *
+ * @note: Supporting ASID and VMID tagged VIVT may need to add ICache
+ * maintenance to other places than just smc.
+ */
+/* Available on both all supported arms,
+ * invalidates entire ICache so the written value does not matter. */
+#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
+#define smc_coherence_block(a, l) smc_coherence(a)
 #endif

kernel/arch/arm32/include/cpu.h

r5d230a30	r69146b93
41	41
42	42
43		/** Struct representing ARM CPU identifiaction. */
	43	/** Struct representing ARM CPU identification. */
44	44	typedef struct {
45	45	/** Implementator (vendor) number. */

kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h

-              r5d230a30
+              r69146b93
 /*
  * Copyright (c) 2011 Martin Sucha
+ * Copyright (c) 2012 Jan Vesely
  * All rights reserved.
+ *
 …
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
+/** @addtogroup arm32beagleboardxm beagleboardxm
+ *  @brief BeagleBoard-xM platform.
+ *  @ingroup arm32
+ * @{
+ */
+/** @file
+ *  @brief BeagleBoard platform driver.
+ */
+/** @addtogroup fs
+ * @{
+ */
+#ifndef KERN_arm32_beagleboardxm_H_
+#define KERN_arm32_beagleboardxm_H_
+#ifndef EXT2FS_EXT2FS_H_
+#define EXT2FS_EXT2FS_H_
+#include <arch/machine_func.h>
+#include <libext2.h>
+#include <libfs.h>
+#include <sys/types.h>
+#define min(a, b)               ((a) < (b) ? (a) : (b))
+extern vfs_out_ops_t ext2fs_ops;
+extern libfs_ops_t ext2fs_libfs_ops;
+extern int ext2fs_global_init(void);
+extern int ext2fs_global_fini(void);
+extern struct arm_machine_ops bbxm_machine_ops;
 #endif
+/**
+ * @}
+/** @}
  */

kernel/arch/arm32/include/machine_func.h

r5d230a30	r69146b93
108	108	extern size_t machine_get_irq_count(void);
109	109
	110	extern const char * machine_get_platform_name(void);
	111
110	112	#endif
111	113

kernel/arch/arm32/include/mm/frame.h

-              r5d230a30
+              r69146b93
 #ifdef MACHINE_gta02
 #define BOOT_PAGE_TABLE_ADDRESS  0x30010000
+#elif defined MACHINE_beagleboardxm
+#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
 #else
 #define BOOT_PAGE_TABLE_ADDRESS  0x00008000
 …
 #ifdef MACHINE_gta02
 #define PHYSMEM_START_ADDR      0x30008000
+#elif defined MACHINE_beagleboardxm
+#define PHYSMEM_START_ADDR      0x80000000
 #else
 #define PHYSMEM_START_ADDR      0x00000000

kernel/arch/arm32/include/mm/page.h

-              r5d230a30
+              r69146b93
 #define PAGE_SIZE       FRAME_SIZE
+#ifdef MACHINE_beagleboardxm
+#ifndef __ASM__
+#       define KA2PA(x) ((uintptr_t) (x))
+#       define PA2KA(x) ((uintptr_t) (x))
+#else
+#       define KA2PA(x) (x)
+#       define PA2KA(x) (x)
+#endif
+#else
 #ifndef __ASM__
 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
 …
 #       define PA2KA(x) ((x) + 0x80000000)
 #endif
+#endif
 /* Number of entries in each level. */
 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
 #define PTL1_ENTRIES_ARCH       0
 #define PTL2_ENTRIES_ARCH       0
+#define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
+#define PTL1_ENTRIES_ARCH       0
+#define PTL2_ENTRIES_ARCH       0
 /* coarse page tables used (256 * 4 = 1KB per page) */
 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
+#define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
 /* Page table sizes for each level. */
 #define PTL0_SIZE_ARCH          FOUR_FRAMES
 #define PTL1_SIZE_ARCH          0
 #define PTL2_SIZE_ARCH          0
 #define PTL3_SIZE_ARCH          ONE_FRAME
+#define PTL0_SIZE_ARCH          FOUR_FRAMES
+#define PTL1_SIZE_ARCH          0
+#define PTL2_SIZE_ARCH          0
+#define PTL3_SIZE_ARCH          ONE_FRAME
 /* Macros calculating indices into page tables for each level. */
 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
 #define PTL1_INDEX_ARCH(vaddr)  0
 #define PTL2_INDEX_ARCH(vaddr)  0
 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
+#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
 /* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
+        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
         (ptl1)
+        (ptl1)
 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
         (ptl2)
+        (ptl2)
 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
+        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
 /* Set PTE address accessors for each level. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
         (set_ptl0_addr((pte_t *) (ptl0)))
+        (set_ptl0_addr((pte_t *) (ptl0)))
 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
+        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
+        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
 /* Get PTE flags accessors for each level. */
 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
+        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
         PAGE_PRESENT
+        PAGE_PRESENT
 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
         PAGE_PRESENT
+        PAGE_PRESENT
 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
+        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
 /* Set PTE flags accessors for each level. */
 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
+        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
 …
         set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
+/* Macros for querying the last-level PTE entries. */
+#define PTE_VALID_ARCH(pte) \
+        (*((uint32_t *) (pte)) != 0)
+#define PTE_PRESENT_ARCH(pte) \
+        (((pte_t *) (pte))->l0.descriptor_type != 0)
+#define PTE_GET_FRAME_ARCH(pte) \
+        (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
+#define PTE_WRITABLE_ARCH(pte) \
+        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
+#define PTE_EXECUTABLE_ARCH(pte) \
+#ifndef __ASM__
+/** Level 0 page table entry. */
+typedef struct {
+        /* 0b01 for coarse tables, see below for details */
+        unsigned descriptor_type : 2;
+        unsigned impl_specific : 3;
+        unsigned domain : 4;
+        unsigned should_be_zero : 1;
+        /* Pointer to the coarse 2nd level page table (holding entries for small
+         * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
+         * tables that may hold even tiny pages (1KB) but they are bigger (4KB
+         * per table in comparison with 1KB per the coarse table)
+         */
+        unsigned coarse_table_addr : 22;
+} ATTRIBUTE_PACKED pte_level0_t;
+/** Level 1 page table entry (small (4KB) pages used). */
+typedef struct {
+        /* 0b10 for small pages */
+        unsigned descriptor_type : 2;
+        unsigned bufferable : 1;
+        unsigned cacheable : 1;
+        /* access permissions for each of 4 subparts of a page
+         * (for each 1KB when small pages used */
+        unsigned access_permission_0 : 2;
+        unsigned access_permission_1 : 2;
+        unsigned access_permission_2 : 2;
+        unsigned access_permission_3 : 2;
+        unsigned frame_base_addr : 20;
+} ATTRIBUTE_PACKED pte_level1_t;
+typedef union {
+        pte_level0_t l0;
+        pte_level1_t l1;
+} pte_t;
+/* Level 1 page tables access permissions */
+/** User mode: no access, privileged mode: no access. */
+#define PTE_AP_USER_NO_KERNEL_NO        0
+/** User mode: no access, privileged mode: read/write. */
+#define PTE_AP_USER_NO_KERNEL_RW        1
+/** User mode: read only, privileged mode: read/write. */
+#define PTE_AP_USER_RO_KERNEL_RW        2
+/** User mode: read/write, privileged mode: read/write. */
+#define PTE_AP_USER_RW_KERNEL_RW        3
+/* pte_level0_t and pte_level1_t descriptor_type flags */
+/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
+#define PTE_DESCRIPTOR_NOT_PRESENT      0
+/** pte_level0_t coarse page table flag (used in descriptor_type). */
+#define PTE_DESCRIPTOR_COARSE_TABLE     1
+/** pte_level1_t small page table flag (used in descriptor type). */
+#define PTE_DESCRIPTOR_SMALL_PAGE       2
+/** Sets the address of level 0 page table.
+ *
+ * @param pt Pointer to the page table to set.
+ *
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+{
+        asm volatile (
+                "mcr p15, 0, %[pt], c2, c0, 0\n"
+                :: [pt] "r" (pt)
+        );
+}
+/** Returns level 0 page table entry flags.
+ *
+ * @param pt Level 0 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
+{
+        pte_level0_t *p = &pt[i].l0;
+        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
+        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
+            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
+            (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
+}
+/** Returns level 1 page table entry flags.
+ *
+ * @param pt Level 1 page table.
+ * @param i  Index of the entry to return.
+ *
+ */
+NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
+{
+        pte_level1_t *p = &pt[i].l1;
+        int dt = p->descriptor_type;
+        int ap = p->access_permission_0;
+        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
+            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
+            ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
+            ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+            ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
+            ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
+            ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
+            (1 << PAGE_EXEC_SHIFT) |
+            (p->bufferable << PAGE_CACHEABLE);
+}
+/** Sets flags of level 0 page table entry.
+ *
+ * @param pt    level 0 page table
+ * @param i     index of the entry to be changed
+ * @param flags new flags
+ *
+ */
+NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
+{
+        pte_level0_t *p = &pt[i].l0;
+        if (flags & PAGE_NOT_PRESENT) {
+                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
+                /*
+                 * Ensures that the entry will be recognized as valid when
+                 * PTE_VALID_ARCH applied.
+                 */
+                p->should_be_zero = 1;
+        } else {
+                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+                p->should_be_zero = 0;
+        }
+}
+NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
+{
+        pte_level0_t *p = &pt[i].l0;
+        p->should_be_zero = 0;
+        write_barrier();
+        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+}
+/** Sets flags of level 1 page table entry.
+ *
+ * We use same access rights for the whole page. When page
+ * is not preset we store 1 in acess_rigts_3 so that at least
+ * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
+ *
+ * @param pt    Level 1 page table.
+ * @param i     Index of the entry to be changed.
+ * @param flags New flags.
+ *
+ */
+NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
+{
+        pte_level1_t *p = &pt[i].l1;
+        if (flags & PAGE_NOT_PRESENT)
+                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
+        else
+                p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
+        /* default access permission */
+        p->access_permission_0 = p->access_permission_1 =
+            p->access_permission_2 = p->access_permission_3 =
+            PTE_AP_USER_NO_KERNEL_RW;
+        if (flags & PAGE_USER)  {
+                if (flags & PAGE_READ) {
+                        p->access_permission_0 = p->access_permission_1 =
+                            p->access_permission_2 = p->access_permission_3 =
+                            PTE_AP_USER_RO_KERNEL_RW;
+                }
+                if (flags & PAGE_WRITE) {
+                        p->access_permission_0 = p->access_permission_1 =
+                            p->access_permission_2 = p->access_permission_3 =
+                            PTE_AP_USER_RW_KERNEL_RW;
+                }
+        }
+}
+NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
+{
+        pte_level1_t *p = &pt[i].l1;
+        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+}
+extern void page_arch_init(void);
+#endif /* __ASM__ */
+#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+#include "page_armv6.h"
+#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#include "page_armv4.h"
+#else
+#error "Unsupported architecture"
+#endif
 #endif

kernel/arch/arm32/include/mm/page_fault.h

-              r5d230a30
+              r69146b93
+/** Decribes CP15 "fault status register" (FSR). */
+typedef struct {
+        unsigned status : 3;
+        unsigned domain : 4;
+        unsigned zero : 1;
+        unsigned should_be_zero : 24;
+} ATTRIBUTE_PACKED fault_status_t;
+/** Help union used for casting integer value into #fault_status_t. */
+/** Decribes CP15 "fault status register" (FSR).
+ *
+ * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743).
+ */
 typedef union {
+        fault_status_t fs;
+        uint32_t dummy;
+} fault_status_union_t;
+        struct {
+                unsigned status : 4;
+                unsigned domain : 4;
+                unsigned zero : 1;
+                unsigned lpae : 1; /**< Needs LPAE support implemented */
+                unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */
+                unsigned wr : 1; /**< armv6+ only */
+                unsigned ext : 1 ; /**< external abort */
+                unsigned cm : 1; /**< Cache maintenance, needs LPAE support */
+                unsigned should_be_zero : 18;
+        } data;
+        struct {
+                unsigned status : 4;
+                unsigned sbz0 : 6;
+                unsigned fs : 1;
+                unsigned should_be_zero : 21;
+        } inst;
+        uint32_t raw;
+} fault_status_t;

kernel/arch/arm32/include/regutils.h

-              r5d230a30
+              r69146b93
 #define STATUS_REG_MODE_MASK         0x1f
+#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
+/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+#define CP15_R1_MMU_EN            (1 << 0)
+#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
+#define CP15_R1_CACHE_EN          (1 << 2)
+#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
+#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
+#define CP15_R1_SWAP_EN           (1 << 10)
+#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
+#define CP15_R1_INST_CACHE_EN     (1 << 12)
+#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
+#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
+#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
+#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
+#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
+#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
+#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
+#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
+#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
+#define CP15_R1_NMFI_EN           (1 << 27)
+#define CP15_R1_TEX_REMAP_EN      (1 << 28)
+#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
+#define CP15_R1_THUMB_EXC_EN      (1 << 30)
 /* ARM Processor Operation Modes */

kernel/arch/arm32/src/arm32.c

-              r5d230a30
+              r69146b93
 #include <str.h>
 #include <arch/ras.h>
+#include <sysinfo/sysinfo.h>
 /** Performs arm32-specific initialization before main_bsp() is called. */
 …
+{
         machine_input_init();
+        const char *platform = machine_get_platform_name();
+        sysinfo_set_item_data("platform", NULL, (void *) platform,
+            str_size(platform));
+}

kernel/arch/arm32/src/cpu/cpu.c

-              r5d230a30
+              r69146b93
 /** Implementators (vendor) names */
 static const char *imp_data[] = {
+        "?",                                    /* IMP_DATA_START_OFFSET */
+        "ARM Ltd",                              /* 0x41 */
+        "",                                     /* 0x42 */
+        "",                                     /* 0x43 */
+        "Digital Equipment Corporation",        /* 0x44 */
+        "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */
+        "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
+        "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
+        "", "", "", "", "", "",                 /* 0x63 - 0x68 */
+        "Intel Corporation"                     /* 0x69 */
+        "?",                                     /* IMP_DATA_START_OFFSET */
+        "ARM Limited",                           /* 0x41 */
+        "", "",                                  /* 0x42 - 0x43 */
+        "Digital Equipment Corporation",         /* 0x44 */
+        "", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
+        "Motorola, Freescale Semicondutor Inc.", /* 0x4d */
+        "", "", "",                              /* 0x4e - 0x50 */
+        "Qualcomm Inc.",                         /* 0x51 */
+        "", "", "", "",                          /* 0x52 - 0x55 */
+        "Marvell Semiconductor",                 /* 0x56 */
+        "", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
+        "", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
+        "Intel Corporation"                      /* 0x69 */
 };
 …
+}
 /** Does nothing on ARM. */
+/** Enables unaligned access and caching for armv6+ */
 void cpu_arch_init(void)
+{
+#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
+        uint32_t control_reg = 0;
+        asm volatile (
+                "mrc p15, 0, %[control_reg], c1, c0"
+                : [control_reg] "=r" (control_reg)
+        );
+        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
+        control_reg &= ~CP15_R1_TEX_REMAP_EN;
+        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
+        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+        /* Enable unaligned access, RAZ ignores writes prior to armv6
+         * switchable on armv6, RAO ignores writes on armv7,
+         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
+         * L.3.1 (p. 2456) */
+        control_reg |= CP15_R1_UNALIGNED_EN;
+        /* Disable alignment checks, this turns unaligned access to undefined,
+         * unless U bit is set. */
+        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
+        /* Enable caching, On arm prior to armv7 there is only one level
+         * of caches. Data cache is coherent.
+         * "This means that the behavior of accesses from the same observer to
+         * different VAs, that are translated to the same PA
+         * with the same memory attributes, is fully coherent."
+         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
+         *    B3.11.1 (p. 1383)
+         * ICache coherency is elaborate on in barrier.h.
+         * We are safe to turn these on.
+         */
+        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
+        asm volatile (
+                "mcr p15, 0, %[control_reg], c1, c0"
+                :: [control_reg] "r" (control_reg)
+        );
+#endif
+}
 /** Retrieves processor identification and stores it to #CPU.arch */
 void cpu_identify(void)
+void cpu_identify(void)
+{
         arch_cpu_identify(&CPU->arch);
 …
         cpu_arch_t * cpu_arch = &m->arch;
+        if ((cpu_arch->imp_num) > 0 &&
+            (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
+        const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
+        if (imp_offset < imp_data_length) {
                 vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
+        }
         if ((cpu_arch->arch_num) > 0 &&
             (cpu_arch->arch_num < arch_data_length)) {
+        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
+        if (cpu_arch->arch_num < arch_data_length) {
                 architecture = arch_data[cpu_arch->arch_num];
+        }

kernel/arch/arm32/src/exception.c

-              r5d230a30
+              r69146b93
 #ifdef HIGH_EXCEPTION_VECTORS
+/** Activates use of high exception vectors addresses. */
+/** Activates use of high exception vectors addresses.
+ *
+ * "High vectors were introduced into some implementations of ARMv4 and are
+ * required in ARMv6 implementations. High vectors allow the exception vector
+ * locations to be moved from their normal address range 0x00000000-0x0000001C
+ * at the bottom of the 32-bit address space, to an alternative address range
+ * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative
+ * locations are known as the high vectors.
+ *
+ * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are
+ * supported. When they are, a hardware configuration input selects whether
+ * the normal vectors or the high vectors are to be used from
+ * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF).
+ *
+ * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42)
+ * say that armv4 an armv5 chips that we support implement this.
+ */
 static void high_vectors(void)
+{
+        uint32_t control_reg;
+        uint32_t control_reg = 0;
         asm volatile (
                 "mrc p15, 0, %[control_reg], c1, c0"
 …
         /* switch on the high vectors bit */
         control_reg |= CP15_R1_HIGH_VECTORS_BIT;
+        control_reg |= CP15_R1_HIGH_VECTORS_EN;
         asm volatile (
 …
 void exception_init(void)
+{
+        // TODO check for availability of high vectors for <= armv5
 #ifdef HIGH_EXCEPTION_VECTORS
         high_vectors();

kernel/arch/arm32/src/machine_func.c

-              r5d230a30
+              r69146b93
 #include <arch/mach/integratorcp/integratorcp.h>
 #include <arch/mach/testarm/testarm.h>
+#include <arch/mach/beagleboardxm/beagleboardxm.h>
 /** Pointer to machine_ops structure being used. */
 …
 #elif defined(MACHINE_integratorcp)
         machine_ops = &icp_machine_ops;
+#elif defined(MACHINE_beagleboardxm)
+        machine_ops = &bbxm_machine_ops;
 #else
 #error Machine type not defined.
 …
+}
+const char * machine_get_platform_name(void)
+{
+        if (machine_ops->machine_get_platform_name)
+                return machine_ops->machine_get_platform_name();
+        return NULL;
+}
 /** @}
  */

kernel/arch/arm32/src/mm/page.c

-              r5d230a30
+              r69146b93
 void page_arch_init(void)
+{
         int flags = PAGE_CACHEABLE;
+        int flags = PAGE_CACHEABLE | PAGE_EXEC;
         page_mapping_operations = &pt_mapping_operations;
         page_table_lock(AS_KERNEL, true);
-        uintptr_t cur;
         /* Kernel identity mapping */
+        for (cur = PHYSMEM_START_ADDR;
+            cur < min(config.identity_size, config.physmem_end);
+        //FIXME: We need to consider the possibility that
+        //identity_base > identity_size and physmem_end.
+        //This might lead to overflow if identity_size is too big.
+        for (uintptr_t cur = PHYSMEM_START_ADDR;
+            cur < min(KA2PA(config.identity_base) +
+                config.identity_size, config.physmem_end);
             cur += FRAME_SIZE)
                 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);

kernel/arch/arm32/src/mm/page_fault.c

-              r5d230a30
+              r69146b93
 #include <print.h>
+/** Returns value stored in fault status register.
+/**
+ * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition.
+ *
+ * B3.13.3 page B3-1406 (PDF page 1406)
+ */
+typedef enum {
+        DFSR_SOURCE_ALIGN = 0x0001,
+        DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004,
+        DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c,
+        DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e,
+        DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c,
+        DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e,
+        DFSR_SOURCE_TRANSLATION_L1 = 0x0005,
+        DFSR_SOURCE_TRANSLATION_L2 = 0x0007,
+        DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003,  /**< @note: This used to be alignment enc. */
+        DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006,
+        DFSR_SOURCE_DOMAIN_L1 = 0x0009,
+        DFSR_SOURCE_DOMAIN_L2 = 0x000b,
+        DFSR_SOURCE_PERMISSION_L1 = 0x000d,
+        DFSR_SOURCE_PERMISSION_L2 = 0x000f,
+        DFSR_SOURCE_DEBUG = 0x0002,
+        DFSR_SOURCE_SYNC_EXTERNAL = 0x0008,
+        DFSR_SOURCE_TLB_CONFLICT = 0x0400,
+        DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */
+        DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */
+        DFSR_SOURCE_SYNC_PARITY = 0x0409,
+        DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406,
+        DFSR_SOURCE_ASYNC_PARITY = 0x0408,
+        DFSR_SOURCE_MASK = 0x0000040f,
+} dfsr_source_t;
+static inline const char * dfsr_source_to_str(dfsr_source_t source)
+{
+        switch (source) {
+        case DFSR_SOURCE_TRANSLATION_L1:
+                return "Translation fault L1";
+        case DFSR_SOURCE_TRANSLATION_L2:
+                return "Translation fault L2";
+        case DFSR_SOURCE_PERMISSION_L1:
+                return "Permission fault L1";
+        case DFSR_SOURCE_PERMISSION_L2:
+                return "Permission fault L2";
+        case DFSR_SOURCE_ALIGN:
+                return "Alignment fault";
+        case DFSR_SOURCE_CACHE_MAINTENANCE:
+                return "Instruction cache maintenance fault";
+        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
+                return "Synchronous external abort on translation table walk level 1";
+        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
+                return "Synchronous external abort on translation table walk level 2";
+        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
+                return "Synchronous parity error on translation table walk level 1";
+        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
+                return "Synchronous parity error on translation table walk level 2";
+        case DFSR_SOURCE_ACCESS_FLAG_L1:
+                return "Access flag fault L1";
+        case DFSR_SOURCE_ACCESS_FLAG_L2:
+                return "Access flag fault L2";
+        case DFSR_SOURCE_DOMAIN_L1:
+                return "Domain fault L1";
+        case DFSR_SOURCE_DOMAIN_L2:
+                return "Domain flault L2";
+        case DFSR_SOURCE_DEBUG:
+                return "Debug event";
+        case DFSR_SOURCE_SYNC_EXTERNAL:
+                return "Synchronous external abort";
+        case DFSR_SOURCE_TLB_CONFLICT:
+                return "TLB conflict abort";
+        case DFSR_SOURCE_LOCKDOWN:
+                return "Lockdown (Implementation defined)";
+        case DFSR_SOURCE_COPROCESSOR:
+                return "Coprocessor abort (Implementation defined)";
+        case DFSR_SOURCE_SYNC_PARITY:
+                return "Synchronous parity error on memory access";
+        case DFSR_SOURCE_ASYNC_EXTERNAL:
+                return "Asynchronous external abort";
+        case DFSR_SOURCE_ASYNC_PARITY:
+                return "Asynchronous parity error on memory access";
+        case DFSR_SOURCE_MASK:
+                break;
+        }
+        return "Unknown data abort";
+}
+/** Returns value stored in comnbined/data fault status register.
+ *
  *  @return Value stored in CP15 fault status register (FSR).
+ */
+static inline fault_status_t read_fault_status_register(void)
+{
+        fault_status_union_t fsu;
+ *
+ *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
+ *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
+ *  the architecture. A write flag (bit[11] of the DFSR) has also been
+ *  introduced."
+ *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
+ *
+ *  See ch. B4.9.6 for location of data/instruction FSR.
+ *
+ */
+static inline fault_status_t read_data_fault_status_register(void)
+{
+        fault_status_t fsu;
         /* fault status is stored in CP15 register 5 */
+        /* Combined/Data fault status is stored in CP15 register 5, c0. */
         asm volatile (
                 "mrc p15, 0, %[dummy], c5, c0, 0"
                 : [dummy] "=r" (fsu.dummy)
+                : [dummy] "=r" (fsu.raw)
         );
+        return fsu.fs;
+}
+/** Returns FAR (fault address register) content.
+ *
+ * @return FAR (fault address register) content (address that caused a page
+        return fsu;
+}
+/** Returns DFAR (fault address register) content.
+ *
+ * This register is equivalent to FAR on pre armv6 machines.
+ *
+ * @return DFAR (fault address register) content (address that caused a page
  *         fault)
  */
 static inline uintptr_t read_fault_address_register(void)
+static inline uintptr_t read_data_fault_address_register(void)
+{
         uintptr_t ret;
 …
+}
+#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
 /** Decides whether read or write into memory is requested.
+ *
 …
                 panic("page_fault - instruction does not access memory "
                     "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
                     instr_union.pc, (void *) badvaddr);
+                    *(uint32_t*)instr_union.instr, (void *) badvaddr);
                 return PF_ACCESS_EXEC;
+        }
 …
             inst, (void *) badvaddr);
+}
+#endif
 /** Handles "data abort" exception (load or store at invalid address).
 …
 void data_abort(unsigned int exc_no, istate_t *istate)
+{
+        fault_status_t fsr __attribute__ ((unused)) =
+            read_fault_status_register();
+        uintptr_t badvaddr = read_fault_address_register();
+        pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
+        int ret = as_page_fault(badvaddr, access, istate);
+        if (ret == AS_PF_FAULT) {
+                fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
+                panic_memtrap(istate, access, badvaddr, NULL);
+        const uintptr_t badvaddr = read_data_fault_address_register();
+        const fault_status_t fsr = read_data_fault_status_register();
+        const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
+        switch (source) {
+        case DFSR_SOURCE_TRANSLATION_L1:
+        case DFSR_SOURCE_TRANSLATION_L2:
+        case DFSR_SOURCE_PERMISSION_L1:
+        case DFSR_SOURCE_PERMISSION_L2:
+                /* Page fault is handled further down */
+                break;
+        case DFSR_SOURCE_ALIGN:
+        case DFSR_SOURCE_CACHE_MAINTENANCE:
+        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1:
+        case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2:
+        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1:
+        case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2:
+        case DFSR_SOURCE_ACCESS_FLAG_L1:
+        case DFSR_SOURCE_ACCESS_FLAG_L2:
+        case DFSR_SOURCE_DOMAIN_L1:
+        case DFSR_SOURCE_DOMAIN_L2:
+        case DFSR_SOURCE_DEBUG:
+        case DFSR_SOURCE_SYNC_EXTERNAL:
+        case DFSR_SOURCE_TLB_CONFLICT:
+        case DFSR_SOURCE_LOCKDOWN:
+        case DFSR_SOURCE_COPROCESSOR:
+        case DFSR_SOURCE_SYNC_PARITY:
+        case DFSR_SOURCE_ASYNC_EXTERNAL:
+        case DFSR_SOURCE_ASYNC_PARITY:
+        case DFSR_SOURCE_MASK:
+                /* Weird abort stuff */
+                fault_if_from_uspace(istate, "Unhandled abort %s at address: "
+                    "%#x.", dfsr_source_to_str(source), badvaddr);
+                panic("Unhandled abort %s at address: %#x.",
+                    dfsr_source_to_str(source), badvaddr);
+        }
+#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+        const pf_access_t access =
+            fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
+#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+        const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
+#else
+#error "Unsupported architecture"
+#endif
+        as_page_fault(badvaddr, access, istate);
+}
 …
 void prefetch_abort(unsigned int exc_no, istate_t *istate)
+{
+        int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
+        if (ret == AS_PF_FAULT) {
+                fault_if_from_uspace(istate,
+                    "Page fault - prefetch_abort: %#x.", istate->pc);
+                panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL);
+        }
+        as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
+}

kernel/arch/ia64/include/mm/as.h

r5d230a30	r69146b93
43	43	#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xdfffffffffffffff)
44	44
45		~~#define USTACK_ADDRESS_ARCH UINT64_C(0x0000000ff0000000)~~
46
47	45	typedef struct {
48	46	} as_arch_t;

kernel/arch/ia64/src/mm/tlb.c

-              r5d230a30
+              r69146b93
         va = page;
         rr.word = rr_read(VA2VRN(va));
         if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
+        rr.word = rr_read(VA2VRN(page));
+        if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) {
                 /*
                  * The selected region register does not contain required RID.
 …
                 rr0 = rr;
                 rr0.map.rid = ASID2RID(asid, VA2VRN(va));
                 rr_write(VA2VRN(va), rr0.word);
+                rr0.map.rid = ASID2RID(asid, VA2VRN(page));
+                rr_write(VA2VRN(page), rr0.word);
                 srlz_d();
                 srlz_i();
 …
         case 1: /* cnt 4 - 15 */
                 ps = PAGE_WIDTH + 2;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 2: /* cnt 16 - 63 */
                 ps = PAGE_WIDTH + 4;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 3: /* cnt 64 - 255 */
                 ps = PAGE_WIDTH + 6;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 4: /* cnt 256 - 1023 */
                 ps = PAGE_WIDTH + 8;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 5: /* cnt 1024 - 4095 */
                 ps = PAGE_WIDTH + 10;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 6: /* cnt 4096 - 16383 */
                 ps = PAGE_WIDTH + 12;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         case 7: /* cnt 16384 - 65535 */
         case 8: /* cnt 65536 - (256K - 1) */
                 ps = PAGE_WIDTH + 14;
                 va &= ~((1 << ps) - 1);
+                va &= ~((1UL << ps) - 1);
                 break;
         default:
                 ps = PAGE_WIDTH + 18;
                 va &= ~((1 << ps) - 1);
                 break;
+        }
         for (; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
+                va &= ~((1UL << ps) - 1);
+                break;
+        }
+        for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps))
                 asm volatile (
                         "ptc.l %[va], %[ps] ;;"
 …
         if (restore_rr) {
                 rr_write(VA2VRN(va), rr.word);
+                rr_write(VA2VRN(page), rr.word);
                 srlz_d();
                 srlz_i();
 …
                  * Forward the page fault to address space page fault handler.
                  */
+                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+                        fault_if_from_uspace(istate, "Page fault at %p.",
+                            (void *) va);
+                        panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL);
+                }
+                as_page_fault(va, PF_ACCESS_EXEC, istate);
+        }
+}
 …
                  * handler.
                  */
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        fault_if_from_uspace(istate, "Page fault at %p.",
+                            (void *) va);
+                        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL);
+                }
+                as_page_fault(va, PF_ACCESS_READ, istate);
+        }
+}
 …
                 dtc_pte_copy(t);
         } else {
+                if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+                        fault_if_from_uspace(istate, "Page fault at %p.",
+                            (void *) va);
+                        panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL);
+                }
+                as_page_fault(va, PF_ACCESS_WRITE, istate);
+        }
+}
 …
                 itc_pte_copy(t);
         } else {
+                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+                        fault_if_from_uspace(istate, "Page fault at %p.",
+                            (void *) va);
+                        panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL);
+                }
+                as_page_fault(va, PF_ACCESS_EXEC, istate);
+        }
+}
 …
         ASSERT((t) && (t->p));
         ASSERT(!t->w);
+        if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+                fault_if_from_uspace(istate, "Page fault at %p.",
+                    (void *) va);
+                panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL);
+        }
+        as_page_fault(va, PF_ACCESS_WRITE, istate);
+}
 …
                         dtc_pte_copy(t);
         } else {
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        fault_if_from_uspace(istate, "Page fault at %p.",
+                            (void *) va);
+                        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL);
+                }
+                as_page_fault(va, PF_ACCESS_READ, istate);
+        }
+}

kernel/arch/mips32/src/mm/tlb.c

-              r5d230a30
+              r69146b93
 #include <symtab.h>
+static void tlb_refill_fail(istate_t *);
+static void tlb_invalid_fail(istate_t *);
+static void tlb_modified_fail(istate_t *);
+static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
+static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *);
 /** Initialize TLB.
 …
         uintptr_t badvaddr;
         pte_t *pte;
-        int pfrc;
         badvaddr = cp0_badvaddr_read();
         asid = AS->asid;
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
+        if (pte) {
+                /*
+                 * Record access to PTE.
+                 */
+                pte->a = 1;
+                tlb_prepare_entry_hi(&hi, asid, badvaddr);
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
+                    pte->cacheable, pte->pfn);
+                /*
+                 * New entry is to be inserted into TLB
+                 */
+                cp0_entry_hi_write(hi.value);
+                if ((badvaddr / PAGE_SIZE) % 2 == 0) {
+                        cp0_entry_lo0_write(lo.value);
+                        cp0_entry_lo1_write(0);
+                } else {
+                        cp0_entry_lo0_write(0);
+                        cp0_entry_lo1_write(lo.value);
+                }
+        }
+        /*
+         * Record access to PTE.
+         */
+        pte->a = 1;
+        tlb_prepare_entry_hi(&hi, asid, badvaddr);
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+            pte->pfn);
+        /*
+         * New entry is to be inserted into TLB
+         */
+        cp0_entry_hi_write(hi.value);
+        if ((badvaddr / PAGE_SIZE) % 2 == 0) {
+                cp0_entry_lo0_write(lo.value);
+                cp0_entry_lo1_write(0);
+        }
+        else {
+                cp0_entry_lo0_write(0);
+                cp0_entry_lo1_write(lo.value);
+        }
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwr();
+        return;
+fail:
+        tlb_refill_fail(istate);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwr();
+        }
+}
 …
         entry_hi_t hi;
         pte_t *pte;
-        int pfrc;
         badvaddr = cp0_badvaddr_read();
 …
         index.value = cp0_index_read();
+        /*
+         * Fail if the entry is not in TLB.
+         */
+        if (index.p) {
+                printf("TLB entry not found.\n");
+                goto fail;
+        }
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+                }
+        }
+        /*
+         * Read the faulting TLB entry.
+         */
+        tlbr();
+        /*
+         * Record access to PTE.
+         */
+        pte->a = 1;
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
+            pte->pfn);
+        /*
+         * The entry is to be updated in TLB.
+         */
+        if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                cp0_entry_lo0_write(lo.value);
+        else
+                cp0_entry_lo1_write(lo.value);
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwi();
+        return;
+fail:
+        tlb_invalid_fail(istate);
+        ASSERT(!index.p);
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
+        if (pte) {
+                /*
+                 * Read the faulting TLB entry.
+                 */
+                tlbr();
+                /*
+                 * Record access to PTE.
+                 */
+                pte->a = 1;
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d,
+                    pte->cacheable, pte->pfn);
+                /*
+                 * The entry is to be updated in TLB.
+                 */
+                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                        cp0_entry_lo0_write(lo.value);
+                else
+                        cp0_entry_lo1_write(lo.value);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwi();
+        }
+}
 …
         entry_hi_t hi;
         pte_t *pte;
-        int pfrc;
         badvaddr = cp0_badvaddr_read();
 …
          * Fail if the entry is not in TLB.
          */
+        if (index.p) {
+                printf("TLB entry not found.\n");
+                goto fail;
+        }
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+                }
+        }
+        /*
+         * Read the faulting TLB entry.
+         */
+        tlbr();
+        /*
+         * Record access and write to PTE.
+         */
+        pte->a = 1;
+        pte->d = 1;
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
+            pte->pfn);
+        /*
+         * The entry is to be updated in TLB.
+         */
+        if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                cp0_entry_lo0_write(lo.value);
+        else
+                cp0_entry_lo1_write(lo.value);
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwi();
+        return;
+fail:
+        tlb_modified_fail(istate);
+}
+void tlb_refill_fail(istate_t *istate)
+{
+        uintptr_t va = cp0_badvaddr_read();
+        fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
+            (void *) va);
+        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception.");
+}
+void tlb_invalid_fail(istate_t *istate)
+{
+        uintptr_t va = cp0_badvaddr_read();
+        fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
+            (void *) va);
+        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception.");
+}
+void tlb_modified_fail(istate_t *istate)
+{
+        uintptr_t va = cp0_badvaddr_read();
+        fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
+            (void *) va);
+        panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception.");
+        ASSERT(!index.p);
+        pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate);
+        if (pte) {
+                /*
+                 * Read the faulting TLB entry.
+                 */
+                tlbr();
+                /*
+                 * Record access and write to PTE.
+                 */
+                pte->a = 1;
+                pte->d = 1;
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w,
+                    pte->cacheable, pte->pfn);
+                /*
+                 * The entry is to be updated in TLB.
+                 */
+                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                        cp0_entry_lo0_write(lo.value);
+                else
+                        cp0_entry_lo1_write(lo.value);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwi();
+        }
+}
 …
  * @param access        Access mode that caused the fault.
  * @param istate        Pointer to interrupted state.
- * @param pfrc          Pointer to variable where as_page_fault() return code
- *                      will be stored.
+ *
  * @return              PTE on success, NULL otherwise.
  */
+pte_t *
+find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
+    int *pfrc)
+pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate)
+{
         entry_hi_t hi;
 …
         hi.value = cp0_entry_hi_read();
+        /*
+         * Handler cannot succeed if the ASIDs don't match.
+         */
+        if (hi.asid != AS->asid) {
+                printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
+                return NULL;
+        }
+        ASSERT(hi.asid == AS->asid);
         /*
 …
                  */
                 return pte;
+        } else {
+                int rc;
+                /*
+                 * Mapping not found in page tables.
+                 * Resort to higher-level page fault handler.
+                 */
+                switch (rc = as_page_fault(badvaddr, access, istate)) {
+                case AS_PF_OK:
+                        /*
+                         * The higher-level page fault handler succeeded,
+                         * The mapping ought to be in place.
+                         */
+                        pte = page_mapping_find(AS, badvaddr, true);
+                        ASSERT(pte && pte->p);
+                        ASSERT(pte->w || access != PF_ACCESS_WRITE);
+                        return pte;
+                case AS_PF_DEFER:
+                        *pfrc = AS_PF_DEFER;
+                        return NULL;
+                case AS_PF_FAULT:
+                        *pfrc = AS_PF_FAULT;
+                        return NULL;
+                default:
+                        panic("Unexpected rc (%d).", rc);
+                }
+        }
+        }
+        /*
+         * Mapping not found in page tables.
+         * Resort to higher-level page fault handler.
+         */
+        if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
+                pte = page_mapping_find(AS, badvaddr, true);
+                ASSERT(pte && pte->p);
+                ASSERT(pte->w || access != PF_ACCESS_WRITE);
+                return pte;
+        }
+        return NULL;
+}

kernel/arch/mips64/src/mm/tlb.c

-              r5d230a30
+              r69146b93
  * @param access   Access mode that caused the fault.
  * @param istate   Pointer to interrupted state.
- * @param pfrc     Pointer to variable where as_page_fault()
- *                 return code will be stored.
+ *
  * @return PTE on success, NULL otherwise.
 …
  */
 static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access,
     istate_t *istate, int *pfrc)
+    istate_t *istate)
+{
         entry_hi_t hi;
         hi.value = cp0_entry_hi_read();
+        /*
+         * Handler cannot succeed if the ASIDs don't match.
+         */
+        if (hi.asid != AS->asid) {
+                printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
+                return NULL;
+        }
+        ASSERT(hi.asid == AS->asid);
         /*
 …
                  */
                 return pte;
+        } else {
+                int rc;
+                /*
+                 * Mapping not found in page tables.
+                 * Resort to higher-level page fault handler.
+                 */
+                switch (rc = as_page_fault(badvaddr, access, istate)) {
+                case AS_PF_OK:
+                        /*
+                         * The higher-level page fault handler succeeded,
+                         * The mapping ought to be in place.
+                         */
+                        pte = page_mapping_find(AS, badvaddr, true);
+                        ASSERT(pte);
+                        ASSERT(pte->p);
+                        ASSERT((pte->w) || (access != PF_ACCESS_WRITE));
+                        return pte;
+                case AS_PF_DEFER:
+                        *pfrc = AS_PF_DEFER;
+                        return NULL;
+                case AS_PF_FAULT:
+                        *pfrc = AS_PF_FAULT;
+                        return NULL;
+                default:
+                        panic("Unexpected return code (%d).", rc);
+                }
+        }
+        }
+        /*
+         * Mapping not found in page tables.
+         * Resort to higher-level page fault handler.
+         */
+        if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
+                /*
+                 * The higher-level page fault handler succeeded,
+                 * The mapping ought to be in place.
+                 */
+                pte = page_mapping_find(AS, badvaddr, true);
+                ASSERT(pte);
+                ASSERT(pte->p);
+                ASSERT((pte->w) || (access != PF_ACCESS_WRITE));
+                return pte;
+        }
+        return NULL;
+}
 …
+}
-static void tlb_refill_fail(istate_t *istate)
+{
-        uintptr_t va = cp0_badvaddr_read();
-        fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
-            (void *) va);
-        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception.");
+}
-static void tlb_invalid_fail(istate_t *istate)
+{
-        uintptr_t va = cp0_badvaddr_read();
-        fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
-            (void *) va);
-        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception.");
+}
-static void tlb_modified_fail(istate_t *istate)
+{
-        uintptr_t va = cp0_badvaddr_read();
-        fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
-            (void *) va);
-        panic_memtrap(istate, PF_ACCESS_WRITE, va, "TLB Modified Exception.");
+}
 /** Process TLB Refill Exception.
+ *
 …
         mutex_unlock(&AS->lock);
+        int pfrc;
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ,
+            istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
+        if (pte) {
+                /*
+                 * Record access to PTE.
+                 */
+                pte->a = 1;
+                entry_lo_t lo;
+                entry_hi_t hi;
+                tlb_prepare_entry_hi(&hi, asid, badvaddr);
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c,
+                    pte->frame);
+                /*
+                 * New entry is to be inserted into TLB
+                 */
+                cp0_entry_hi_write(hi.value);
+                if ((badvaddr / PAGE_SIZE) % 2 == 0) {
+                        cp0_entry_lo0_write(lo.value);
+                        cp0_entry_lo1_write(0);
+                } else {
+                        cp0_entry_lo0_write(0);
+                        cp0_entry_lo1_write(lo.value);
+                }
+        }
+        /*
+         * Record access to PTE.
+         */
+        pte->a = 1;
+        entry_lo_t lo;
+        entry_hi_t hi;
+        tlb_prepare_entry_hi(&hi, asid, badvaddr);
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c,
+            pte->frame);
+        /*
+         * New entry is to be inserted into TLB
+         */
+        cp0_entry_hi_write(hi.value);
+        if ((badvaddr / PAGE_SIZE) % 2 == 0) {
+                cp0_entry_lo0_write(lo.value);
+                cp0_entry_lo1_write(0);
+        } else {
+                cp0_entry_lo0_write(0);
+                cp0_entry_lo1_write(lo.value);
+        }
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwr();
+        return;
+fail:
+        tlb_refill_fail(istate);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwr();
+        }
+}
 …
         index.value = cp0_index_read();
+        /*
+         * Fail if the entry is not in TLB.
+         */
+        if (index.p) {
+                printf("TLB entry not found.\n");
+                goto fail;
+        }
+        int pfrc;
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ,
+            istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+                }
+        }
+        /*
+         * Read the faulting TLB entry.
+         */
+        tlbr();
+        /*
+         * Record access to PTE.
+         */
+        pte->a = 1;
+        entry_lo_t lo;
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c,
+            pte->frame);
+        /*
+         * The entry is to be updated in TLB.
+         */
+        if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                cp0_entry_lo0_write(lo.value);
+        else
+                cp0_entry_lo1_write(lo.value);
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwi();
+        return;
+fail:
+        tlb_invalid_fail(istate);
+        ASSERT(!index.p);
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);
+        if (pte) {
+                /*
+                 * Read the faulting TLB entry.
+                 */
+                tlbr();
+                /*
+                 * Record access to PTE.
+                 */
+                pte->a = 1;
+                entry_lo_t lo;
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->c,
+                    pte->frame);
+                /*
+                 * The entry is to be updated in TLB.
+                 */
+                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                        cp0_entry_lo0_write(lo.value);
+                else
+                        cp0_entry_lo1_write(lo.value);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwi();
+        }
+}
 …
         index.value = cp0_index_read();
+        /*
+         * Fail if the entry is not in TLB.
+         */
+        if (index.p) {
+                printf("TLB entry not found.\n");
+                goto fail;
+        }
+        int pfrc;
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE,
+            istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        goto fail;
+                        break;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+                }
+        }
+        /*
+         * Read the faulting TLB entry.
+         */
+        tlbr();
+        /*
+         * Record access and write to PTE.
+         */
+        pte->a = 1;
+        pte->d = 1;
+        entry_lo_t lo;
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->c,
+            pte->frame);
+        /*
+         * The entry is to be updated in TLB.
+         */
+        if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                cp0_entry_lo0_write(lo.value);
+        else
+                cp0_entry_lo1_write(lo.value);
+        cp0_pagemask_write(TLB_PAGE_MASK_16K);
+        tlbwi();
+        return;
+fail:
+        tlb_modified_fail(istate);
+        ASSERT(!index.p);
+        pte_t *pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate);
+        if (pte) {
+                /*
+                 * Read the faulting TLB entry.
+                 */
+                tlbr();
+                /*
+                 * Record access and write to PTE.
+                 */
+                pte->a = 1;
+                pte->d = 1;
+                entry_lo_t lo;
+                tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->c,
+                    pte->frame);
+                /*
+                 * The entry is to be updated in TLB.
+                 */
+                if ((badvaddr / PAGE_SIZE) % 2 == 0)
+                        cp0_entry_lo0_write(lo.value);
+                else
+                        cp0_entry_lo1_write(lo.value);
+                cp0_pagemask_write(TLB_PAGE_MASK_16K);
+                tlbwi();
+        }
+}

kernel/arch/ppc32/src/mm/pht.c

-              r5d230a30
+              r69146b93
  * @param access   Access mode that caused the fault.
  * @param istate   Pointer to interrupted state.
- * @param pfrc     Pointer to variable where as_page_fault() return code
- *                 will be stored.
+ *
  * @return PTE on success, NULL otherwise.
 …
  */
 static pte_t *find_mapping_and_check(as_t *as, uintptr_t badvaddr, int access,
     istate_t *istate, int *pfrc)
+    istate_t *istate)
+{
         /*
 …
                  */
                 return pte;
+        } else {
+        }
+        /*
+         * Mapping not found in page tables.
+         * Resort to higher-level page fault handler.
+         */
+        if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) {
                 /*
                  * Mapping not found in page tables.
                  * Resort to higher-level page fault handler.
+                 * The higher-level page fault handler succeeded,
+                 * The mapping ought to be in place.
                  */
+                int rc = as_page_fault(badvaddr, access, istate);
+                switch (rc) {
+                case AS_PF_OK:
+                        /*
+                         * The higher-level page fault handler succeeded,
+                         * The mapping ought to be in place.
+                         */
+                        pte = page_mapping_find(as, badvaddr, true);
+                        ASSERT((pte) && (pte->present));
+                        *pfrc = 0;
+                        return pte;
+                case AS_PF_DEFER:
+                        *pfrc = rc;
+                        return NULL;
+                case AS_PF_FAULT:
+                        *pfrc = rc;
+                        return NULL;
+                default:
+                        panic("Unexpected rc (%d).", rc);
+                }
+        }
+}
+static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate)
+{
+        fault_if_from_uspace(istate, "PHT Refill Exception on %p.",
+            (void *) badvaddr);
+        panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr,
+            "PHT Refill Exception.");
+                pte = page_mapping_find(as, badvaddr, true);
+                ASSERT((pte) && (pte->present));
+                return pte;
+        }
+        return NULL;
+}
 …
                 badvaddr = istate->pc;
-        int pfrc;
         pte_t *pte = find_mapping_and_check(AS, badvaddr,
+            PF_ACCESS_READ /* FIXME */, istate, &pfrc);
+        if (!pte) {
+                switch (pfrc) {
+                case AS_PF_FAULT:
+                        pht_refill_fail(badvaddr, istate);
+                        return;
+                case AS_PF_DEFER:
+                        /*
+                         * The page fault came during copy_from_uspace()
+                         * or copy_to_uspace().
+                         */
+                        return;
+                default:
+                        panic("Unexpected pfrc (%d).", pfrc);
+                }
+        }
+        /* Record access to PTE */
+        pte->accessed = 1;
+        pht_insert(badvaddr, pte);
+            PF_ACCESS_READ /* FIXME */, istate);
+        if (pte) {
+                /* Record access to PTE */
+                pte->accessed = 1;
+                pht_insert(badvaddr, pte);
+        }
+}

kernel/arch/ppc32/src/ppc32.c

r5d230a30	r69146b93
103	103	}
104	104
	105	#ifdef CONFIG_FB
105	106	static bool display_register(ofw_tree_node_t node, void arg)
106	107	{
…	…
169	170	return true;
170	171	}
	172	#endif
171	173
172	174	void arch_post_mm_init(void)

kernel/arch/sparc64/src/mm/sun4u/tlb.c

-              r5d230a30
+              r69146b93
 static void dtlb_pte_copy(pte_t *, size_t, bool);
 static void itlb_pte_copy(pte_t *, size_t);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t,
-    const char *);
-static void do_fast_data_access_mmu_miss_fault(istate_t *, tlb_tag_access_reg_t,
-    const char *);
-static void do_fast_data_access_protection_fault(istate_t *,
-    tlb_tag_access_reg_t, const char *);
 const char *context_encoding[] = {
 …
                  * handler.
                  */
+                if (as_page_fault(page_16k, PF_ACCESS_EXEC, istate) ==
+                    AS_PF_FAULT) {
+                        do_fast_instruction_access_mmu_miss_fault(istate,
+                            istate->tpc, __func__);
+                }
+                as_page_fault(page_16k, PF_ACCESS_EXEC, istate);
+        }
+}
 …
                 if (!tag.vpn) {
                         /* NULL access in kernel */
+                        do_fast_data_access_mmu_miss_fault(istate, tag,
+                            "Dereferencing NULL pointer.");
+                        panic("NULL pointer dereference.");
                 } else if (page_8k >= end_of_identity) {
                         /* Kernel non-identity. */
                         as = AS_KERNEL;
                 } else {
+                        do_fast_data_access_mmu_miss_fault(istate, tag,
+                    "Unexpected kernel page fault.");
+                        panic("Unexpected kernel page fault.");
+                }
+        }
 …
                  * handler.
                  */
+                if (as_page_fault(page_16k, PF_ACCESS_READ, istate) ==
+                    AS_PF_FAULT) {
+                        do_fast_data_access_mmu_miss_fault(istate, tag,
+                            __func__);
+                }
+                as_page_fault(page_16k, PF_ACCESS_READ, istate);
+        }
+}
 …
                  * handler.
                  */
+                if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) ==
+                    AS_PF_FAULT) {
+                        do_fast_data_access_protection_fault(istate, tag,
+                            __func__);
+                }
+                as_page_fault(page_16k, PF_ACCESS_WRITE, istate);
+        }
+}
 …
 #endif
-void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
-    uintptr_t va, const char *str)
+{
-        fault_if_from_uspace(istate, "%s, address=%p.", str, (void *) va);
-        panic_memtrap(istate, PF_ACCESS_EXEC, va, str);
+}
-void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str)
+{
-        uintptr_t va;
-        va = tag.vpn << MMU_PAGE_WIDTH;
-        fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str,
-            (void *) va, tag.context);
-        panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, str);
+}
-void do_fast_data_access_protection_fault(istate_t *istate,
-    tlb_tag_access_reg_t tag, const char *str)
+{
-        uintptr_t va;
-        va = tag.vpn << MMU_PAGE_WIDTH;
-        fault_if_from_uspace(istate, "%s, page=%p (asid=%u).", str,
-            (void *) va, tag.context);
-        panic_memtrap(istate, PF_ACCESS_WRITE, va, str);
+}
 void describe_dmmu_fault(void)

kernel/arch/sparc64/src/mm/sun4v/tlb.c

-              r5d230a30
+              r69146b93
 static void itlb_pte_copy(pte_t *);
 static void dtlb_pte_copy(pte_t *, bool);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *, uintptr_t,
-    const char *);
-static void do_fast_data_access_mmu_miss_fault(istate_t *, uint64_t,
-    const char *);
-static void do_fast_data_access_protection_fault(istate_t *,
-    uint64_t, const char *);
 /*
 …
                  * handler.
                  */
+                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+                        do_fast_instruction_access_mmu_miss_fault(istate,
+                            istate->tpc, __func__);
+                }
+                as_page_fault(va, PF_ACCESS_EXEC, istate);
+        }
+}
 …
                 if (va == 0) {
                         /* NULL access in kernel */
+                        do_fast_data_access_mmu_miss_fault(istate, page_and_ctx,
+                            __func__);
+                        panic("NULL pointer dereference.");
+                }
+                do_fast_data_access_mmu_miss_fault(istate, page_and_ctx, "Unexpected "
+                    "kernel page fault.");
+                panic("Unexpected kernel page fault.");
+        }
 …
                  * handler.
                  */
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        do_fast_data_access_mmu_miss_fault(istate, page_and_ctx,
+                            __func__);
+                }
+                as_page_fault(va, PF_ACCESS_READ, istate);
+        }
+}
 …
                  * handler.
                  */
+                if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+                        do_fast_data_access_protection_fault(istate, page_and_ctx,
+                            __func__);
+                }
+                as_page_fault(va, PF_ACCESS_WRITE, istate);
+        }
+}
 …
+}
-void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, uintptr_t va,
-    const char *str)
+{
-        fault_if_from_uspace(istate, "%s, address=%p.", str,
-            (void *) va);
-        panic_memtrap(istate, PF_ACCESS_EXEC, va, str);
+}
-void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    uint64_t page_and_ctx, const char *str)
+{
-        fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str,
-            (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
-        panic_memtrap(istate, PF_ACCESS_UNKNOWN, DMISS_ADDRESS(page_and_ctx),
-            str);
+}
-void do_fast_data_access_protection_fault(istate_t *istate,
-    uint64_t page_and_ctx, const char *str)
+{
-        fault_if_from_uspace(istate, "%s, page=%p (asid=%" PRId64 ").", str,
-            (void *) DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
-        panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx),
-            str);
+}
 /**
  * Describes the exact condition which caused the last DMMU fault.

kernel/genarch/Makefile.inc

-              r5d230a30
+              r69146b93
 endif
+ifeq ($(CONFIG_AMDM37X_UART),y)
+        GENARCH_SOURCES += \
+                genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
+endif
 ifeq ($(CONFIG_VIA_CUDA),y)
         GENARCH_SOURCES += \

kernel/genarch/src/mm/page_ht.c

-              r5d230a30
+              r69146b93
                 pte->frame = ALIGN_DOWN(frame, FRAME_SIZE);
+                /*
+                 * Make sure that a concurrent ht_mapping_find() will see the
+                 * new entry only after it is fully initialized.
+                 */
                 write_barrier();

kernel/genarch/src/mm/page_pt.c

-              r5d230a30
+              r69146b93
                     PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                /*
+                 * Make sure that a concurrent hardware page table walk or
+                 * pt_mapping_find() will see the new PTL1 only after it is
+                 * fully initialized.
+                 */
                 write_barrier();
                 SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page));
 …
                     PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                /*
+                 * Make the new PTL2 visible only after it is fully initialized.
+                 */
                 write_barrier();
                 SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));
 …
                     PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
                     PAGE_WRITE);
+                /*
+                 * Make the new PTL3 visible only after it is fully initialized.
+                 */
                 write_barrier();
                 SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page));
 …
         SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame);
         SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT);
+        /*
+         * Make the new mapping visible only after it is fully initialized.
+         */
         write_barrier();
         SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page));
 …
 #if (PTL1_ENTRIES != 0)
+        /*
+         * Always read ptl2 only after we are sure it is present.
+         */
         read_barrier();
 #endif
 …
 #if (PTL2_ENTRIES != 0)
+        /*
+         * Always read ptl3 only after we are sure it is present.
+         */
         read_barrier();
 #endif

kernel/generic/include/config.h

r5d230a30	r69146b93
44	44	#define STACK_FRAMES TWO_FRAMES
45	45	#define STACK_SIZE ((1 << STACK_FRAMES) << PAGE_WIDTH)
	46
	47	#define STACK_SIZE_USER (1 * 1024 * 1024)
46	48
47	49	#define CONFIG_INIT_TASKS 32

kernel/generic/include/mm/as.h

-              r5d230a30
+              r69146b93
 #define USER_ADDRESS_SPACE_END      USER_ADDRESS_SPACE_END_ARCH
-#ifdef USTACK_ADDRESS_ARCH
-        #define USTACK_ADDRESS  USTACK_ADDRESS_ARCH
-#else
-        #define USTACK_ADDRESS  (USER_ADDRESS_SPACE_END - (STACK_SIZE - 1))
-#endif
 /** Kernel address space. */
 #define FLAG_AS_KERNEL  (1 << 0)
 …
 #define AS_AREA_ATTR_PARTIAL  1  /**< Not fully initialized area. */
+/** The page fault was resolved by as_page_fault(). */
+#define AS_PF_OK     0
+/** The page fault was caused by memcpy_from_uspace() or memcpy_to_uspace(). */
+#define AS_PF_DEFER  1
 /** The page fault was not resolved by as_page_fault(). */
+#define AS_PF_FAULT  0
+/** The page fault was resolved by as_page_fault(). */
+#define AS_PF_OK  1
+/** The page fault was caused by memcpy_from_uspace() or memcpy_to_uspace(). */
+#define AS_PF_DEFER  2
+#define AS_PF_FAULT  2
+/** The page fault was not resolved by as_page_fault(). Non-verbose version. */
+#define AS_PF_SILENT 3
 /** Address space structure.
 …
         void (* destroy)(as_area_t *);
+        bool (* is_resizable)(as_area_t *);
+        bool (* is_shareable)(as_area_t *);
         int (* page_fault)(as_area_t *, uintptr_t, pf_access_t);
         void (* frame_free)(as_area_t *, uintptr_t, uintptr_t);

kernel/generic/src/console/cmd.c

-              r5d230a30
+              r69146b93
 #include <cpu.h>
 #include <mm/tlb.h>
+#include <mm/km.h>
 #include <arch/mm/tlb.h>
 #include <mm/frame.h>
 …
         .func = cmd_help,
         .argc = 0
+};
+/* Data and methods for pio_read_8 command */
+static int cmd_pio_read_8(cmd_arg_t *argv);
+static cmd_arg_t pio_read_8_argv[] = { { .type = ARG_TYPE_INT } };
+static cmd_info_t pio_read_8_info = {
+        .name = "pio_read_8",
+        .description = "pio_read_8 <address> Read 1 byte from memory (or port).",
+        .func = cmd_pio_read_8,
+        .argc = 1,
+        .argv = pio_read_8_argv
+};
+/* Data and methods for pio_read_16 command */
+static int cmd_pio_read_16(cmd_arg_t *argv);
+static cmd_arg_t pio_read_16_argv[] = { { .type = ARG_TYPE_INT } };
+static cmd_info_t pio_read_16_info = {
+        .name = "pio_read_16",
+        .description = "pio_read_16 <address> Read 2 bytes from memory (or port).",
+        .func = cmd_pio_read_16,
+        .argc = 1,
+        .argv = pio_read_16_argv
+};
+/* Data and methods for pio_read_32 command */
+static int cmd_pio_read_32(cmd_arg_t *argv);
+static cmd_arg_t pio_read_32_argv[] = { { .type = ARG_TYPE_INT } };
+static cmd_info_t pio_read_32_info = {
+        .name = "pio_read_32",
+        .description = "pio_read_32 <address> Read 4 bytes from memory (or port).",
+        .func = cmd_pio_read_32,
+        .argc = 1,
+        .argv = pio_read_32_argv
+};
+/* Data and methods for pio_write_8 command */
+static int cmd_pio_write_8(cmd_arg_t *argv);
+static cmd_arg_t pio_write_8_argv[] = {
+        { .type = ARG_TYPE_INT },
+        { .type = ARG_TYPE_INT }
+};
+static cmd_info_t pio_write_8_info = {
+        .name = "pio_write_8",
+        .description = "pio_write_8 <address> <value> Write 1 byte to memory (or port).",
+        .func = cmd_pio_write_8,
+        .argc = 2,
+        .argv = pio_write_8_argv
+};
+/* Data and methods for pio_write_16 command */
+static int cmd_pio_write_16(cmd_arg_t *argv);
+static cmd_arg_t pio_write_16_argv[] = {
+        { .type = ARG_TYPE_INT },
+        { .type = ARG_TYPE_INT }
+};
+static cmd_info_t pio_write_16_info = {
+        .name = "pio_write_16",
+        .description = "pio_write_16 <address> <value> Write 2 bytes to memory (or port).",
+        .func = cmd_pio_write_16,
+        .argc = 2,
+        .argv = pio_write_16_argv
+};
+/* Data and methods for pio_write_32 command */
+static int cmd_pio_write_32(cmd_arg_t *argv);
+static cmd_arg_t pio_write_32_argv[] = {
+        { .type = ARG_TYPE_INT },
+        { .type = ARG_TYPE_INT }
+};
+static cmd_info_t pio_write_32_info = {
+        .name = "pio_write_32",
+        .description = "pio_write_32 <address> <value> Write 4 bytes to memory (or port).",
+        .func = cmd_pio_write_32,
+        .argc = 2,
+        .argv = pio_write_32_argv
 };
 …
         &btrace_info,
 #endif
+        &pio_read_8_info,
+        &pio_read_16_info,
+        &pio_read_32_info,
+        &pio_write_8_info,
+        &pio_write_16_info,
+        &pio_write_32_info,
         NULL
 };
 …
         spinlock_unlock(&cmd_lock);
+        return 1;
+}
+/** Read 1 byte from phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_read_8(cmd_arg_t *argv)
+{
+        uint8_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t),
+                    PAGE_NOT_CACHEABLE);
+        const uint8_t val = pio_read_8(ptr);
+        printf("read %" PRIxn ": %" PRIx8 "\n", argv[0].intval, val);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint8_t));
+        return 1;
+}
+/** Read 2 bytes from phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_read_16(cmd_arg_t *argv)
+{
+        uint16_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t),
+                    PAGE_NOT_CACHEABLE);
+        const uint16_t val = pio_read_16(ptr);
+        printf("read %" PRIxn ": %" PRIx16 "\n", argv[0].intval, val);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint16_t));
+        return 1;
+}
+/** Read 4 bytes from phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_read_32(cmd_arg_t *argv)
+{
+        uint32_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t),
+                    PAGE_NOT_CACHEABLE);
+        const uint32_t val = pio_read_32(ptr);
+        printf("read %" PRIxn ": %" PRIx32 "\n", argv[0].intval, val);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint32_t));
+        return 1;
+}
+/** Write 1 byte to phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_write_8(cmd_arg_t *argv)
+{
+        uint8_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint8_t *) km_map(argv[0].intval, sizeof(uint8_t),
+                    PAGE_NOT_CACHEABLE);
+        printf("write %" PRIxn ": %" PRIx8 "\n", argv[0].intval,
+            (uint8_t) argv[1].intval);
+        pio_write_8(ptr, (uint8_t) argv[1].intval);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint8_t));
+        return 1;
+}
+/** Write 2 bytes to phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_write_16(cmd_arg_t *argv)
+{
+        uint16_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint16_t *) km_map(argv[0].intval, sizeof(uint16_t),
+                    PAGE_NOT_CACHEABLE);
+        printf("write %" PRIxn ": %" PRIx16 "\n", argv[0].intval,
+            (uint16_t) argv[1].intval);
+        pio_write_16(ptr, (uint16_t) argv[1].intval);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint16_t));
+        return 1;
+}
+/** Write 4 bytes to phys memory or io port.
+ *
+ * @param argv Argument vector.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+static int cmd_pio_write_32(cmd_arg_t *argv)
+{
+        uint32_t *ptr = NULL;
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                ptr = (void *) argv[0].intval;
+        else
+#endif
+                ptr = (uint32_t *) km_map(argv[0].intval, sizeof(uint32_t),
+                    PAGE_NOT_CACHEABLE);
+        printf("write %" PRIxn ": %" PRIx32 "\n", argv[0].intval,
+            (uint32_t) argv[1].intval);
+        pio_write_32(ptr, (uint32_t) argv[1].intval);
+#ifdef IO_SPACE_BOUNDARY
+        if ((void *) argv->intval < IO_SPACE_BOUNDARY)
+                return 1;
+#endif
+        km_unmap((uintptr_t) ptr, sizeof(uint32_t));
         return 1;
+}

kernel/generic/src/console/kconsole.c

-              r5d230a30
+              r69146b93
                 /* It's a number - convert it */
                 uint64_t value;
+                int rc = str_uint64_t(text, NULL, 0, true, &value);
+                char *end;
+                int rc = str_uint64_t(text, &end, 0, false, &value);
+                if (end != text + len)
+                        rc = EINVAL;
                 switch (rc) {
                 case EINVAL:
                         printf("Invalid number.\n");
+                        printf("Invalid number '%s'.\n", text);
                         return false;
                 case EOVERFLOW:
                         printf("Integer overflow.\n");
+                        printf("Integer overflow in '%s'.\n", text);
                         return false;
                 case EOK:
 …
                         break;
                 default:
                         printf("Unknown error.\n");
+                        printf("Unknown error parsing '%s'.\n", text);
                         return false;
+                }

kernel/generic/src/interrupt/interrupt.c

r5d230a30	r69146b93
164	164	}
165	165
166		static NO_TRACE void fault_from_uspace_core(istate_t istate, const char fmt, va_list args)
	166	static NO_TRACE
	167	void fault_from_uspace_core(istate_t istate, const char fmt, va_list args)
167	168	{
168	169	printf("Task %s (%" PRIu64 ") killed due to an exception at "

kernel/generic/src/main/kinit.c

-              r5d230a30
+              r69146b93
 #endif /* CONFIG_KCONSOLE */
+        /*
+         * Store the default stack size in sysinfo so that uspace can create
+         * stack with this default size.
+         */
+        sysinfo_set_item_val("default.stack_size", NULL, STACK_SIZE_USER);
         interrupts_enable();

kernel/generic/src/mm/as.c

-              r5d230a30
+              r69146b93
 #include <syscall/copy.h>
 #include <arch/interrupt.h>
+#include <interrupt.h>
 /**
 …
         /*
          * So far, the area does not conflict with other areas.
          * Check if it doesn't conflict with kernel address space.
+         * Check if it is contained in the user address space.
          */
         if (!KERNEL_ADDRESS_SPACE_SHADOWED) {
+                return !overlaps(addr, P2SZ(count), KERNEL_ADDRESS_SPACE_START,
+                    KERNEL_ADDRESS_SPACE_END - KERNEL_ADDRESS_SPACE_START);
+                return iswithin(USER_ADDRESS_SPACE_START,
+                    (USER_ADDRESS_SPACE_END - USER_ADDRESS_SPACE_START) + 1,
+                    addr, P2SZ(count));
+        }
 …
                 return ENOENT;
+        }
+        if (area->backend == &phys_backend) {
+                /*
+                 * Remapping of address space areas associated
+                 * with memory mapped devices is not supported.
+        if (!area->backend->is_resizable(area)) {
+                /*
+                 * The backend does not support resizing for this area.
                  */
                 mutex_unlock(&area->lock);
 …
+        }
+        if ((!src_area->backend) || (!src_area->backend->share)) {
+                /*
+                 * There is no backend or the backend does not
+                 * know how to share the area.
+        if (!src_area->backend->is_shareable(src_area)) {
+                /*
+                 * The backend does not permit sharing of this area.
                  */
                 mutex_unlock(&src_area->lock);
 …
 int as_page_fault(uintptr_t page, pf_access_t access, istate_t *istate)
+{
+        int rc = AS_PF_FAULT;
         if (!THREAD)
                 return AS_PF_FAULT;
+                goto page_fault;
         if (!AS)
                 return AS_PF_FAULT;
+                goto page_fault;
         mutex_lock(&AS->lock);
 …
          * Resort to the backend page fault handler.
          */
+        if (area->backend->page_fault(area, page, access) != AS_PF_OK) {
+        rc = area->backend->page_fault(area, page, access);
+        if (rc != AS_PF_OK) {
                 page_table_unlock(AS, false);
                 mutex_unlock(&area->lock);
 …
                 istate_set_retaddr(istate,
                     (uintptr_t) &memcpy_to_uspace_failover_address);
+        } else if (rc == AS_PF_SILENT) {
+                printf("Killing task %" PRIu64 " due to a "
+                    "failed late reservation request.\n", TASK->taskid);
+                task_kill_self(true);
         } else {
+                return AS_PF_FAULT;
+                fault_if_from_uspace(istate, "Page fault: %p.", (void *) page);
+                panic_memtrap(istate, access, page, NULL);
+        }
 …
+{
         uintptr_t virt = base;
         as_area_t *area = as_area_create(AS, flags | AS_AREA_CACHEABLE, size,
+        as_area_t *area = as_area_create(AS, flags, size,
             AS_AREA_ATTR_NONE, &anon_backend, NULL, &virt, bound);
         if (area == NULL)

kernel/generic/src/mm/backend_anon.c

-              r5d230a30
+              r69146b93
 static void anon_destroy(as_area_t *);
+static bool anon_is_resizable(as_area_t *);
+static bool anon_is_shareable(as_area_t *);
 static int anon_page_fault(as_area_t *, uintptr_t, pf_access_t);
 static void anon_frame_free(as_area_t *, uintptr_t, uintptr_t);
 …
         .destroy = anon_destroy,
+        .is_resizable = anon_is_resizable,
+        .is_shareable = anon_is_shareable,
         .page_fault = anon_page_fault,
         .frame_free = anon_frame_free,
 …
 bool anon_create(as_area_t *area)
+{
+        if (area->flags & AS_AREA_LATE_RESERVE)
+                return true;
         return reserve_try_alloc(area->pages);
+}
 …
 bool anon_resize(as_area_t *area, size_t new_pages)
+{
+        if (area->flags & AS_AREA_LATE_RESERVE)
+                return true;
         if (new_pages > area->pages)
                 return reserve_try_alloc(new_pages - area->pages);
 …
         ASSERT(mutex_locked(&area->as->lock));
         ASSERT(mutex_locked(&area->lock));
+        ASSERT(!(area->flags & AS_AREA_LATE_RESERVE));
         /*
 …
 void anon_destroy(as_area_t *area)
+{
+        if (area->flags & AS_AREA_LATE_RESERVE)
+                return;
         reserve_free(area->pages);
+}
+bool anon_is_resizable(as_area_t *area)
+{
+        return true;
+}
+bool anon_is_shareable(as_area_t *area)
+{
+        return !(area->flags & AS_AREA_LATE_RESERVE);
+}
 /** Service a page fault in the anonymous memory address space area.
 …
                  *   the different causes
                  */
+                if (area->flags & AS_AREA_LATE_RESERVE) {
+                        /*
+                         * Reserve the memory for this page now.
+                         */
+                        if (!reserve_try_alloc(1))
+                                return AS_PF_SILENT;
+                }
                 kpage = km_temporary_page_get(&frame, FRAME_NO_RESERVE);
                 memsetb((void *) kpage, PAGE_SIZE, 0);
 …
         ASSERT(mutex_locked(&area->lock));
+        frame_free_noreserve(frame);
+        if (area->flags & AS_AREA_LATE_RESERVE) {
+                /*
+                 * In case of the late reserve areas, physical memory will not
+                 * be unreserved when the area is destroyed so we need to use
+                 * the normal unreserving frame_free().
+                 */
+                frame_free(frame);
+        } else {
+                /*
+                 * The reserve will be given back when the area is destroyed or
+                 * resized, so use the frame_free_noreserve() which does not
+                 * manipulate the reserve or it would be given back twice.
+                 */
+                frame_free_noreserve(frame);
+        }
+}

kernel/generic/src/mm/backend_elf.c

-              r5d230a30
+              r69146b93
 static void elf_destroy(as_area_t *);
+static bool elf_is_resizable(as_area_t *);
+static bool elf_is_shareable(as_area_t *);
 static int elf_page_fault(as_area_t *, uintptr_t, pf_access_t);
 static void elf_frame_free(as_area_t *, uintptr_t, uintptr_t);
 …
         .share = elf_share,
         .destroy = elf_destroy,
+        .is_resizable = elf_is_resizable,
+        .is_shareable = elf_is_shareable,
         .page_fault = elf_page_fault,
 …
+}
+bool elf_is_resizable(as_area_t *area)
+{
+        return true;
+}
+bool elf_is_shareable(as_area_t *area)
+{
+        return true;
+}
 /** Service a page fault in the ELF backend address space area.
+ *

kernel/generic/src/mm/backend_phys.c

-              r5d230a30
+              r69146b93
 static void phys_destroy(as_area_t *);
+static bool phys_is_resizable(as_area_t *);
+static bool phys_is_shareable(as_area_t *);
 static int phys_page_fault(as_area_t *, uintptr_t, pf_access_t);
 …
         .share = phys_share,
         .destroy = phys_destroy,
+        .is_resizable = phys_is_resizable,
+        .is_shareable = phys_is_shareable,
         .page_fault = phys_page_fault,
 …
         /* Nothing to do. */
+}
+bool phys_is_resizable(as_area_t *area)
+{
+        return false;
+}
+bool phys_is_shareable(as_area_t *area)
+{
+        return true;
+}
 /** Service a page fault in the address space area backed by physical memory.

kernel/generic/src/mm/km.c

-              r5d230a30
+              r69146b93
  * @param[inout] framep Pointer to a variable which will receive the physical
  *                      address of the allocated frame.
+ * @param[in] flags     Frame allocation flags. FRAME_NONE or FRAME_NO_RESERVE.
+ * @param[in] flags     Frame allocation flags. FRAME_NONE, FRAME_NO_RESERVE
+ *                      and FRAME_ATOMIC bits are allowed.
  * @return              Virtual address of the allocated frame.
  */
 …
         ASSERT(THREAD);
         ASSERT(framep);
         ASSERT(!(flags & ~FRAME_NO_RESERVE));
+        ASSERT(!(flags & ~(FRAME_NO_RESERVE | FRAME_ATOMIC)));
         /*
 …
                 ASSERT(page);   // FIXME
         } else {
+                frame = (uintptr_t) frame_alloc_noreserve(ONE_FRAME,
+                    FRAME_LOWMEM);
+                frame = (uintptr_t) frame_alloc(ONE_FRAME,
+                    FRAME_LOWMEM | flags);
+                if (!frame)
+                        return (uintptr_t) NULL;
                 page = PA2KA(frame);
+        }

kernel/generic/src/proc/program.c

-              r5d230a30
+              r69146b93
          * Create the stack address space area.
          */
+        uintptr_t virt = USTACK_ADDRESS;
+        uintptr_t virt = (uintptr_t) -1;
+        uintptr_t bound = USER_ADDRESS_SPACE_END - (STACK_SIZE_USER - 1);
+        /* Adjust bound to create space for the desired guard page. */
+        bound -= PAGE_SIZE;
         as_area_t *area = as_area_create(as,
+            AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE,
+            STACK_SIZE, AS_AREA_ATTR_NONE, &anon_backend, NULL, &virt, 0);
+            AS_AREA_READ | AS_AREA_WRITE | AS_AREA_CACHEABLE | AS_AREA_GUARD |
+            AS_AREA_LATE_RESERVE, STACK_SIZE_USER, AS_AREA_ATTR_NONE,
+            &anon_backend, NULL, &virt, bound);
         if (!area) {
                 task_destroy(prg->task);
 …
         kernel_uarg->uspace_entry = (void *) entry_addr;
         kernel_uarg->uspace_stack = (void *) virt;
         kernel_uarg->uspace_stack_size = STACK_SIZE;
+        kernel_uarg->uspace_stack_size = STACK_SIZE_USER;
         kernel_uarg->uspace_thread_function = NULL;
         kernel_uarg->uspace_thread_arg = NULL;

kernel/generic/src/proc/task.c

r5d230a30	r69146b93
196	196	task->ucycles = 0;
197	197	task->kcycles = 0;
198
	198
199	199	task->ipc_info.call_sent = 0;
200	200	task->ipc_info.call_received = 0;

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Changeset 69146b93 in mainline for kernel

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