| 1 | /*
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| 2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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| 3 | * Copyright (c) 2012 Jan Vesely
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup arm32mm
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief Paging related declarations.
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| 35 | */
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| 36 |
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| 37 | #ifndef KERN_arm32_PAGE_armv4_H_
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| 38 | #define KERN_arm32_PAGE_armv4_H_
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| 39 |
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| 40 | #ifndef KERN_arm32_PAGE_H_
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| 41 | #error "Do not include arch specific page.h directly use generic page.h instead"
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| 42 | #endif
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| 43 |
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| 44 | /* Macros for querying the last-level PTE entries. */
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| 45 | #define PTE_VALID_ARCH(pte) \
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| 46 | (*((uint32_t *) (pte)) != 0)
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| 47 | #define PTE_PRESENT_ARCH(pte) \
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| 48 | (((pte_t *) (pte))->l0.descriptor_type != 0)
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| 49 | #define PTE_GET_FRAME_ARCH(pte) \
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| 50 | (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
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| 51 | #define PTE_WRITABLE_ARCH(pte) \
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| 52 | (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
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| 53 | #define PTE_EXECUTABLE_ARCH(pte) \
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| 54 | 1
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| 55 |
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| 56 | #ifndef __ASM__
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| 57 |
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| 58 | /** Level 0 page table entry. */
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| 59 | typedef struct {
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| 60 | /* 0b01 for coarse tables, see below for details */
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| 61 | unsigned descriptor_type : 2;
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| 62 | unsigned impl_specific : 3;
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| 63 | unsigned domain : 4;
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| 64 | unsigned should_be_zero : 1;
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| 65 |
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| 66 | /* Pointer to the coarse 2nd level page table (holding entries for small
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| 67 | * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page
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| 68 | * tables that may hold even tiny pages (1KB) but they are bigger (4KB
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| 69 | * per table in comparison with 1KB per the coarse table)
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| 70 | */
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| 71 | unsigned coarse_table_addr : 22;
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| 72 | } ATTRIBUTE_PACKED pte_level0_t;
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| 73 |
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| 74 | /** Level 1 page table entry (small (4KB) pages used). */
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| 75 | typedef struct {
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| 76 |
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| 77 | /* 0b10 for small pages */
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| 78 | unsigned descriptor_type : 2;
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| 79 | unsigned bufferable : 1;
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| 80 | unsigned cacheable : 1;
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| 81 |
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| 82 | /* access permissions for each of 4 subparts of a page
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| 83 | * (for each 1KB when small pages used */
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| 84 | unsigned access_permission_0 : 2;
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| 85 | unsigned access_permission_1 : 2;
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| 86 | unsigned access_permission_2 : 2;
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| 87 | unsigned access_permission_3 : 2;
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| 88 | unsigned frame_base_addr : 20;
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| 89 | } ATTRIBUTE_PACKED pte_level1_t;
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| 90 |
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| 91 | typedef union {
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| 92 | pte_level0_t l0;
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| 93 | pte_level1_t l1;
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| 94 | } pte_t;
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| 95 |
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| 96 | /* Level 1 page tables access permissions */
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| 97 |
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| 98 | /** User mode: no access, privileged mode: no access. */
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| 99 | #define PTE_AP_USER_NO_KERNEL_NO 0
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| 100 |
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| 101 | /** User mode: no access, privileged mode: read/write. */
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| 102 | #define PTE_AP_USER_NO_KERNEL_RW 1
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| 103 |
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| 104 | /** User mode: read only, privileged mode: read/write. */
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| 105 | #define PTE_AP_USER_RO_KERNEL_RW 2
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| 106 |
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| 107 | /** User mode: read/write, privileged mode: read/write. */
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| 108 | #define PTE_AP_USER_RW_KERNEL_RW 3
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| 109 |
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| 110 |
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| 111 | /* pte_level0_t and pte_level1_t descriptor_type flags */
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| 112 |
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| 113 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */
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| 114 | #define PTE_DESCRIPTOR_NOT_PRESENT 0
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| 115 |
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| 116 | /** pte_level0_t coarse page table flag (used in descriptor_type). */
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| 117 | #define PTE_DESCRIPTOR_COARSE_TABLE 1
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| 118 |
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| 119 | /** pte_level1_t small page table flag (used in descriptor type). */
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| 120 | #define PTE_DESCRIPTOR_SMALL_PAGE 2
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| 121 |
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| 122 |
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| 123 | /** Sets the address of level 0 page table.
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| 124 | *
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| 125 | * @param pt Pointer to the page table to set.
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| 126 | *
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| 127 | */
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| 128 | NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
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| 129 | {
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| 130 | asm volatile (
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| 131 | "mcr p15, 0, %[pt], c2, c0, 0\n"
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| 132 | :: [pt] "r" (pt)
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| 133 | );
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| 134 | }
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| 135 |
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| 136 |
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| 137 | /** Returns level 0 page table entry flags.
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| 138 | *
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| 139 | * @param pt Level 0 page table.
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| 140 | * @param i Index of the entry to return.
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| 141 | *
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| 142 | */
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| 143 | NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
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| 144 | {
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| 145 | pte_level0_t *p = &pt[i].l0;
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| 146 | int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
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| 147 |
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| 148 | return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
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| 149 | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
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| 150 | (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT);
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| 151 | }
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| 152 |
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| 153 | /** Returns level 1 page table entry flags.
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| 154 | *
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| 155 | * @param pt Level 1 page table.
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| 156 | * @param i Index of the entry to return.
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| 157 | *
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| 158 | */
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| 159 | NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
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| 160 | {
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| 161 | pte_level1_t *p = &pt[i].l1;
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| 162 |
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| 163 | int dt = p->descriptor_type;
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| 164 | int ap = p->access_permission_0;
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| 165 |
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| 166 | return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
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| 167 | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
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| 168 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) |
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| 169 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) |
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| 170 | ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) |
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| 171 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) |
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| 172 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) |
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| 173 | (1 << PAGE_EXEC_SHIFT) |
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| 174 | (p->bufferable << PAGE_CACHEABLE);
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| 175 | }
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| 176 |
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| 177 | /** Sets flags of level 0 page table entry.
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| 178 | *
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| 179 | * @param pt level 0 page table
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| 180 | * @param i index of the entry to be changed
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| 181 | * @param flags new flags
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| 182 | *
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| 183 | */
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| 184 | NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
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| 185 | {
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| 186 | pte_level0_t *p = &pt[i].l0;
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| 187 |
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| 188 | if (flags & PAGE_NOT_PRESENT) {
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| 189 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
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| 190 | /*
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| 191 | * Ensures that the entry will be recognized as valid when
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| 192 | * PTE_VALID_ARCH applied.
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| 193 | */
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| 194 | p->should_be_zero = 1;
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| 195 | } else {
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| 196 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
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| 197 | p->should_be_zero = 0;
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| 198 | }
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| 199 | }
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| 200 |
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| 201 |
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| 202 | /** Sets flags of level 1 page table entry.
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| 203 | *
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| 204 | * We use same access rights for the whole page. When page
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| 205 | * is not preset we store 1 in acess_rigts_3 so that at least
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| 206 | * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
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| 207 | *
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| 208 | * @param pt Level 1 page table.
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| 209 | * @param i Index of the entry to be changed.
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| 210 | * @param flags New flags.
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| 211 | *
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| 212 | */
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| 213 | NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
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| 214 | {
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| 215 | pte_level1_t *p = &pt[i].l1;
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| 216 |
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| 217 | if (flags & PAGE_NOT_PRESENT)
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| 218 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
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| 219 | else
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| 220 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
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| 221 |
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| 222 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
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| 223 |
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| 224 | /* default access permission */
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| 225 | p->access_permission_0 = p->access_permission_1 =
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| 226 | p->access_permission_2 = p->access_permission_3 =
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| 227 | PTE_AP_USER_NO_KERNEL_RW;
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| 228 |
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| 229 | if (flags & PAGE_USER) {
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| 230 | if (flags & PAGE_READ) {
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| 231 | p->access_permission_0 = p->access_permission_1 =
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| 232 | p->access_permission_2 = p->access_permission_3 =
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| 233 | PTE_AP_USER_RO_KERNEL_RW;
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| 234 | }
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| 235 | if (flags & PAGE_WRITE) {
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| 236 | p->access_permission_0 = p->access_permission_1 =
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| 237 | p->access_permission_2 = p->access_permission_3 =
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| 238 | PTE_AP_USER_RW_KERNEL_RW;
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| 239 | }
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| 240 | }
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| 241 | }
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| 242 |
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| 243 | NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
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| 244 | {
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| 245 | pte_level0_t *p = &pt[i].l0;
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| 246 |
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| 247 | p->should_be_zero = 0;
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| 248 | write_barrier();
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| 249 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
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| 250 | }
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| 251 |
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| 252 |
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| 253 | NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
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| 254 | {
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| 255 | pte_level1_t *p = &pt[i].l1;
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| 256 |
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| 257 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
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| 258 | }
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| 259 |
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| 260 |
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| 261 | extern void page_arch_init(void);
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| 262 |
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| 263 |
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| 264 | #endif /* __ASM__ */
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| 265 |
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| 266 | #endif
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| 267 |
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| 268 | /** @}
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| 269 | */
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