Changeset 68656282 in mainline for arch/sparc64/include/mm/tlb.h

Timestamp:

2006-02-24T19:59:57Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

578aebf7

Parents:

b6fba84

Message:

Fixes in sparc64 preliminary TLB miss handler.
Compute and insert identity mapping for kernel on the fly.

File:

• arch/sparc64/include/mm/tlb.h (modified) (4 diffs)

arch/sparc64/include/mm/tlb.h

@@ -112 +112 @@
                 unsigned asi : 8;       /**< ASI. */
                 unsigned tm : 1;        /**< TLB miss. */
-                unsigned : 3;
-                unsigned ft : 5;        /**< Fault type. */
+                unsigned : 1;
+                unsigned ft : 7;        /**< Fault type. */
                 unsigned e : 1;         /**< Side-effect bit. */
                 unsigned ct : 2;        /**< Context Register selection. */
@@ -119 +119 @@
                 unsigned w : 1;         /**< Write bit. */
                 unsigned ow : 1;        /**< Overwrite bit. */
-                unsigned fv : 1;        /**< Fayult Valid bit. */
+                unsigned fv : 1;        /**< Fault Valid bit. */
         } __attribute__ ((packed));
 };
@@ -262 +262 @@
 }
 
+/** Read IMMU TLB Tag Access Register.
+ *
+ * @return Current value of IMMU TLB Tag Access Register.
+ */
+static inline __u64 itlb_tag_access_read(void)
+{
+        return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
+}
+
 /** Write DMMU TLB Tag Access Register.
  *
@@ -271 +280 @@
         flush();
 }
+
+/** Read DMMU TLB Tag Access Register.
+ *
+ * @return Current value of DMMU TLB Tag Access Register.
+ */
+static inline __u64 dtlb_tag_access_read(void)
+{
+        return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
+}
+
 
 /** Write IMMU TLB Data in Register.