Ignore:
Timestamp:
2018-01-31T02:21:24Z (7 years ago)
Author:
Jenda <jenda.jzqk73@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a0a9cc2
Parents:
132ab5d1
Message:

Merge commit '50f19b7ee8e94570b5c63896736c4eb49cfa18db' into forwardport

Not all ints are converted to errno_t in xhci tree yet, however it compiles and works :)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/lib/c/generic/device/hw_res.c

    r132ab5d1 r5a6cc679  
    3838#include <stdlib.h>
    3939
    40 int hw_res_get_resource_list(async_sess_t *sess,
     40errno_t hw_res_get_resource_list(async_sess_t *sess,
    4141    hw_resource_list_t *hw_resources)
    4242{
     
    4545        async_exch_t *exch = async_exchange_begin(sess);
    4646       
    47         int rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     47        errno_t rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    4848            HW_RES_GET_RESOURCE_LIST, &count);
    4949       
     
    7575}
    7676
    77 int hw_res_enable_interrupt(async_sess_t *sess, int irq)
     77errno_t hw_res_enable_interrupt(async_sess_t *sess, int irq)
    7878{
    7979        async_exch_t *exch = async_exchange_begin(sess);
    8080       
    81         int rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     81        errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    8282            HW_RES_ENABLE_INTERRUPT, irq);
    8383        async_exchange_end(exch);
     
    8686}
    8787
    88 int hw_res_disable_interrupt(async_sess_t *sess, int irq)
     88errno_t hw_res_disable_interrupt(async_sess_t *sess, int irq)
    8989{
    9090        async_exch_t *exch = async_exchange_begin(sess);
    9191       
    92         int rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     92        errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    9393            HW_RES_DISABLE_INTERRUPT, irq);
    9494        async_exchange_end(exch);
     
    9797}
    9898
    99 int hw_res_clear_interrupt(async_sess_t *sess, int irq)
     99errno_t hw_res_clear_interrupt(async_sess_t *sess, int irq)
    100100{
    101101        async_exch_t *exch = async_exchange_begin(sess);
    102102       
    103         int rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     103        errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    104104            HW_RES_CLEAR_INTERRUPT, irq);
    105105        async_exchange_end(exch);
     
    122122 *
    123123 */
    124 int hw_res_dma_channel_setup(async_sess_t *sess,
     124errno_t hw_res_dma_channel_setup(async_sess_t *sess,
    125125    unsigned channel, uint32_t pa, uint32_t size, uint8_t mode)
    126126{
     
    128128       
    129129        const uint32_t packed = (channel & 0xffff) | (mode << 16);
    130         const int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     130        const errno_t ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    131131            HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
    132132       
     
    145145 *
    146146 */
    147 int hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel, size_t *rem)
     147errno_t hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel, size_t *rem)
    148148{
    149149        async_exch_t *exch = async_exchange_begin(sess);
    150150       
    151151        sysarg_t remain;
    152         const int ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
     152        const errno_t ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
    153153            HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
    154154       
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