- Timestamp:
- 2010-11-02T18:29:01Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4f35b9ff
- Parents:
- 76e1121f (diff), 28f4adb (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 8 added
- 21 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/include/interrupt.h
r76e1121f r4687a26c 37 37 38 38 #include <typedefs.h> 39 #include <verify.h> 40 #include <trace.h> 39 #include <arch/istate.h> 41 40 42 41 #define IVT_ITEMS 0 … … 45 44 #define VECTOR_TLB_SHOOTDOWN_IPI 0 46 45 47 /*48 * On real hardware this stores the registers which49 * need to be preserved during interupts.50 */51 typedef struct istate {52 uintptr_t ip;53 uintptr_t fp;54 uint32_t stack[];55 } istate_t;56 57 NO_TRACE static inline int istate_from_uspace(istate_t *istate)58 REQUIRES_EXTENT_MUTABLE(istate)59 {60 /* On real hardware this checks whether the interrupted61 context originated from user space. */62 63 return !(istate->ip & 0x80000000);64 }65 66 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,67 uintptr_t retaddr)68 WRITES(&istate->ip)69 {70 /* On real hardware this sets the instruction pointer. */71 72 istate->ip = retaddr;73 }74 75 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)76 REQUIRES_EXTENT_MUTABLE(istate)77 {78 /* On real hardware this returns the instruction pointer. */79 80 return istate->ip;81 }82 83 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)84 REQUIRES_EXTENT_MUTABLE(istate)85 {86 /* On real hardware this returns the frame pointer. */87 88 return istate->fp;89 }90 91 46 #endif 92 47 -
kernel/arch/amd64/include/interrupt.h
r76e1121f r4687a26c 37 37 38 38 #include <typedefs.h> 39 #include <arch/istate.h> 39 40 #include <arch/pm.h> 40 #include <trace.h>41 41 42 42 #define IVT_ITEMS IDT_ITEMS … … 71 71 #define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) 72 72 73 /** This is passed to interrupt handlers */74 typedef struct istate {75 uint64_t rax;76 uint64_t rbx;77 uint64_t rcx;78 uint64_t rdx;79 uint64_t rsi;80 uint64_t rdi;81 uint64_t rbp;82 uint64_t r8;83 uint64_t r9;84 uint64_t r10;85 uint64_t r11;86 uint64_t r12;87 uint64_t r13;88 uint64_t r14;89 uint64_t r15;90 uint64_t alignment; /* align rbp_frame on multiple of 16 */91 uint64_t rbp_frame; /* imitation of frame pointer linkage */92 uint64_t rip_frame; /* imitation of return address linkage */93 uint64_t error_word; /* real or fake error word */94 uint64_t rip;95 uint64_t cs;96 uint64_t rflags;97 uint64_t rsp; /* only if istate_t is from uspace */98 uint64_t ss; /* only if istate_t is from uspace */99 } istate_t;100 101 /** Return true if exception happened while in userspace */102 NO_TRACE static inline int istate_from_uspace(istate_t *istate)103 {104 return !(istate->rip & 0x8000000000000000);105 }106 107 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,108 uintptr_t retaddr)109 {110 istate->rip = retaddr;111 }112 113 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)114 {115 return istate->rip;116 }117 118 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)119 {120 return istate->rbp;121 }122 123 73 extern void (* disable_irqs_function)(uint16_t); 124 74 extern void (* enable_irqs_function)(uint16_t); -
kernel/arch/arm32/include/exception.h
r76e1121f r4687a26c 39 39 40 40 #include <typedefs.h> 41 #include <arch/regutils.h> 42 #include <trace.h> 41 #include <arch/istate.h> 43 42 44 43 /** If defined, forces using of high exception vectors. */ … … 85 84 extern uintptr_t exc_stack; 86 85 87 /** Struct representing CPU state saved when an exception occurs. */88 typedef struct istate {89 uint32_t spsr;90 uint32_t sp;91 uint32_t lr;92 93 uint32_t r0;94 uint32_t r1;95 uint32_t r2;96 uint32_t r3;97 uint32_t r4;98 uint32_t r5;99 uint32_t r6;100 uint32_t r7;101 uint32_t r8;102 uint32_t r9;103 uint32_t r10;104 uint32_t fp;105 uint32_t r12;106 107 uint32_t pc;108 } istate_t;109 110 /** Set Program Counter member of given istate structure.111 *112 * @param istate istate structure113 * @param retaddr new value of istate's PC member114 *115 */116 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,117 uintptr_t retaddr)118 {119 istate->pc = retaddr;120 }121 122 /** Return true if exception happened while in userspace. */123 NO_TRACE static inline int istate_from_uspace(istate_t *istate)124 {125 return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;126 }127 128 /** Return Program Counter member of given istate structure. */129 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)130 {131 return istate->pc;132 }133 134 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)135 {136 return istate->fp;137 }138 139 86 extern void install_exception_handlers(void); 140 87 extern void exception_init(void); -
kernel/arch/ia32/include/interrupt.h
r76e1121f r4687a26c 37 37 38 38 #include <typedefs.h> 39 #include <arch/istate.h> 39 40 #include <arch/pm.h> 40 #include <trace.h>41 41 42 42 #define IVT_ITEMS IDT_ITEMS … … 71 71 #define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) 72 72 73 typedef struct istate {74 /*75 * The strange order of the GPRs is given by the requirement to use the76 * istate structure for both regular interrupts and exceptions as well77 * as for syscall handlers which use this order as an optimization.78 */79 uint32_t edx;80 uint32_t ecx;81 uint32_t ebx;82 uint32_t esi;83 uint32_t edi;84 uint32_t ebp;85 uint32_t eax;86 87 uint32_t ebp_frame; /* imitation of frame pointer linkage */88 uint32_t eip_frame; /* imitation of return address linkage */89 90 uint32_t gs;91 uint32_t fs;92 uint32_t es;93 uint32_t ds;94 95 uint32_t error_word; /* real or fake error word */96 uint32_t eip;97 uint32_t cs;98 uint32_t eflags;99 uint32_t esp; /* only if istate_t is from uspace */100 uint32_t ss; /* only if istate_t is from uspace */101 } istate_t;102 103 /** Return true if exception happened while in userspace */104 NO_TRACE static inline int istate_from_uspace(istate_t *istate)105 {106 return !(istate->eip & 0x80000000);107 }108 109 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,110 uintptr_t retaddr)111 {112 istate->eip = retaddr;113 }114 115 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)116 {117 return istate->eip;118 }119 120 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)121 {122 return istate->ebp;123 }124 125 73 extern void (* disable_irqs_function)(uint16_t); 126 74 extern void (* enable_irqs_function)(uint16_t); -
kernel/arch/ia64/include/interrupt.h
r76e1121f r4687a26c 37 37 38 38 #include <typedefs.h> 39 #include <arch/register.h> 40 #include <trace.h> 39 #include <arch/istate.h> 41 40 42 41 /** ia64 has 256 INRs. */ … … 74 73 #define EOI 0 /**< The actual value doesn't matter. */ 75 74 76 typedef struct istate {77 uint128_t f2;78 uint128_t f3;79 uint128_t f4;80 uint128_t f5;81 uint128_t f6;82 uint128_t f7;83 uint128_t f8;84 uint128_t f9;85 uint128_t f10;86 uint128_t f11;87 uint128_t f12;88 uint128_t f13;89 uint128_t f14;90 uint128_t f15;91 uint128_t f16;92 uint128_t f17;93 uint128_t f18;94 uint128_t f19;95 uint128_t f20;96 uint128_t f21;97 uint128_t f22;98 uint128_t f23;99 uint128_t f24;100 uint128_t f25;101 uint128_t f26;102 uint128_t f27;103 uint128_t f28;104 uint128_t f29;105 uint128_t f30;106 uint128_t f31;107 108 uintptr_t ar_bsp;109 uintptr_t ar_bspstore;110 uintptr_t ar_bspstore_new;111 uint64_t ar_rnat;112 uint64_t ar_ifs;113 uint64_t ar_pfs;114 uint64_t ar_rsc;115 uintptr_t cr_ifa;116 cr_isr_t cr_isr;117 uintptr_t cr_iipa;118 psr_t cr_ipsr;119 uintptr_t cr_iip;120 uint64_t pr;121 uintptr_t sp;122 123 /*124 * The following variables are defined only for break_instruction125 * handler.126 */127 uint64_t in0;128 uint64_t in1;129 uint64_t in2;130 uint64_t in3;131 uint64_t in4;132 uint64_t in5;133 uint64_t in6;134 } istate_t;135 136 75 extern void *ivt; 137 138 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,139 uintptr_t retaddr)140 {141 istate->cr_iip = retaddr;142 istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */143 }144 145 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)146 {147 return istate->cr_iip;148 }149 150 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)151 {152 /* FIXME */153 154 return 0;155 }156 157 NO_TRACE static inline int istate_from_uspace(istate_t *istate)158 {159 return (istate->cr_iip) < 0xe000000000000000ULL;160 }161 76 162 77 extern void general_exception(uint64_t, istate_t *); -
kernel/arch/ia64/include/register.h
r76e1121f r4687a26c 142 142 #ifndef __ASM__ 143 143 144 #ifdef KERNEL 144 145 #include <typedefs.h> 146 #else 147 #include <sys/types.h> 148 #endif 145 149 146 150 /** Processor Status Register. */ -
kernel/arch/mips32/include/cp0.h
r76e1121f r4687a26c 36 36 #define KERN_mips32_CP0_H_ 37 37 38 #ifdef KERNEL 38 39 #include <typedefs.h> 40 #else 41 #include <sys/types.h> 42 #endif 39 43 40 44 #define cp0_status_ie_enabled_bit (1 << 0) -
kernel/arch/mips32/include/exception.h
r76e1121f r4687a26c 37 37 38 38 #include <typedefs.h> 39 #include <arch/cp0.h> 40 #include <trace.h> 39 #include <arch/istate.h> 41 40 42 41 #define EXC_Int 0 … … 59 58 #define EXC_VCED 31 60 59 61 typedef struct istate {62 /*63 * The first seven registers are arranged so that the istate structure64 * can be used both for exception handlers and for the syscall handler.65 */66 uint32_t a0; /* arg1 */67 uint32_t a1; /* arg2 */68 uint32_t a2; /* arg3 */69 uint32_t a3; /* arg4 */70 uint32_t t0; /* arg5 */71 uint32_t t1; /* arg6 */72 uint32_t v0; /* arg7 */73 uint32_t v1;74 uint32_t at;75 uint32_t t2;76 uint32_t t3;77 uint32_t t4;78 uint32_t t5;79 uint32_t t6;80 uint32_t t7;81 uint32_t s0;82 uint32_t s1;83 uint32_t s2;84 uint32_t s3;85 uint32_t s4;86 uint32_t s5;87 uint32_t s6;88 uint32_t s7;89 uint32_t t8;90 uint32_t t9;91 uint32_t kt0;92 uint32_t kt1; /* We use it as thread-local pointer */93 uint32_t gp;94 uint32_t sp;95 uint32_t s8;96 uint32_t ra;97 98 uint32_t lo;99 uint32_t hi;100 101 uint32_t status; /* cp0_status */102 uint32_t epc; /* cp0_epc */103 104 uint32_t alignment; /* to make sizeof(istate_t) a multiple of 8 */105 } istate_t;106 107 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,108 uintptr_t retaddr)109 {110 istate->epc = retaddr;111 }112 113 /** Return true if exception happened while in userspace */114 NO_TRACE static inline int istate_from_uspace(istate_t *istate)115 {116 return istate->status & cp0_status_um_bit;117 }118 119 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)120 {121 return istate->epc;122 }123 124 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)125 {126 return istate->sp;127 }128 129 60 extern void exception(istate_t *istate); 130 61 extern void tlb_refill_entry(void); -
kernel/arch/mips32/include/smp/dorder.h
r76e1121f r4687a26c 1 1 /* 2 * Copyright (c) 20 10Martin Decky2 * Copyright (c) 2007 Martin Decky 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup netif_standalone 30 * @{ 29 /** @addtogroup mips32 30 * @{ 31 */ 32 /** @file 31 33 */ 32 34 33 #ifndef __NETIF_NIL_BUNDLE_H__34 #define __NETIF_NIL_BUNDLE_H__35 #ifndef KERN_mips32_DORDER_H_ 36 #define KERN_mips32_DORDER_H_ 35 37 36 #include <ipc/ipc.h> 37 #include <async.h> 38 #include <typedefs.h> 38 39 39 extern int netif_nil_module_message(const char *, ipc_callid_t, ipc_call_t *, 40 ipc_call_t *, int *); 41 extern int netif_nil_module_start(async_client_conn_t); 40 extern uint32_t dorder_cpuid(void); 41 extern void dorder_ipi_ack(uint32_t); 42 42 43 43 #endif -
kernel/arch/mips32/src/interrupt.c
r76e1121f r4687a26c 38 38 #include <arch.h> 39 39 #include <arch/cp0.h> 40 #include <arch/smp/dorder.h> 40 41 #include <time/clock.h> 41 42 #include <ipc/sysipc.h> … … 48 49 function virtual_timer_fnc = NULL; 49 50 static irq_t timer_irq; 51 static irq_t dorder_irq; 50 52 51 53 // TODO: This is SMP unsafe!!! … … 149 151 } 150 152 153 static irq_ownership_t dorder_claim(irq_t *irq) 154 { 155 return IRQ_ACCEPT; 156 } 157 158 static void dorder_irq_handler(irq_t *irq) 159 { 160 dorder_ipi_ack(1 << dorder_cpuid()); 161 } 162 151 163 /* Initialize basic tables for exception dispatching */ 152 164 void interrupt_init(void) … … 163 175 timer_start(); 164 176 cp0_unmask_int(TIMER_IRQ); 177 178 irq_initialize(&dorder_irq); 179 dorder_irq.devno = device_assign_devno(); 180 dorder_irq.inr = DORDER_IRQ; 181 dorder_irq.claim = dorder_claim; 182 dorder_irq.handler = dorder_irq_handler; 183 irq_register(&dorder_irq); 184 185 cp0_unmask_int(DORDER_IRQ); 165 186 } 166 187 -
kernel/arch/mips32/src/smp/dorder.c
r76e1121f r4687a26c 33 33 */ 34 34 35 #include <typedefs.h> 35 36 #include <smp/ipi.h> 37 #include <arch/smp/dorder.h> 38 39 #define MSIM_DORDER_ADDRESS 0xB0000004 36 40 37 41 #ifdef CONFIG_SMP 38 42 39 #define MSIM_DORDER_ADDRESS 0xB000000440 41 43 void ipi_broadcast_arch(int ipi) 42 44 { 43 *((volatile u nsigned int *) MSIM_DORDER_ADDRESS) = 0x7FFFFFFF;45 *((volatile uint32_t *) MSIM_DORDER_ADDRESS) = 0x7fffffff; 44 46 } 45 47 46 48 #endif 47 49 50 uint32_t dorder_cpuid(void) 51 { 52 return *((volatile uint32_t *) MSIM_DORDER_ADDRESS); 53 } 54 55 void dorder_ipi_ack(uint32_t mask) 56 { 57 *((volatile uint32_t *) (MSIM_DORDER_ADDRESS + 4)) = mask; 58 } 59 48 60 /** @} 49 61 */ -
kernel/arch/sparc64/include/interrupt.h
r76e1121f r4687a26c 38 38 39 39 #include <typedefs.h> 40 #include <arch/regdef.h> 41 #include <trace.h> 40 #include <arch/istate.h> 42 41 43 42 #define IVT_ITEMS 15 … … 51 50 }; 52 51 53 typedef struct istate {54 uint64_t tnpc;55 uint64_t tpc;56 uint64_t tstate;57 } istate_t;58 59 NO_TRACE static inline void istate_set_retaddr(istate_t *istate,60 uintptr_t retaddr)61 {62 istate->tpc = retaddr;63 }64 65 NO_TRACE static inline int istate_from_uspace(istate_t *istate)66 {67 return !(istate->tstate & TSTATE_PRIV_BIT);68 }69 70 NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)71 {72 return istate->tpc;73 }74 75 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)76 {77 /* TODO */78 79 return 0;80 }81 82 52 #endif 83 53 -
kernel/generic/include/ddi/ddi.h
r76e1121f r4687a26c 54 54 extern unative_t sys_physmem_map(unative_t, unative_t, unative_t, unative_t); 55 55 extern unative_t sys_iospace_enable(ddi_ioarg_t *); 56 extern unative_t sys_ preempt_control(int);56 extern unative_t sys_interrupt_enable(int irq, int enable); 57 57 58 58 /* … … 61 61 extern int ddi_iospace_enable_arch(task_t *, uintptr_t, size_t); 62 62 63 63 64 #endif 64 65 -
kernel/generic/include/security/cap.h
r76e1121f r4687a26c 70 70 71 71 /** 72 * CAP_PREEMPT_CONTROL allows its holder to disable/enable preemption.73 */74 #define CAP_PREEMPT_CONTROL (1<<3)75 76 /**77 72 * CAP_IRQ_REG entitles its holder to register IRQ handlers. 78 73 */ 79 #define CAP_IRQ_REG (1<< 4)74 #define CAP_IRQ_REG (1<<3) 80 75 81 76 typedef uint32_t cap_t; -
kernel/generic/include/syscall/syscall.h
r76e1121f r4687a26c 80 80 SYS_PHYSMEM_MAP, 81 81 SYS_IOSPACE_ENABLE, 82 SYS_ PREEMPT_CONTROL,82 SYS_INTERRUPT_ENABLE, 83 83 84 84 SYS_SYSINFO_GET_TAG, -
kernel/generic/src/ddi/ddi.c
r76e1121f r4687a26c 258 258 } 259 259 260 /** Disable or enable preemption.261 * 262 * @param enable If non-zero, the preemption counter will be decremented,263 * leading to potential enabling of preemption. Otherwise264 * the preemption counter will be incremented, preventing265 * preemption from occurring.266 * 267 * @return Zero on success or EPERM if callers capabilities are not sufficient. 268 * 269 */270 unative_t sys_preempt_control(int enable) 271 { 272 if (!( cap_get(TASK) & CAP_PREEMPT_CONTROL))260 /** Disable or enable specified interrupts. 261 * 262 * @param irq the interrupt to be enabled/disabled. 263 * @param enable if true enable the interrupt, disable otherwise. 264 * 265 * @retutn Zero on success, error code otherwise. 266 */ 267 unative_t sys_interrupt_enable(int irq, int enable) 268 { 269 /* FIXME: this needs to be generic code, or better not be in kernel at all. */ 270 #if 0 271 cap_t task_cap = cap_get(TASK); 272 if (!(task_cap & CAP_IRQ_REG)) 273 273 return EPERM; 274 275 if (enable) 276 preemption_enable(); 277 else 278 preemption_disable(); 279 274 275 if (irq < 0 || irq > 16) { 276 return EINVAL; 277 } 278 279 uint16_t irq_mask = (uint16_t)(1 << irq); 280 if (enable) { 281 trap_virtual_enable_irqs(irq_mask); 282 } else { 283 trap_virtual_disable_irqs(irq_mask); 284 } 285 286 #endif 280 287 return 0; 281 288 } -
kernel/generic/src/ipc/kbox.c
r76e1121f r4687a26c 107 107 /* Terminate debugging session (if any). */ 108 108 LOG("Terminate debugging session."); 109 irq_spinlock_lock(&TASK->lock, true);109 mutex_lock(&TASK->udebug.lock); 110 110 udebug_task_cleanup(TASK); 111 irq_spinlock_unlock(&TASK->lock, true);111 mutex_unlock(&TASK->udebug.lock); 112 112 } else { 113 113 LOG("Was not debugger."); -
kernel/generic/src/main/kinit.c
r76e1121f r4687a26c 208 208 */ 209 209 cap_set(programs[i].task, CAP_CAP | CAP_MEM_MANAGER | 210 CAP_IO_MANAGER | CAP_ PREEMPT_CONTROL | CAP_IRQ_REG);210 CAP_IO_MANAGER | CAP_IRQ_REG); 211 211 212 212 if (!ipc_phone_0) -
kernel/generic/src/syscall/syscall.c
r76e1121f r4687a26c 159 159 (syshandler_t) sys_physmem_map, 160 160 (syshandler_t) sys_iospace_enable, 161 (syshandler_t) sys_ preempt_control,161 (syshandler_t) sys_interrupt_enable, 162 162 163 163 /* Sysinfo syscalls */ -
kernel/tools/amd64/decpt.py
r76e1121f r4687a26c 7 7 def main(): 8 8 if len(sys.argv) != 2 or not sys.argv[1].startswith('0x'): 9 print "%s 0x..." % sys.argv[0]9 print("%s 0x..." % sys.argv[0]) 10 10 sys.exit(1) 11 11 … … 16 16 ptl1 = (address >> 30) & 0x1ff 17 17 ptl0 = (address >> 39) & 0x1ff 18 print "Ptl0: %3d" % ptl019 print "Ptl1: %3d" % ptl120 print "Ptl2: %3d" % ptl221 print "Ptl3: %3d" % ptl322 print "Offset: 0x%x" % offset18 print("Ptl0: %3d" % ptl0) 19 print("Ptl1: %3d" % ptl1) 20 print("Ptl2: %3d" % ptl2) 21 print("Ptl3: %3d" % ptl3) 22 print("Offset: 0x%x" % offset) 23 23 24 24 if __name__ == '__main__': -
kernel/tools/genmap.py
r76e1121f r4687a26c 86 86 obdump = read_obdump(obmapf) 87 87 88 def sorter(x,y):89 return cmp(x[0],y[0])88 def key_sorter(x): 89 return x[0] 90 90 91 91 for line in kmapf: … … 93 93 res = startfile.match(line) 94 94 95 if ((res) and ( obdump[res.group(1)].has_key(res.group(3)))):95 if ((res) and (res.group(3) in obdump[res.group(1)])): 96 96 offset = int(res.group(2), 16) 97 97 fname = res.group(3) 98 98 symbols = obdump[res.group(1)][fname] 99 symbols.sort( sorter)99 symbols.sort(key = key_sorter) 100 100 for addr, symbol in symbols: 101 101 value = fname + ':' + symbol … … 107 107 def main(): 108 108 if (len(sys.argv) != 4): 109 print "Usage: %s <kernel.map> <nm dump> <output.bin>" % sys.argv[0]109 print("Usage: %s <kernel.map> <nm dump> <output.bin>" % sys.argv[0]) 110 110 return 1 111 111 112 112 kmapf = open(sys.argv[1], 'r') 113 113 obmapf = open(sys.argv[2], 'r') 114 out = open(sys.argv[3], 'w ')114 out = open(sys.argv[3], 'wb') 115 115 116 116 generate(kmapf, obmapf, out) -
kernel/tools/ia32/decpt.py
r76e1121f r4687a26c 7 7 def main(): 8 8 if len(sys.argv) != 2 or not sys.argv[1].startswith('0x'): 9 print "%s 0x..." % sys.argv[0]9 print("%s 0x..." % sys.argv[0]) 10 10 sys.exit(1) 11 11 … … 14 14 ptl1 = (address >> 12) & 0x3ff 15 15 ptl0 = (address >> 22) & 0x3ff 16 print "Ptl0: %3d" % ptl017 print "Ptl1: %3d" % ptl118 print "Offset: 0x%x" % offset16 print("Ptl0: %3d" % ptl0) 17 print("Ptl1: %3d" % ptl1) 18 print("Offset: 0x%x" % offset) 19 19 20 20 if __name__ == '__main__':
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