Changeset 454f1da in mainline for kernel/arch/sparc64/include

Timestamp:

2007-03-26T19:35:28Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5d7daff

Parents:

4638401

Message:

Reworked handling of illegal virtual aliases caused by frame reuse.
We moved the incomplete handling from backend's frame method to
backend's page_fault method. The page_fault method is the one that
can create an illegal alias if it writes the userspace frame using
kernel address with a different page color than the page to which is
this frame mapped in userspace. When we detect this, we do D-cache
shootdown on all processors (!!!).

If we add code that accesses userspace memory from kernel address
space, we will have to check for illegal virtual aliases at all such
places.

I tested this on a 4-way simulated E6500 and a real-world Ultra 5,
which has unfortunatelly only one processor.

This solves ticket #26.

Location:

kernel/arch/sparc64/include

Files:

• cpu.h (modified) (2 diffs)
• interrupt.h (modified) (1 diff)
• mm/cache.h (modified) (1 diff)

kernel/arch/sparc64/include/cpu.h

@@ -40 +40 @@
 #include <arch/asm.h>
 
+#ifdef CONFIG_SMP
+#include <arch/mm/cache.h>
+#endif
+
 #define MANUF_FUJITSU           0x04
 #define MANUF_ULTRASPARC        0x17    /**< UltraSPARC I, UltraSPARC II */
@@ -54 +58 @@
 
 typedef struct {
-        uint32_t mid;                   /**< Processor ID as read from UPA_CONFIG. */
+        uint32_t mid;                   /**< Processor ID as read from
+                                             UPA_CONFIG. */
         ver_reg_t ver;
         uint32_t clock_frequency;       /**< Processor frequency in Hz. */
         uint64_t next_tick_cmpr;        /**< Next clock interrupt should be
-                                                                         generated when the TICK register
-                                                                         matches this value. */
+                                             generated when the TICK register
+                                             matches this value. */
+#ifdef CONFIG_SMP
+        int dcache_active;
+        dcache_shootdown_msg_t dcache_messages[DCACHE_MSG_QUEUE_LEN];
+        count_t dcache_message_count;
+#endif
 } cpu_arch_t;
         

kernel/arch/sparc64/include/interrupt.h

@@ -47 +47 @@
 
 enum {
-        IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI
+        IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI,
+        IPI_DCACHE_SHOOTDOWN
 };              
 

kernel/arch/sparc64/include/mm/cache.h

@@ -44 +44 @@
         dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f)));
 
+/**
+ * Enumerations to differentiate among different scopes of D-Cache
+ * invalidation.
+ */
+typedef enum {
+        DCACHE_INVL_INVALID,
+        DCACHE_INVL_ALL,
+        DCACHE_INVL_COLOR,
+        DCACHE_INVL_FRAME
+} dcache_invalidate_type_t;
+
+/**
+ * Number of messages that can be queued in the cpu_arch_t structure at a time.
+ */
+#define DCACHE_MSG_QUEUE_LEN    10
+
+/** D-cache shootdown message type. */
+typedef struct {
+        dcache_invalidate_type_t type;
+        int color;
+        uintptr_t frame;
+} dcache_shootdown_msg_t;
+
 extern void dcache_flush(void);
 extern void dcache_flush_color(int c);
 extern void dcache_flush_tag(int c, pfn_t tag);
+
+#ifdef CONFIG_SMP
+extern void dcache_shootdown_start(dcache_invalidate_type_t type, int color,
+    uintptr_t frame);
+extern void dcache_shootdown_finalize(void);
+extern void dcache_shootdown_ipi_recv(void); 
+#else
+#define dcache_shootdown_start(t, c, f)
+#define dcache_shootdown_finalize()
+#define dcache_shootdown_ipi_recv()
+#endif /* CONFIG_SMP */
 
 #endif