Changeset 44d0758 in mainline for kernel/arch/sparc64/src/mm

Timestamp:

2006-11-22T18:35:17Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

aca95f6b

Parents:

eb353b3

Message:

Add option to compile the sparc64 kernel without the TTE_CV bit support.
The bit is not used by default now.
Enabling it may theoretically lead to physical memory inconsistencies until code that
mitigates the problem is written.

Location:

kernel/arch/sparc64/src/mm

Files:

• tlb.c (modified) (3 diffs)
• tsb.c (modified) (2 diffs)

kernel/arch/sparc64/src/mm/tlb.c

@@ -112 +112 @@
         data.l = locked;
         data.cp = cacheable;
+#ifdef CONFIG_VIRT_IDX_CACHE
         data.cv = cacheable;
+#endif /* CONFIG_VIRT_IDX_CACHE */
         data.p = true;
         data.w = true;
@@ -147 +149 @@
         data.l = false;
         data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
         data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
         data.p = t->k;          /* p like privileged */
         data.w = ro ? false : t->w;
@@ -181 +185 @@
         data.l = false;
         data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
         data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
         data.p = t->k;          /* p like privileged */
         data.w = false;

kernel/arch/sparc64/src/mm/tsb.c

@@ -101 +101 @@
         tsb->data.pfn = t->frame >> PAGE_WIDTH;
         tsb->data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
         tsb->data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
         tsb->data.p = t->k;             /* p as privileged */
         tsb->data.v = t->p;
@@ -141 +143 @@
         tsb->data.pfn = t->frame >> PAGE_WIDTH;
         tsb->data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
         tsb->data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
         tsb->data.p = t->k;             /* p as privileged */
         tsb->data.w = ro ? false : t->w;