Changeset 43114c5 in mainline for arch/ia32/src


Ignore:
Timestamp:
2005-04-09T18:22:53Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8262010
Parents:
e6ba9a3f
Message:

Introduce macros CPU, THREAD, TASK and use them to replace the→cpu, the→thread, the→task.
Later on, this will make it possible to reference *current* cpu, thread and/or task without the aid from virtual memory.

Location:
arch/ia32/src
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • arch/ia32/src/cpu/cpu.c

    re6ba9a3f r43114c5  
    6262void cpu_arch_init(void)
    6363{
    64         the->cpu->arch.tss = tss_p;
     64        CPU->arch.tss = tss_p;
    6565}
    6666
     
    7171        int i;
    7272
    73         the->cpu->arch.vendor = VendorUnknown;
     73        CPU->arch.vendor = VendorUnknown;
    7474        if (has_cpuid()) {
    7575                cpuid(0, &info);
     
    8282                    info.cpuid_edx==AMD_CPUID_EDX) {
    8383                       
    84                         the->cpu->arch.vendor = VendorAMD;
     84                        CPU->arch.vendor = VendorAMD;
    8585                }
    8686
     
    9292                    info.cpuid_edx==INTEL_CPUID_EDX) {
    9393
    94                         the->cpu->arch.vendor = VendorIntel;
     94                        CPU->arch.vendor = VendorIntel;
    9595
    9696                }
    9797                               
    9898                cpuid(1, &info);
    99                 the->cpu->arch.family = (info.cpuid_eax>>8)&0xf;
    100                 the->cpu->arch.model = (info.cpuid_eax>>4)&0xf;
    101                 the->cpu->arch.stepping = (info.cpuid_eax>>0)&0xf;                                             
     99                CPU->arch.family = (info.cpuid_eax>>8)&0xf;
     100                CPU->arch.model = (info.cpuid_eax>>4)&0xf;
     101                CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                                           
    102102        }
    103103}
  • arch/ia32/src/drivers/i8042.c

    re6ba9a3f r43114c5  
    5555        trap_virtual_eoi();
    5656        x = inb(0x60);
    57         printf("%d", the->cpu->id);;
     57        printf("%d", CPU->id);;
    5858}
  • arch/ia32/src/drivers/i8254.c

    re6ba9a3f r43114c5  
    111111
    112112
    113         the->cpu->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) +
     113        CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) +
    114114                                    (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
    115115       
     
    119119        clk2 = rdtsc();
    120120       
    121         the->cpu->frequency_mhz = (clk2-clk1)>>SHIFT;
     121        CPU->frequency_mhz = (clk2-clk1)>>SHIFT;
    122122
    123123        return;
  • arch/ia32/src/drivers/i8259.c

    re6ba9a3f r43114c5  
    117117void pic_spurious(__u8 n, __u32 stack[])
    118118{
    119         printf("cpu%d: PIC spurious interrupt\n", the->cpu->id);
     119        printf("cpu%d: PIC spurious interrupt\n", CPU->id);
    120120}
  • arch/ia32/src/smp/apic.c

    re6ba9a3f r43114c5  
    115115void apic_spurious(__u8 n, __u32 stack[])
    116116{
    117         printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);
     117        printf("cpu%d: APIC spurious interrupt\n", CPU->id);
    118118}
    119119
     
    143143
    144144/*
    145  * Send all CPUs excluding the->cpu IPI vector.
     145 * Send all CPUs excluding CPU IPI vector.
    146146 */
    147147int l_apic_broadcast_custom_ipi(__u8 vector)
     
    233233        l_apic[TPR] &= TPRClear;
    234234
    235         if (the->cpu->arch.family >= 6)
     235        if (CPU->arch.family >= 6)
    236236                enable_l_apic_in_msr();
    237237       
     
    271271        int i, lint;
    272272
    273         printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);
     273        printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);
    274274
    275275        printf("LVT_Tm: ");
     
    305305         * This register is supported only on P6 and higher.
    306306         */
    307         if (the->cpu->family > 5) {
     307        if (CPU->family > 5) {
    308308                printf("LVT_PCINT: ");
    309309                if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  • arch/ia32/src/userspace.c

    re6ba9a3f r43114c5  
    4343         * Prepare TSS stack selector and pointers for next syscall.
    4444         */
    45         the->cpu->arch.tss->esp0 = (__address) &the->thread->kstack[THREAD_STACK_SIZE-8];
    46         the->cpu->arch.tss->ss0 = selector(KDATA_DES);
     45        CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-8];
     46        CPU->arch.tss->ss0 = selector(KDATA_DES);
    4747       
    4848        __asm__ volatile (""
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