Changeset 43114c5 in mainline for arch/ia32/src
- Timestamp:
- 2005-04-09T18:22:53Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8262010
- Parents:
- e6ba9a3f
- Location:
- arch/ia32/src
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/src/cpu/cpu.c
re6ba9a3f r43114c5 62 62 void cpu_arch_init(void) 63 63 { 64 the->cpu->arch.tss = tss_p;64 CPU->arch.tss = tss_p; 65 65 } 66 66 … … 71 71 int i; 72 72 73 the->cpu->arch.vendor = VendorUnknown;73 CPU->arch.vendor = VendorUnknown; 74 74 if (has_cpuid()) { 75 75 cpuid(0, &info); … … 82 82 info.cpuid_edx==AMD_CPUID_EDX) { 83 83 84 the->cpu->arch.vendor = VendorAMD;84 CPU->arch.vendor = VendorAMD; 85 85 } 86 86 … … 92 92 info.cpuid_edx==INTEL_CPUID_EDX) { 93 93 94 the->cpu->arch.vendor = VendorIntel;94 CPU->arch.vendor = VendorIntel; 95 95 96 96 } 97 97 98 98 cpuid(1, &info); 99 the->cpu->arch.family = (info.cpuid_eax>>8)&0xf;100 the->cpu->arch.model = (info.cpuid_eax>>4)&0xf;101 the->cpu->arch.stepping = (info.cpuid_eax>>0)&0xf;99 CPU->arch.family = (info.cpuid_eax>>8)&0xf; 100 CPU->arch.model = (info.cpuid_eax>>4)&0xf; 101 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf; 102 102 } 103 103 } -
arch/ia32/src/drivers/i8042.c
re6ba9a3f r43114c5 55 55 trap_virtual_eoi(); 56 56 x = inb(0x60); 57 printf("%d", the->cpu->id);;57 printf("%d", CPU->id);; 58 58 } -
arch/ia32/src/drivers/i8254.c
re6ba9a3f r43114c5 111 111 112 112 113 the->cpu->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) +113 CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + 114 114 (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); 115 115 … … 119 119 clk2 = rdtsc(); 120 120 121 the->cpu->frequency_mhz = (clk2-clk1)>>SHIFT;121 CPU->frequency_mhz = (clk2-clk1)>>SHIFT; 122 122 123 123 return; -
arch/ia32/src/drivers/i8259.c
re6ba9a3f r43114c5 117 117 void pic_spurious(__u8 n, __u32 stack[]) 118 118 { 119 printf("cpu%d: PIC spurious interrupt\n", the->cpu->id);119 printf("cpu%d: PIC spurious interrupt\n", CPU->id); 120 120 } -
arch/ia32/src/smp/apic.c
re6ba9a3f r43114c5 115 115 void apic_spurious(__u8 n, __u32 stack[]) 116 116 { 117 printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);117 printf("cpu%d: APIC spurious interrupt\n", CPU->id); 118 118 } 119 119 … … 143 143 144 144 /* 145 * Send all CPUs excluding the->cpuIPI vector.145 * Send all CPUs excluding CPU IPI vector. 146 146 */ 147 147 int l_apic_broadcast_custom_ipi(__u8 vector) … … 233 233 l_apic[TPR] &= TPRClear; 234 234 235 if ( the->cpu->arch.family >= 6)235 if (CPU->arch.family >= 6) 236 236 enable_l_apic_in_msr(); 237 237 … … 271 271 int i, lint; 272 272 273 printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);273 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf); 274 274 275 275 printf("LVT_Tm: "); … … 305 305 * This register is supported only on P6 and higher. 306 306 */ 307 if ( the->cpu->family > 5) {307 if (CPU->family > 5) { 308 308 printf("LVT_PCINT: "); 309 309 if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(','); -
arch/ia32/src/userspace.c
re6ba9a3f r43114c5 43 43 * Prepare TSS stack selector and pointers for next syscall. 44 44 */ 45 the->cpu->arch.tss->esp0 = (__address) &the->thread->kstack[THREAD_STACK_SIZE-8];46 the->cpu->arch.tss->ss0 = selector(KDATA_DES);45 CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-8]; 46 CPU->arch.tss->ss0 = selector(KDATA_DES); 47 47 48 48 __asm__ volatile (""
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