Changeset 3bacee1 in mainline for uspace/drv/bus/usb/ehci
- Timestamp:
- 2018-04-12T16:27:17Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3cf22f9
- Parents:
- 76d0981d
- git-author:
- Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)
- Location:
- uspace/drv/bus/usb/ehci
- Files:
-
- 5 edited
-
ehci_batch.c (modified) (11 diffs)
-
ehci_rh.c (modified) (13 diffs)
-
hc.c (modified) (11 diffs)
-
hw_struct/transfer_descriptor.c (modified) (2 diffs)
-
res.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ehci/ehci_batch.c
r76d0981d r3bacee1 53 53 #define EHCI_TD_MAX_TRANSFER (16 * 1024) 54 54 55 static void (*const batch_setup[])(ehci_transfer_batch_t *);55 static void (*const batch_setup[])(ehci_transfer_batch_t *); 56 56 57 57 /** Safely destructs ehci_transfer_batch_t structure … … 74 74 * 75 75 */ 76 ehci_transfer_batch_t * ehci_transfer_batch_create(endpoint_t *ep)76 ehci_transfer_batch_t *ehci_transfer_batch_create(endpoint_t *ep) 77 77 { 78 78 assert(ep); … … 99 99 assert(ehci_batch); 100 100 101 const size_t setup_size = (ehci_batch->base.ep->transfer_type == USB_TRANSFER_CONTROL) 102 ? USB_SETUP_PACKET_SIZE103 :0;101 const size_t setup_size = (ehci_batch->base.ep->transfer_type == USB_TRANSFER_CONTROL) ? 102 USB_SETUP_PACKET_SIZE : 103 0; 104 104 105 105 const size_t size = ehci_batch->base.size; … … 109 109 110 110 /* Determine number of TDs needed */ 111 ehci_batch->td_count = (size + EHCI_TD_MAX_TRANSFER - 1) 112 /EHCI_TD_MAX_TRANSFER;111 ehci_batch->td_count = (size + EHCI_TD_MAX_TRANSFER - 1) / 112 EHCI_TD_MAX_TRANSFER; 113 113 114 114 /* Control transfer need Setup and Status stage */ … … 173 173 ehci_batch->qh->next, ehci_batch->qh->alternate); 174 174 175 if (!qh_halted(ehci_batch->qh) && (qh_transfer_pending(ehci_batch->qh) 176 ||qh_transfer_active(ehci_batch->qh)))175 if (!qh_halted(ehci_batch->qh) && (qh_transfer_pending(ehci_batch->qh) || 176 qh_transfer_active(ehci_batch->qh))) 177 177 return false; 178 178 … … 204 204 * we leave the very last(unused) TD behind. 205 205 */ 206 ehci_batch->base.transferred_size 207 -=td_remain_size(&ehci_batch->tds[i]);206 ehci_batch->base.transferred_size -= 207 td_remain_size(&ehci_batch->tds[i]); 208 208 } else { 209 209 usb_log_debug("Batch %p found error TD(%zu):%08x: %s.", … … 274 274 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, ehci_batch->setup_buffer), 275 275 USB_DIRECTION_BOTH, USB_SETUP_PACKET_SIZE, toggle, false); 276 usb_log_debug2("Batch %p: Created CONTROL SETUP TD(%" PRIxn"): "276 usb_log_debug2("Batch %p: Created CONTROL SETUP TD(%" PRIxn "): " 277 277 "%08x:%08x:%08x", ehci_batch, 278 278 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, &ehci_batch->tds[0]), … … 292 292 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, &ehci_batch->tds[td_current + 1]), 293 293 buffer, data_dir, transfer_size, toggle, false); 294 usb_log_debug2("Batch %p: Created CONTROL DATA TD(%" PRIxn"): "294 usb_log_debug2("Batch %p: Created CONTROL DATA TD(%" PRIxn "): " 295 295 "%08x:%08x:%08x", ehci_batch, 296 296 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, &ehci_batch->tds[td_current]), … … 308 308 assert(td_current == ehci_batch->td_count - 1); 309 309 td_init(&ehci_batch->tds[td_current], 0, 0, status_dir, 0, 1, true); 310 usb_log_debug2("Batch %p: Created CONTROL STATUS TD %d(%" PRIxn"): "310 usb_log_debug2("Batch %p: Created CONTROL STATUS TD %d(%" PRIxn "): " 311 311 "%08x:%08x:%08x", ehci_batch, td_current, 312 312 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, &ehci_batch->tds[td_current]), … … 340 340 ehci_batch->data_buffer); 341 341 while (remain_size > 0) { 342 const size_t transfer_size = remain_size > EHCI_TD_MAX_TRANSFER 343 ?EHCI_TD_MAX_TRANSFER : remain_size;342 const size_t transfer_size = remain_size > EHCI_TD_MAX_TRANSFER ? 343 EHCI_TD_MAX_TRANSFER : remain_size; 344 344 345 345 const bool last = (remain_size == transfer_size); 346 346 td_init(&ehci_batch->tds[td_current], 347 347 last ? 0 : dma_buffer_phys(&ehci_batch->ehci_dma_buffer, 348 &ehci_batch->tds[td_current + 1]),348 &ehci_batch->tds[td_current + 1]), 349 349 buffer, ehci_batch->base.dir, transfer_size, -1, last); 350 350 351 usb_log_debug2("Batch %p: DATA TD(%" PRIxn": %08x:%08x:%08x",351 usb_log_debug2("Batch %p: DATA TD(%" PRIxn ": %08x:%08x:%08x", 352 352 ehci_batch, 353 353 dma_buffer_phys(&ehci_batch->ehci_dma_buffer, 354 &ehci_batch->tds[td_current]),354 &ehci_batch->tds[td_current]), 355 355 ehci_batch->tds[td_current].status, 356 356 ehci_batch->tds[td_current].next, … … 365 365 366 366 /** Transfer setup table. */ 367 static void (*const batch_setup[])(ehci_transfer_batch_t *) =368 {367 static void (*const batch_setup[])(ehci_transfer_batch_t *) = 368 { 369 369 [USB_TRANSFER_CONTROL] = batch_control, 370 370 [USB_TRANSFER_BULK] = batch_data, -
uspace/drv/bus/usb/ehci/ehci_rh.c
r76d0981d r3bacee1 119 119 } 120 120 for (unsigned i = 0; i < instance->port_count; ++i) 121 usb_log_debug2("RH(%p-%u): status: %" PRIx32, instance, i,121 usb_log_debug2("RH(%p-%u): status: %" PRIx32, instance, i, 122 122 EHCI_RD(regs->portsc[i])); 123 123 … … 147 147 assert(batch); 148 148 batch->error = virthub_base_request(&instance->base, batch->target, 149 batch->dir, (void *) batch->setup.buffer,149 batch->dir, (void *) batch->setup.buffer, 150 150 batch->dma_buffer.virt, batch->size, 151 151 &batch->transferred_size); … … 195 195 } 196 196 197 usb_transfer_batch_t * const batch = ep->active_batch;197 usb_transfer_batch_t *const batch = ep->active_batch; 198 198 endpoint_deactivate_locked(ep); 199 199 instance->status_change_endpoint = NULL; … … 206 206 instance, batch); 207 207 batch->error = virthub_base_request(&instance->base, batch->target, 208 batch->dir, (void *) batch->setup.buffer,208 batch->dir, (void *) batch->setup.buffer, 209 209 batch->dma_buffer.virt, batch->size, 210 210 &batch->transferred_size); … … 304 304 EHCI2USB(reg, USB_PORTSC_PORT_POWER_FLAG, USB2_HUB_PORT_STATUS_POWER) | 305 305 (((reg & USB_PORTSC_LINE_STATUS_MASK) == USB_PORTSC_LINE_STATUS_K) ? 306 (USB2_HUB_PORT_STATUS_LOW_SPEED) : 0) |306 (USB2_HUB_PORT_STATUS_LOW_SPEED) : 0) | 307 307 ((reg & USB_PORTSC_PORT_OWNER_FLAG) ? 0 : USB2_HUB_PORT_STATUS_HIGH_SPEED) | 308 308 EHCI2USB(reg, USB_PORTSC_PORT_TEST_MASK, USB2_HUB_PORT_STATUS_TEST) | … … 312 312 (hub->resume_flag[port] ? USB2_HUB_PORT_STATUS_C_SUSPEND : 0) | 313 313 EHCI2USB(reg, USB_PORTSC_OC_CHANGE_FLAG, USB_HUB_PORT_STATUS_C_OC) | 314 (hub->reset_flag[port] ? USB_HUB_PORT_STATUS_C_RESET: 0) 315 ); 314 (hub->reset_flag[port] ? USB_HUB_PORT_STATUS_C_RESET : 0)); 316 315 /* Note feature numbers for test and indicator feature do not 317 316 * correspond to the port status bit locations */ 318 usb_log_debug2("RH(%p-%u) port status: %" PRIx32"(%"PRIx32")", hub, port,317 usb_log_debug2("RH(%p-%u) port status: %" PRIx32 "(%" PRIx32 ")", hub, port, 319 318 status, reg); 320 319 memcpy(data, &status, sizeof(status)); … … 345 344 if (!(EHCI_RD(job->hub->registers->portsc[job->port]) & 346 345 USB_PORTSC_ENABLED_FLAG)) { 347 usb_log_info("RH(%p-%u): Port not enabled after reset (%" PRIX32346 usb_log_info("RH(%p-%u): Port not enabled after reset (%" PRIX32 348 347 "), giving up ownership", job->hub, job->port, 349 348 EHCI_RD(job->hub->registers->portsc[job->port])); … … 370 369 } 371 370 372 static errno_t delayed_job(errno_t (*func)(void *), ehci_rh_t *rh, unsigned port)371 static errno_t delayed_job(errno_t (*func)(void *), ehci_rh_t *rh, unsigned port) 373 372 { 374 373 ehci_rh_job_t *job = malloc(sizeof(*job)); … … 405 404 const unsigned feature = uint16_usb2host(setup_packet->value); 406 405 /* Enabled features to clear: see page 269 of USB specs */ 407 switch (feature) 408 { 406 switch (feature) { 409 407 case USB_HUB_FEATURE_PORT_POWER: /*8*/ 410 408 usb_log_debug2("RH(%p-%u): Clear port power.", hub, port); … … 424 422 if ((EHCI_RD(hub->registers->portsc[port]) & 425 423 USB_PORTSC_SUSPEND_FLAG) == 0) 426 return EOK;424 return EOK; 427 425 /* Host driven resume */ 428 426 EHCI_SET(hub->registers->portsc[port], … … 542 540 if ((status & USB_PORTSC_CONNECT_CH_FLAG) && 543 541 (status & USB_PORTSC_LINE_STATUS_MASK) == 544 USB_PORTSC_LINE_STATUS_K)542 USB_PORTSC_LINE_STATUS_K) 545 543 EHCI_SET(hub->registers->portsc[port], 546 544 USB_PORTSC_PORT_OWNER_FLAG); … … 550 548 } 551 549 552 usb_log_debug2("RH(%p): root hub interrupt mask: %" PRIx16, hub, mask);550 usb_log_debug2("RH(%p): root hub interrupt mask: %" PRIx16, hub, mask); 553 551 554 552 if (mask == 0) … … 619 617 /** Virtual EHCI root hub ops */ 620 618 static usbvirt_device_ops_t ops = { 621 .control = control_transfer_handlers,622 .data_in[HUB_STATUS_CHANGE_PIPE] = req_status_change_handler,619 .control = control_transfer_handlers, 620 .data_in[HUB_STATUS_CHANGE_PIPE] = req_status_change_handler, 623 621 }; -
uspace/drv/bus/usb/ehci/hc.c
r76d0981d r3bacee1 133 133 134 134 ehci_regs_t *registers = 135 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength));135 (ehci_regs_t *)(RNGABSPTR(regs) + EHCI_RD8(instance->caps->caplength)); 136 136 code->cmds[0].addr = (void *) ®isters->usbsts; 137 137 code->cmds[3].addr = (void *) ®isters->usbsts; … … 158 158 if (hw_res->mem_ranges.count != 1 || 159 159 hw_res->mem_ranges.ranges[0].size < 160 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t)))161 return EINVAL;160 (sizeof(ehci_caps_regs_t) + sizeof(ehci_regs_t))) 161 return EINVAL; 162 162 163 163 errno_t ret = pio_enable_range(&hw_res->mem_ranges.ranges[0], … … 169 169 } 170 170 171 usb_log_info("HC(%p): Device registers at %" PRIx64" (%zuB) accessible.",171 usb_log_info("HC(%p): Device registers at %" PRIx64 " (%zuB) accessible.", 172 172 instance, hw_res->mem_ranges.ranges[0].address.absolute, 173 173 hw_res->mem_ranges.ranges[0].size); 174 174 instance->registers = 175 (void *)instance->caps + EHCI_RD8(instance->caps->caplength);175 (void *)instance->caps + EHCI_RD8(instance->caps->caplength); 176 176 usb_log_info("HC(%p): Device control registers at %" PRIx64, instance, 177 hw_res->mem_ranges.ranges[0].address.absolute 178 +EHCI_RD8(instance->caps->caplength));177 hw_res->mem_ranges.ranges[0].address.absolute + 178 EHCI_RD8(instance->caps->caplength)); 179 179 180 180 list_initialize(&instance->pending_endpoints); … … 221 221 usb_str_transfer_type_short(ep->transfer_type), 222 222 usb_str_direction(ep->direction)); 223 switch (ep->transfer_type) 224 { 223 switch (ep->transfer_type) { 225 224 case USB_TRANSFER_CONTROL: 226 225 case USB_TRANSFER_BULK: … … 245 244 usb_str_transfer_type_short(ep->transfer_type), 246 245 usb_str_direction(ep->direction)); 247 switch (ep->transfer_type) 248 { 246 switch (ep->transfer_type) { 249 247 case USB_TRANSFER_INTERRUPT: 250 248 endpoint_list_remove_ep(&instance->int_list, ehci_ep); … … 305 303 } 306 304 307 endpoint_t * const ep = batch->ep;308 ehci_endpoint_t * const ehci_ep = ehci_endpoint_get(ep);305 endpoint_t *const ep = batch->ep; 306 ehci_endpoint_t *const ehci_ep = ehci_endpoint_get(ep); 309 307 ehci_transfer_batch_t *ehci_batch = ehci_transfer_batch_get(batch); 310 308 … … 345 343 assert(hc); 346 344 347 usb_log_debug2("HC(%p): Interrupt: %" PRIx32, hc, status);345 usb_log_debug2("HC(%p): Interrupt: %" PRIx32, hc, status); 348 346 if (status & USB_STS_PORT_CHANGE_FLAG) { 349 347 ehci_rh_interrupt(&hc->rh); … … 361 359 362 360 usb_log_debug2("HC(%p): Scanning %lu pending endpoints", hc, 363 list_count(&hc->pending_endpoints));361 list_count(&hc->pending_endpoints)); 364 362 list_foreach_safe(hc->pending_endpoints, current, next) { 365 ehci_endpoint_t *ep 366 =list_get_instance(current, ehci_endpoint_t, pending_link);367 368 ehci_transfer_batch_t *batch 369 =ehci_transfer_batch_get(ep->base.active_batch);363 ehci_endpoint_t *ep = 364 list_get_instance(current, ehci_endpoint_t, pending_link); 365 366 ehci_transfer_batch_t *batch = 367 ehci_transfer_batch_get(ep->base.active_batch); 370 368 assert(batch); 371 369 … … 429 427 assert(instance->periodic_list); 430 428 uintptr_t phys_base = 431 addr_to_phys((void *)instance->periodic_list);429 addr_to_phys((void *)instance->periodic_list); 432 430 assert((phys_base & USB_PERIODIC_LIST_BASE_MASK) == phys_base); 433 431 EHCI_WR(instance->registers->periodiclistbase, phys_base); … … 437 435 438 436 /* Enable Async schedule */ 439 phys_base = addr_to_phys((void *)instance->async_list.list_head);437 phys_base = addr_to_phys((void *)instance->async_list.list_head); 440 438 assert((phys_base & USB_ASYNCLIST_MASK) == phys_base); 441 439 EHCI_WR(instance->registers->asynclistaddr, phys_base); … … 516 514 517 515 usb_log_debug2("HC(%p): Initializing Periodic list.", instance); 518 for (unsigned i = 0; i < PAGE_SIZE/sizeof(link_pointer_t); ++i) 519 { 516 for (unsigned i = 0; i < PAGE_SIZE / sizeof(link_pointer_t); ++i) { 520 517 /* Disable everything for now */ 521 518 instance->periodic_list[i] = -
uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.c
r76d0981d r3bacee1 92 92 ((dir[direction] & TD_STATUS_PID_MASK) << TD_STATUS_PID_SHIFT) | 93 93 ((size & TD_STATUS_TOTAL_MASK) << TD_STATUS_TOTAL_SHIFT) | 94 (ioc ? TD_STATUS_IOC_FLAG : 0) );94 (ioc ? TD_STATUS_IOC_FLAG : 0)); 95 95 96 96 if (toggle == 0 || toggle == 1) { … … 101 101 if (buffer != 0) { 102 102 assert(size != 0); 103 for (unsigned i = 0; (i < ARRAY_SIZE(instance->buffer_pointer)) 104 &&size; ++i) {103 for (unsigned i = 0; (i < ARRAY_SIZE(instance->buffer_pointer)) && 104 size; ++i) { 105 105 const uintptr_t offset = buffer & TD_BUFFER_POINTER_OFFSET_MASK; 106 106 assert(offset == 0 || i == 0); -
uspace/drv/bus/usb/ehci/res.c
r76d0981d r3bacee1 95 95 ret = pci_config_space_read_32( 96 96 parent_sess, eecp + USBLEGSUP_OFFSET, &usblegsup); 97 while ((ret == EOK) && (wait < DEFAULT_WAIT) 98 &&(usblegsup & USBLEGSUP_BIOS_CONTROL)) {97 while ((ret == EOK) && (wait < DEFAULT_WAIT) && 98 (usblegsup & USBLEGSUP_BIOS_CONTROL)) { 99 99 async_usleep(WAIT_STEP); 100 100 ret = pci_config_space_read_32(parent_sess, … … 109 109 110 110 /* BIOS failed to hand over control, this should not happen. */ 111 usb_log_warning( "BIOS failed to release control after "111 usb_log_warning("BIOS failed to release control after " 112 112 "%zu usecs, force it.", wait); 113 113 ret = pci_config_space_write_32(parent_sess, … … 197 197 usb_log_error("Failed to disable extended capabilities: %s.", 198 198 str_error(ret)); 199 goto clean;199 goto clean; 200 200 } 201 201 clean:
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