Changeset 2bd4fdf in mainline for arch/mips/src/exception.c

Timestamp:

2005-09-06T23:10:17Z (20 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0b512a8

Parents:

2c9de7e

Message:

MIPS bug fixes.
Added usermode to MIPS, unfortunately impossible to test until
MM is ready.

File:

• arch/mips/src/exception.c (modified) (3 diffs)

arch/mips/src/exception.c

@@ -40 +40 @@
         __u32 epc;
         __u32 epc_shift = 0;
-        pri_t pri;
 
         ASSERT(CPU != NULL);
@@ -51 +50 @@
          */
 
-        pri = cpu_priority_high();
+        cpu_priority_high();
         epc = cp0_epc_read();
-        cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
+        cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
+                                                cp0_status_um_bit));
 
         if (THREAD) {
-                THREAD->saved_pri = pri;
                 THREAD->saved_epc = epc;
         }
@@ -116 +115 @@
         }
         
-        if (THREAD) {
-                pri = THREAD->saved_pri;
+        if (THREAD)
                 epc = THREAD->saved_epc;
-        }
-
+        
+        /* Raise EXL bit before epc_write, so that we support
+         * properly nested exceptions
+         */
+        cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);
         cp0_epc_write(epc + epc_shift);
-        cp0_status_write(cp0_status_read() | cp0_status_exl_exception_bit);
-        cpu_priority_restore(pri);
 }