Changeset 22f0561 in mainline for kernel/arch/ia64/src
- Timestamp:
- 2011-12-31T00:12:58Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 2107e79, c520034
- Parents:
- efb48eb
- Location:
- kernel/arch/ia64/src
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/src/ia64.c
refb48eb r22f0561 45 45 #include <arch/drivers/it.h> 46 46 #include <arch/drivers/kbd.h> 47 #include <arch/legacyio.h> 47 48 #include <genarch/drivers/ega/ega.h> 48 49 #include <genarch/drivers/i8042/i8042.h> … … 51 52 #include <genarch/kbrd/kbrd.h> 52 53 #include <genarch/srln/srln.h> 54 #include <mm/page.h> 55 56 #ifdef MACHINE_ski 57 #include <arch/drivers/ski.h> 58 #endif 53 59 54 60 /* NS16550 as a COM 1 */ … … 58 64 59 65 static uint64_t iosapic_base = 0xfec00000; 66 uintptr_t legacyio_virt_base = 0; 60 67 61 68 /** Performs ia64-specific initialization before main_bsp() is called. */ … … 80 87 static void iosapic_init(void) 81 88 { 82 uint 64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET;89 uintptr_t IOSAPIC = hw_map(iosapic_base, PAGE_SIZE); 83 90 int i; 84 91 … … 107 114 { 108 115 if (config.cpu_active == 1) { 116 /* Map the page with legacy I/O. */ 117 legacyio_virt_base = hw_map(LEGACYIO_PHYS_BASE, LEGACYIO_SIZE); 118 109 119 iosapic_init(); 110 120 irq_init(INR_COUNT, INR_COUNT); … … 113 123 } 114 124 115 void arch_post_cpu_init(void) 116 { 125 void arch_post_cpu_init(void){ 117 126 } 118 127 … … 202 211 sysinfo_set_item_val("ia64_iospace", NULL, true); 203 212 sysinfo_set_item_val("ia64_iospace.address", NULL, true); 204 sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET);213 sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, LEGACYIO_USER_BASE); 205 214 } 206 215 -
kernel/arch/ia64/src/mm/tlb.c
refb48eb r22f0561 52 52 #include <arch.h> 53 53 #include <interrupt.h> 54 55 #define IO_FRAME_BASE 0xFFFFC000000 54 #include <arch/legacyio.h> 56 55 57 56 /** Invalidate all TLB entries. */ … … 530 529 static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) 531 530 { 532 if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 <<IO_PAGE_WIDTH))) {531 if ((va >= LEGACYIO_USER_BASE) && (va < LEGACYIO_USER_BASE + (1 << LEGACYIO_PAGE_WIDTH))) { 533 532 if (TASK) { 534 uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>535 USPACE_IO_PAGE_WIDTH;533 uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >> 534 LEGACYIO_SINGLE_PAGE_WIDTH; 536 535 537 536 if (is_io_page_accessible(io_page)) { 538 537 uint64_t page, frame; 539 538 540 page = IO_OFFSET+541 (1 << USPACE_IO_PAGE_WIDTH) * io_page;542 frame = IO_FRAME_BASE +543 (1 << USPACE_IO_PAGE_WIDTH) * io_page;539 page = LEGACYIO_USER_BASE + 540 (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; 541 frame = LEGACYIO_PHYS_BASE + 542 (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; 544 543 545 544 tlb_entry_t entry; … … 555 554 entry.ar = AR_READ | AR_WRITE; 556 555 entry.ppn = frame >> PPN_SHIFT; 557 entry.ps = USPACE_IO_PAGE_WIDTH;556 entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH; 558 557 559 558 dtc_mapping_insert(page, TASK->as->asid, entry); -
kernel/arch/ia64/src/start.S
refb48eb r22f0561 38 38 #define KERNEL_TRANSLATION_I 0x0010000000000661 39 39 #define KERNEL_TRANSLATION_D 0x0010000000000661 40 #define KERNEL_TRANSLATION_VIO 0x0010000000000671 // FIXME: [non-ident]41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 // FIXME: [non-ident]42 #define KERNEL_TRANSLATION_FW 0x00100000F0000671 // FIXME: [non-ident]43 40 44 41 .section K_TEXT_START, "ax" … … 88 85 itr.d dtr[r0] = r10 89 86 90 movl r7 = 1 91 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET 92 mov cr.ifa = r8 93 movl r10 = (KERNEL_TRANSLATION_VIO) 94 itr.d dtr[r7] = r10 95 96 mov r11 = cr.itir 97 movl r10 = ~0xfc 98 and r10 = r10, r11 99 movl r11 = (IO_PAGE_WIDTH << PS_SHIFT) 100 or r10 = r10, r11 101 mov cr.itir = r10 102 103 movl r7 = 2 104 movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET 105 mov cr.ifa = r8 106 movl r10 = (KERNEL_TRANSLATION_IO) 107 itr.d dtr[r7] = r10 108 109 # Setup mapping for firmware area (also SAPIC) 110 111 mov r11 = cr.itir 112 movl r10 = ~0xfc 113 and r10 = r10, r11 114 movl r11 = (FW_PAGE_WIDTH << PS_SHIFT) 115 or r10 = r10, r11 116 mov cr.itir = r10 117 118 movl r7 = 3 119 movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET 120 mov cr.ifa = r8 121 movl r10 = (KERNEL_TRANSLATION_FW) 122 itr.d dtr[r7] = r10 123 124 # Initialize DSR 87 # Initialize DCR 125 88 126 89 movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
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