Changeset 0dc2fec in mainline for kernel/arch/amd64/src/smp/ap.S

Timestamp:

2016-05-22T19:19:43Z (9 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b272c67a

Parents:

153c7a29 (diff), af2254ec (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• kernel/arch/amd64/src/smp/ap.S (modified) (5 diffs)

kernel/arch/amd64/src/smp/ap.S

@@ -39 +39 @@
 #include <arch/cpu.h>
 #include <arch/cpuid.h>
+#include <arch/context_struct.h>
 
 .section K_TEXT_START, "ax"
@@ -58 +59 @@
         
         movl %cr0, %eax
-        orl $1, %eax
+        orl $CR0_PE, %eax
         movl %eax, %cr0     # switch to protected mode
         jmpl $GDT_SELECTOR(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET
@@ -75 +76 @@
         
         movl %cr4, %eax
-        btsl $5, %eax
+        orl $CR4_PAE, %eax
         movl %eax, %cr4
         
@@ -82 +83 @@
         
         # Enable long mode
-        movl $EFER_MSR_NUM, %ecx  # EFER MSR number
+        movl $AMD_MSR_EFER, %ecx  # EFER MSR number
         rdmsr                     # Read EFER
-        btsl $AMD_LME_FLAG, %eax  # Set LME=1
+        orl $AMD_LME, %eax        # Set LME=1
         wrmsr                     # Write EFER
         
         # Enable paging to activate long mode (set CR0.PG = 1)
         movl %cr0, %eax
-        btsl $31, %eax
+        orl $CR0_PG, %eax
         movl %eax, %cr0
         
@@ -98 +99 @@
 start64:
         movabsq $ctx, %rsp
-        movq (%rsp), %rsp
+        movq CONTEXT_OFFSET_SP(%rsp), %rsp
         
         pushq $0