Changeset 0cf1dcf in mainline for kernel/arch/sparc64/src

Timestamp:

2006-11-28T23:03:04Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

058b021

Parents:

d4b5542

Message:

Indentation and comment fixes.

Location:

kernel/arch/sparc64/src

Files:

• mm/tsb.c (modified) (2 diffs)
• start.S (modified) (1 diff)

kernel/arch/sparc64/src/mm/tsb.c

@@ -99 +99 @@
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = t->frame >> PAGE_WIDTH;
+        tsb->data.pfn = t->frame >> FRAME_WIDTH;
         tsb->data.cp = t->c;
 #ifdef CONFIG_VIRT_IDX_CACHE
@@ -141 +141 @@
         tsb->data.value = 0;
         tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = t->frame >> PAGE_WIDTH;
+        tsb->data.pfn = t->frame >> FRAME_WIDTH;
         tsb->data.cp = t->c;
 #ifdef CONFIG_VIRT_IDX_CACHE

kernel/arch/sparc64/src/start.S

@@ -65 +65 @@
 kernel_image_start:
         mov BSP_FLAG, %l0
-        and %o0, %l0, %l7                               ! l7 <= bootstrap processor?
-        andn %o0, %l0, %l6                              ! l6 <= start of physical memory
+        and %o0, %l0, %l7                       ! l7 <= bootstrap processor?
+        andn %o0, %l0, %l6                      ! l6 <= start of physical memory
 
         ! Get bits 40:13 of physmem_base.
         srlx %l6, 13, %l5
         sllx %l5, 13 + (63 - 40), %l5
-        srlx %l5, 63 - 40, %l5                          ! l5 <= physmem_base[40:13]
+        srlx %l5, 63 - 40, %l5                  ! l5 <= physmem_base[40:13]
         
         /*