Context Navigation

rb2aaaa0	r09ab0a9a
64	64	arch_ops_t *arch_ops = &arm32_ops;
65	65
66
67	66	/** Performs arm32-specific initialization before main_bsp() is called. */
68	67	void arm32_pre_main(void entry __attribute__((unused)), bootinfo_t bootinfo)
…	…
118	117	}
119	118
120
121	119	/** Performs arm32 specific tasks needed before the new task is run. */
122	120	void before_task_runs_arch(void)
123	121	{
124	122	}
125
126	123
127	124	/** Performs arm32 specific tasks needed before the new thread is scheduled.

kernel/arch/arm32/src/cpu/cpu.c

rb2aaaa0	r09ab0a9a
60	60	static unsigned dcache_linesize_log(unsigned level);
61	61
62
63	62	/** Implementers (vendor) names */
64	63	static const char *implementer(unsigned id)
…	…
99	98	return arch_data[0];
100	99	}
101
102	100
103	101	/** Retrieves processor identification from CP15 register 0.
…	…
317	315	}
318	316
319
320	317	void cpu_dcache_flush(void)
321	318	{

-              rb2aaaa0
+              r09ab0a9a
 #include <log.h>
 #define SDRAM_SIZE \
         sdram[(*(uint32_t *) (ICP_CMCR + ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2]
 …
         *((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq);
+}
 /** Unmasks interrupt.

rb2aaaa0	r09ab0a9a
72	72	}
73	73
74
75	74	/** Starts timer. */
76	75	void machine_timer_irq_start(void)
…	…
78	77	(machine_ops->machine_timer_irq_start)();
79	78	}
80
81	79
82	80	/** Halts CPU. */
…	…
105	103	(machine_ops->machine_irq_exception)(exc_no, istate);
106	104	}
107
108	105
109	106	/*

Note: See TracChangeset for help on using the changeset viewer.