Changeset cc74cb5 in mainline

Timestamp:

2018-09-14T23:15:04Z (6 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6f58770

Parents:

09ab0a9a

Message:

Set FPSR.sf1 controls to standard values

The Itanium Software Conventions and Runtime Architecture Guide reserves
the Status Field 1 of FPSR to be used by the divide and square root code
and requires that it has certain standard values.

Location:

kernel/arch/ia64

Files:

• include/arch/context.h (modified) (1 diff)
• include/arch/register.h (modified) (1 diff)
• src/fpu_context.c (modified) (1 diff)

kernel/arch/ia64/include/arch/context.h

@@ -57 +57 @@
                 (c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \
                 (c)->ar_pfs &= PFM_MASK; \
-                (c)->ar_fpsr = FPSR_TRAPS_ALL; \
+                (c)->ar_fpsr = FPSR_TRAPS_ALL | FPSR_SF1_CTRL; \
                 (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \
                 (c)->r1 = (uintptr_t) &__gp; \

kernel/arch/ia64/include/arch/register.h

@@ -78 +78 @@
 #define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \
     FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID)
+
+#define FPSR_SF1_SHIFT 19
+
+#define FPSR_CTRL_WRE           (1 << 1)
+#define FPSR_CTRL_PC_EXTENDED   (3 << 2)
+#define FPSR_CTRL_RC_NEAREST    (0 << 4)
+#define FPSR_CTRL_TD            (1 << 6)
+
+#define FPSR_SF1_CTRL ((FPSR_CTRL_WRE | FPSR_CTRL_PC_EXTENDED | \
+    FPSR_CTRL_RC_NEAREST | FPSR_CTRL_TD) << FPSR_SF1_SHIFT)
 
 /** Application registers. */

kernel/arch/ia64/src/fpu_context.c

@@ -491 +491 @@
             "mov ar.fpsr = %0 ;;\n"
             : "+r" (a)
-            : "r" (FPSR_TRAPS_ALL)
+            : "r" (FPSR_TRAPS_ALL | FPSR_SF1_CTRL)
         );