Context Navigation

rb2aaaa0	r09ab0a9a
584	584	CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
585	585
586
587	586	/c10 has tons of reserved too /
588	587	CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */

kernel/arch/arm32/include/arch/istate_struct.h

rb2aaaa0	r09ab0a9a
97	97	} icp_hw_map_t;
98	98
99
100	99	extern void icp_init(void);
101	100	extern void icp_output_init(void);

-              rb2aaaa0
+              r09ab0a9a
 extern void machine_init(void);
 /** Starts timer. */
 extern void machine_timer_irq_start(void);
 /** Halts CPU. */
 …
  */
 extern void machine_irq_exception(unsigned int exc_no, istate_t *istate);
 /*

rb2aaaa0	r09ab0a9a
131	131	set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
132	132
133
134	133	#define pt_coherence(page) pt_coherence_m(page, 1)
135	134

rb2aaaa0	r09ab0a9a
113	113	#define PTE_AP_USER_RW_KERNEL_RW 3
114	114
115
116	115	/* pte_level0_t and pte_level1_t descriptor_type flags */
117	116
…	…
195	194	}
196	195	}
197
198	196
199	197	/** Sets flags of level 1 page table entry.
…	…
247	245	}
248	246
249
250	247	NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
251	248	{
…	…
255	252	}
256	253
257
258	254	extern void page_arch_init(void);
259	255
260
261	256	#endif /* __ASSEMBLER__ */
262	257

-              rb2aaaa0
+              r09ab0a9a
 #error "Do not include arch specific page.h directly use generic page.h instead"
 #endif
 /* Macros for querying the last-level PTE entries. */
 …
 #define PTE_AP1_RO   1
 /* pte_level0_t and pte_level1_t descriptor_type flags */
 …
 /** pte_level1_t small page table flag with NX (used in descriptor type). */
 #define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
 /**
 …
         pt_coherence(p);
+}
 /** Sets flags of level 1 page table entry.
 …
+}
 extern void page_arch_init(void);

-              rb2aaaa0
+              r09ab0a9a
 #include <stdint.h>
 /** Decribes CP15 "fault status register" (FSR).
+ *
 …
 } fault_status_t;
 /** Simplified description of instruction code.
+ *
 …
 } ATTRIBUTE_PACKED instruction_t;
 /** Help union used for casting pc register (uint_32_t) value into
  *  #instruction_t pointer.

rb2aaaa0	r09ab0a9a
64	64	arch_ops_t *arch_ops = &arm32_ops;
65	65
66
67	66	/** Performs arm32-specific initialization before main_bsp() is called. */
68	67	void arm32_pre_main(void entry __attribute__((unused)), bootinfo_t bootinfo)
…	…
118	117	}
119	118
120
121	119	/** Performs arm32 specific tasks needed before the new task is run. */
122	120	void before_task_runs_arch(void)
123	121	{
124	122	}
125
126	123
127	124	/** Performs arm32 specific tasks needed before the new thread is scheduled.

rb2aaaa0	r09ab0a9a
60	60	static unsigned dcache_linesize_log(unsigned level);
61	61
62
63	62	/** Implementers (vendor) names */
64	63	static const char *implementer(unsigned id)
…	…
99	98	return arch_data[0];
100	99	}
101
102	100
103	101	/** Retrieves processor identification from CP15 register 0.
…	…
317	315	}
318	316
319
320	317	void cpu_dcache_flush(void)
321	318	{

-              rb2aaaa0
+              r09ab0a9a
 #include <log.h>
 #define SDRAM_SIZE \
         sdram[(*(uint32_t *) (ICP_CMCR + ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2]
 …
         *((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq);
+}
 /** Unmasks interrupt.

rb2aaaa0	r09ab0a9a
72	72	}
73	73
74
75	74	/** Starts timer. */
76	75	void machine_timer_irq_start(void)
…	…
78	77	(machine_ops->machine_timer_irq_start)();
79	78	}
80
81	79
82	80	/** Halts CPU. */
…	…
105	103	(machine_ops->machine_irq_exception)(exc_no, istate);
106	104	}
107
108	105
109	106	/*

Note: See TracChangeset for help on using the changeset viewer.