Changeset 09ab0a9a in mainline for kernel/arch
- Timestamp:
- 2018-09-13T12:05:53Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- cc74cb5
- Parents:
- b2aaaa0
- git-author:
- Jiri Svoboda <jiri@…> (2018-09-13 07:09:46)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-09-13 12:05:53)
- Location:
- kernel/arch
- Files:
-
- 84 edited
-
abs32le/src/cpu/cpu.c (modified) (1 diff)
-
abs32le/src/smc.c (modified) (1 diff)
-
amd64/include/arch/boot/memmap_struct.h (modified) (1 diff)
-
amd64/include/arch/context_struct.h (modified) (1 diff)
-
amd64/include/arch/istate_struct.h (modified) (1 diff)
-
amd64/include/arch/kseg_struct.h (modified) (1 diff)
-
amd64/include/arch/mm/ptl.h (modified) (1 diff)
-
amd64/include/arch/pm.h (modified) (1 diff)
-
amd64/src/cpu/cpu.c (modified) (1 diff)
-
amd64/src/smc.c (modified) (1 diff)
-
arm32/include/arch/context_struct.h (modified) (1 diff)
-
arm32/include/arch/cp15.h (modified) (1 diff)
-
arm32/include/arch/istate_struct.h (modified) (1 diff)
-
arm32/include/arch/mach/beagleboardxm/beagleboardxm.h (modified) (1 diff)
-
arm32/include/arch/mach/beaglebone/beaglebone.h (modified) (1 diff)
-
arm32/include/arch/mach/integratorcp/integratorcp.h (modified) (1 diff)
-
arm32/include/arch/machine_func.h (modified) (2 diffs)
-
arm32/include/arch/mm/page.h (modified) (1 diff)
-
arm32/include/arch/mm/page_armv4.h (modified) (4 diffs)
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arm32/include/arch/mm/page_armv6.h (modified) (5 diffs)
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arm32/include/arch/mm/page_fault.h (modified) (3 diffs)
-
arm32/src/arm32.c (modified) (2 diffs)
-
arm32/src/cpu/cpu.c (modified) (3 diffs)
-
arm32/src/fpu_context.c (modified) (2 diffs)
-
arm32/src/mach/beaglebone/beaglebone.c (modified) (1 diff)
-
arm32/src/mach/integratorcp/integratorcp.c (modified) (2 diffs)
-
arm32/src/machine_func.c (modified) (3 diffs)
-
arm32/src/mm/page_fault.c (modified) (1 diff)
-
arm32/src/smc.c (modified) (1 diff)
-
ia32/include/arch/asm.h (modified) (1 diff)
-
ia32/include/arch/context_struct.h (modified) (1 diff)
-
ia32/include/arch/istate_struct.h (modified) (1 diff)
-
ia32/include/arch/smp/apic.h (modified) (1 diff)
-
ia32/src/cpu/cpu.c (modified) (1 diff)
-
ia32/src/smc.c (modified) (1 diff)
-
ia64/include/arch/context_struct.h (modified) (1 diff)
-
ia64/include/arch/istate_struct.h (modified) (1 diff)
-
ia64/include/arch/proc/task.h (modified) (1 diff)
-
ia64/src/ia64.c (modified) (1 diff)
-
ia64/src/interrupt.c (modified) (1 diff)
-
ia64/src/mm/tlb.c (modified) (3 diffs)
-
ia64/src/mm/vhpt.c (modified) (1 diff)
-
ia64/src/smc.c (modified) (1 diff)
-
ia64/src/smp/smp.c (modified) (1 diff)
-
mips32/include/arch/context_struct.h (modified) (1 diff)
-
mips32/include/arch/debugger.h (modified) (1 diff)
-
mips32/include/arch/fpu_context_struct.h (modified) (1 diff)
-
mips32/include/arch/istate_struct.h (modified) (1 diff)
-
mips32/include/arch/mm/page.h (modified) (1 diff)
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mips32/include/arch/mm/tlb.h (modified) (1 diff)
-
mips32/include/arch/proc/thread.h (modified) (1 diff)
-
mips32/src/debug/stacktrace.c (modified) (1 diff)
-
mips32/src/machine_func.c (modified) (1 diff)
-
mips32/src/mm/frame.c (modified) (2 diffs)
-
mips32/src/smc.c (modified) (1 diff)
-
ppc32/include/arch/context_struct.h (modified) (1 diff)
-
ppc32/include/arch/fpu_context_struct.h (modified) (1 diff)
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ppc32/include/arch/istate.h (modified) (1 diff)
-
ppc32/include/arch/istate_struct.h (modified) (1 diff)
-
ppc32/src/smc.c (modified) (2 diffs)
-
riscv64/include/arch/context_struct.h (modified) (1 diff)
-
riscv64/include/arch/istate_struct.h (modified) (1 diff)
-
riscv64/src/cpu/cpu.c (modified) (1 diff)
-
riscv64/src/smc.c (modified) (1 diff)
-
sparc64/include/arch/context_struct.h (modified) (1 diff)
-
sparc64/include/arch/cpu.h (modified) (1 diff)
-
sparc64/include/arch/cpu_family.h (modified) (1 diff)
-
sparc64/include/arch/cpu_node.h (modified) (2 diffs)
-
sparc64/include/arch/istate_struct.h (modified) (1 diff)
-
sparc64/include/arch/mm/km.h (modified) (1 diff)
-
sparc64/include/arch/mm/mmu.h (modified) (1 diff)
-
sparc64/include/arch/mm/sun4u/mmu.h (modified) (1 diff)
-
sparc64/include/arch/mm/sun4u/tlb.h (modified) (4 diffs)
-
sparc64/include/arch/mm/sun4v/tsb.h (modified) (1 diff)
-
sparc64/include/arch/sun4v/hypercall.h (modified) (3 diffs)
-
sparc64/include/arch/trap/interrupt.h (modified) (1 diff)
-
sparc64/include/arch/trap/sun4u/interrupt.h (modified) (1 diff)
-
sparc64/include/arch/trap/trap.h (modified) (1 diff)
-
sparc64/src/drivers/pci.c (modified) (1 diff)
-
sparc64/src/mm/sun4u/tsb.c (modified) (1 diff)
-
sparc64/src/mm/sun4v/frame.c (modified) (1 diff)
-
sparc64/src/smc.c (modified) (2 diffs)
-
sparc64/src/smp/sun4u/ipi.c (modified) (1 diff)
-
sparc64/src/sun4v/md.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/src/cpu/cpu.c
rb2aaaa0 r09ab0a9a 39 39 #include <fpu_context.h> 40 40 41 42 41 void fpu_disable(void) 43 42 { -
kernel/arch/abs32le/src/smc.c
rb2aaaa0 r09ab0a9a 33 33 compiler_barrier(); 34 34 } 35 -
kernel/arch/amd64/include/arch/boot/memmap_struct.h
rb2aaaa0 r09ab0a9a 47 47 #endif 48 48 #endif 49 -
kernel/arch/amd64/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 65 65 #endif 66 66 #endif 67 -
kernel/arch/amd64/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 95 95 #endif 96 96 #endif 97 -
kernel/arch/amd64/include/arch/kseg_struct.h
rb2aaaa0 r09ab0a9a 47 47 #endif 48 48 #endif 49 -
kernel/arch/amd64/include/arch/mm/ptl.h
rb2aaaa0 r09ab0a9a 45 45 #define PTL_2MB_PAGE (1 << 7) 46 46 47 48 47 #endif 49 48 -
kernel/arch/amd64/include/arch/pm.h
rb2aaaa0 r09ab0a9a 43 43 #define IDT_ITEMS 64 44 44 #define GDT_ITEMS 8 45 46 45 47 46 #define NULL_DES 0 -
kernel/arch/amd64/src/cpu/cpu.c
rb2aaaa0 r09ab0a9a 65 65 "GenuineIntel" 66 66 }; 67 68 67 69 68 /** Setup flags on processor so that we can use the FPU -
kernel/arch/amd64/src/smc.c
rb2aaaa0 r09ab0a9a 33 33 compiler_barrier(); 34 34 } 35 -
kernel/arch/arm32/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 55 55 56 56 #endif 57 -
kernel/arch/arm32/include/arch/cp15.h
rb2aaaa0 r09ab0a9a 584 584 CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0); 585 585 586 587 586 /*c10 has tons of reserved too */ 588 587 CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */ -
kernel/arch/arm32/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 56 56 57 57 #endif 58 -
kernel/arch/arm32/include/arch/mach/beagleboardxm/beagleboardxm.h
rb2aaaa0 r09ab0a9a 46 46 /** @} 47 47 */ 48 -
kernel/arch/arm32/include/arch/mach/beaglebone/beaglebone.h
rb2aaaa0 r09ab0a9a 46 46 /** @} 47 47 */ 48 -
kernel/arch/arm32/include/arch/mach/integratorcp/integratorcp.h
rb2aaaa0 r09ab0a9a 97 97 } icp_hw_map_t; 98 98 99 100 99 extern void icp_init(void); 101 100 extern void icp_output_init(void); -
kernel/arch/arm32/include/arch/machine_func.h
rb2aaaa0 r09ab0a9a 68 68 extern void machine_init(void); 69 69 70 71 70 /** Starts timer. */ 72 71 extern void machine_timer_irq_start(void); 73 74 72 75 73 /** Halts CPU. */ … … 89 87 */ 90 88 extern void machine_irq_exception(unsigned int exc_no, istate_t *istate); 91 92 89 93 90 /* -
kernel/arch/arm32/include/arch/mm/page.h
rb2aaaa0 r09ab0a9a 131 131 set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) 132 132 133 134 133 #define pt_coherence(page) pt_coherence_m(page, 1) 135 134 -
kernel/arch/arm32/include/arch/mm/page_armv4.h
rb2aaaa0 r09ab0a9a 113 113 #define PTE_AP_USER_RW_KERNEL_RW 3 114 114 115 116 115 /* pte_level0_t and pte_level1_t descriptor_type flags */ 117 116 … … 195 194 } 196 195 } 197 198 196 199 197 /** Sets flags of level 1 page table entry. … … 247 245 } 248 246 249 250 247 NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) 251 248 { … … 255 252 } 256 253 257 258 254 extern void page_arch_init(void); 259 255 260 261 256 #endif /* __ASSEMBLER__ */ 262 257 -
kernel/arch/arm32/include/arch/mm/page_armv6.h
rb2aaaa0 r09ab0a9a 40 40 #error "Do not include arch specific page.h directly use generic page.h instead" 41 41 #endif 42 43 42 44 43 /* Macros for querying the last-level PTE entries. */ … … 112 111 #define PTE_AP1_RO 1 113 112 114 115 113 /* pte_level0_t and pte_level1_t descriptor_type flags */ 116 114 … … 126 124 /** pte_level1_t small page table flag with NX (used in descriptor type). */ 127 125 #define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 128 129 126 130 127 /** … … 230 227 pt_coherence(p); 231 228 } 232 233 229 234 230 /** Sets flags of level 1 page table entry. … … 319 315 } 320 316 321 322 317 extern void page_arch_init(void); 323 318 -
kernel/arch/arm32/include/arch/mm/page_fault.h
rb2aaaa0 r09ab0a9a 39 39 #include <stdint.h> 40 40 41 42 41 /** Decribes CP15 "fault status register" (FSR). 43 42 * … … 71 70 } fault_status_t; 72 71 73 74 72 /** Simplified description of instruction code. 75 73 * … … 88 86 } ATTRIBUTE_PACKED instruction_t; 89 87 90 91 88 /** Help union used for casting pc register (uint_32_t) value into 92 89 * #instruction_t pointer. -
kernel/arch/arm32/src/arm32.c
rb2aaaa0 r09ab0a9a 64 64 arch_ops_t *arch_ops = &arm32_ops; 65 65 66 67 66 /** Performs arm32-specific initialization before main_bsp() is called. */ 68 67 void arm32_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo) … … 118 117 } 119 118 120 121 119 /** Performs arm32 specific tasks needed before the new task is run. */ 122 120 void before_task_runs_arch(void) 123 121 { 124 122 } 125 126 123 127 124 /** Performs arm32 specific tasks needed before the new thread is scheduled. -
kernel/arch/arm32/src/cpu/cpu.c
rb2aaaa0 r09ab0a9a 60 60 static unsigned dcache_linesize_log(unsigned level); 61 61 62 63 62 /** Implementers (vendor) names */ 64 63 static const char *implementer(unsigned id) … … 99 98 return arch_data[0]; 100 99 } 101 102 100 103 101 /** Retrieves processor identification from CP15 register 0. … … 317 315 } 318 316 319 320 317 void cpu_dcache_flush(void) 321 318 { -
kernel/arch/arm32/src/fpu_context.c
rb2aaaa0 r09ab0a9a 47 47 #define FPSID_VARIANT(r) (((r) >> 4) 0xf) 48 48 #define FPSID_REVISION(r) (((r) >> 0) 0xf) 49 50 49 51 50 enum { … … 167 166 } 168 167 169 170 168 void fpu_init(void) 171 169 { -
kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
rb2aaaa0 r09ab0a9a 234 234 * @} 235 235 */ 236 -
kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
rb2aaaa0 r09ab0a9a 54 54 #include <log.h> 55 55 56 57 56 #define SDRAM_SIZE \ 58 57 sdram[(*(uint32_t *) (ICP_CMCR + ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2] … … 121 120 *((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq); 122 121 } 123 124 122 125 123 /** Unmasks interrupt. -
kernel/arch/arm32/src/machine_func.c
rb2aaaa0 r09ab0a9a 72 72 } 73 73 74 75 74 /** Starts timer. */ 76 75 void machine_timer_irq_start(void) … … 78 77 (machine_ops->machine_timer_irq_start)(); 79 78 } 80 81 79 82 80 /** Halts CPU. */ … … 105 103 (machine_ops->machine_irq_exception)(exc_no, istate); 106 104 } 107 108 105 109 106 /* -
kernel/arch/arm32/src/mm/page_fault.c
rb2aaaa0 r09ab0a9a 42 42 #include <interrupt.h> 43 43 #include <print.h> 44 45 44 46 45 /** -
kernel/arch/arm32/src/smc.c
rb2aaaa0 r09ab0a9a 67 67 isb(); 68 68 } 69 -
kernel/arch/ia32/include/arch/asm.h
rb2aaaa0 r09ab0a9a 348 348 349 349 #endif /* PROCESSOR_i486 */ 350 351 350 352 351 /** Return base address of current stack -
kernel/arch/ia32/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 58 58 #endif 59 59 #endif 60 -
kernel/arch/ia32/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 108 108 #endif 109 109 #endif 110 -
kernel/arch/ia32/include/arch/smp/apic.h
rb2aaaa0 r09ab0a9a 337 337 } __attribute__((packed)) io_redirection_reg_t; 338 338 339 340 339 /** IO APIC Identification Register. */ 341 340 typedef union { -
kernel/arch/ia32/src/cpu/cpu.c
rb2aaaa0 r09ab0a9a 56 56 #define INTEL_CPUID_ECX UINT32_C(0x6c65746e) 57 57 #define INTEL_CPUID_EDX UINT32_C(0x49656e69) 58 59 58 60 59 enum vendor { -
kernel/arch/ia32/src/smc.c
rb2aaaa0 r09ab0a9a 33 33 compiler_barrier(); 34 34 } 35 -
kernel/arch/ia64/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 141 141 #endif /* __ASSEMBLER__ */ 142 142 #endif 143 -
kernel/arch/ia64/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 156 156 #endif 157 157 #endif 158 -
kernel/arch/ia64/include/arch/proc/task.h
rb2aaaa0 r09ab0a9a 43 43 } task_arch_t; 44 44 45 46 45 #define task_create_arch(t) { (t)->arch.iomap = NULL; } 47 46 #define task_destroy_arch(t) -
kernel/arch/ia64/src/ia64.c
rb2aaaa0 r09ab0a9a 218 218 } 219 219 220 221 220 /** Enter userspace and never return. */ 222 221 void userspace(uspace_arg_t *kernel_uarg) -
kernel/arch/ia64/src/interrupt.c
rb2aaaa0 r09ab0a9a 195 195 } 196 196 197 198 197 #define BREAK_IMM_SYSCALL 0x40000U 199 198 -
kernel/arch/ia64/src/mm/tlb.c
rb2aaaa0 r09ab0a9a 102 102 tlb_invalidate_all(); 103 103 } 104 105 104 106 105 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt) … … 409 408 } 410 409 411 412 410 /** Copy content of PTE into data translation cache. 413 411 * … … 602 600 } 603 601 604 605 602 pte_t t; 606 603 bool found = page_mapping_find(as, va, true, &t); -
kernel/arch/ia64/src/mm/vhpt.c
rb2aaaa0 r09ab0a9a 53 53 } 54 54 55 56 55 void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) 57 56 { -
kernel/arch/ia64/src/smc.c
rb2aaaa0 r09ab0a9a 40 40 srlz_i(); 41 41 } 42 -
kernel/arch/ia64/src/smp/smp.c
rb2aaaa0 r09ab0a9a 54 54 /** @} 55 55 */ 56 -
kernel/arch/mips32/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 71 71 #endif 72 72 #endif 73 -
kernel/arch/mips32/include/arch/debugger.h
rb2aaaa0 r09ab0a9a 57 57 #define BKPOINT_FUNCCALL (1 << 3) 58 58 59 60 59 typedef struct { 61 60 uintptr_t address; /**< Breakpoint address */ -
kernel/arch/mips32/include/arch/fpu_context_struct.h
rb2aaaa0 r09ab0a9a 48 48 #endif 49 49 #endif 50 -
kernel/arch/mips32/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 128 128 #endif 129 129 #endif 130 -
kernel/arch/mips32/include/arch/mm/page.h
rb2aaaa0 r09ab0a9a 161 161 } pte_t; 162 162 163 164 163 NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) 165 164 { -
kernel/arch/mips32/include/arch/mm/tlb.h
rb2aaaa0 r09ab0a9a 140 140 } 141 141 142 143 142 /** Read Indexed TLB Entry 144 143 * -
kernel/arch/mips32/include/arch/proc/thread.h
rb2aaaa0 r09ab0a9a 47 47 /** @} 48 48 */ 49 -
kernel/arch/mips32/src/debug/stacktrace.c
rb2aaaa0 r09ab0a9a 242 242 } 243 243 244 245 244 bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx) 246 245 { -
kernel/arch/mips32/src/machine_func.c
rb2aaaa0 r09ab0a9a 66 66 } 67 67 68 69 68 /** Halts CPU. */ 70 69 void machine_cpu_halt(void) -
kernel/arch/mips32/src/mm/frame.c
rb2aaaa0 r09ab0a9a 95 95 return true; 96 96 } 97 98 97 99 98 /** Check whether frame is safe to write … … 169 168 } 170 169 171 172 170 /** Create memory zones 173 171 * -
kernel/arch/mips32/src/smc.c
rb2aaaa0 r09ab0a9a 34 34 compiler_barrier(); 35 35 } 36 -
kernel/arch/ppc32/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 89 89 #endif 90 90 #endif 91 -
kernel/arch/ppc32/include/arch/fpu_context_struct.h
rb2aaaa0 r09ab0a9a 107 107 #endif 108 108 #endif 109 -
kernel/arch/ppc32/include/arch/istate.h
rb2aaaa0 r09ab0a9a 76 76 } 77 77 78 79 78 #endif 80 79 -
kernel/arch/ppc32/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 131 131 #endif 132 132 #endif 133 -
kernel/arch/ppc32/src/smc.c
rb2aaaa0 r09ab0a9a 26 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 27 */ 28 29 28 30 29 #include <barrier.h> … … 60 59 asm volatile ("isync" ::: "memory"); 61 60 } 62 -
kernel/arch/riscv64/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 75 75 #endif 76 76 #endif 77 -
kernel/arch/riscv64/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 113 113 #endif 114 114 #endif 115 -
kernel/arch/riscv64/src/cpu/cpu.c
rb2aaaa0 r09ab0a9a 39 39 #include <fpu_context.h> 40 40 41 42 41 void fpu_disable(void) 43 42 { -
kernel/arch/riscv64/src/smc.c
rb2aaaa0 r09ab0a9a 34 34 compiler_barrier(); 35 35 } 36 -
kernel/arch/sparc64/include/arch/context_struct.h
rb2aaaa0 r09ab0a9a 81 81 #endif 82 82 #endif 83 -
kernel/arch/sparc64/include/arch/cpu.h
rb2aaaa0 r09ab0a9a 64 64 #endif 65 65 66 67 66 #endif 68 67 -
kernel/arch/sparc64/include/arch/cpu_family.h
rb2aaaa0 r09ab0a9a 81 81 /** @} 82 82 */ 83 -
kernel/arch/sparc64/include/arch/cpu_node.h
rb2aaaa0 r09ab0a9a 38 38 #include <genarch/ofw/ofw_tree.h> 39 39 40 41 40 /** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp"). 42 41 * … … 57 56 /** @} 58 57 */ 59 -
kernel/arch/sparc64/include/arch/istate_struct.h
rb2aaaa0 r09ab0a9a 137 137 #endif 138 138 #endif 139 -
kernel/arch/sparc64/include/arch/mm/km.h
rb2aaaa0 r09ab0a9a 42 42 #endif 43 43 44 45 44 #endif 46 45 -
kernel/arch/sparc64/include/arch/mm/mmu.h
rb2aaaa0 r09ab0a9a 42 42 #endif 43 43 44 45 44 #endif 46 45 -
kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h
rb2aaaa0 r09ab0a9a 59 59 #define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ 60 60 #endif 61 62 61 63 62 /* D-MMU ASIs. */ -
kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
rb2aaaa0 r09ab0a9a 187 187 typedef union tlb_tag_read_reg tlb_tag_read_reg_t; 188 188 typedef union tlb_tag_read_reg tlb_tag_access_reg_t; 189 190 189 191 190 /** TLB Demap Operation Address. */ … … 412 411 #elif defined (US3) 413 412 414 415 413 /** Read IMMU TLB Data Access Register. 416 414 * … … 520 518 #endif 521 519 522 523 520 /** Write IMMU TLB Tag Access Register. 524 521 * … … 558 555 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); 559 556 } 560 561 557 562 558 /** Write IMMU TLB Data in Register. -
kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h
rb2aaaa0 r09ab0a9a 67 67 } __attribute__((packed)) tsb_descr_t; 68 68 69 70 69 /* Forward declarations. */ 71 70 struct as; -
kernel/arch/sparc64/include/arch/sun4v/hypercall.h
rb2aaaa0 r09ab0a9a 73 73 #define CONS_PUTCHAR 0x61 74 74 75 76 75 /* return codes */ 77 76 #define HV_EOK 0 /**< Successful return */ … … 94 93 #define HV_EBUSY 17 /**< Operation failed as resource is otherwise busy */ 95 94 96 97 95 /** 98 96 * Performs a hyperfast hypervisor API call from the assembly language code. … … 115 113 #define __HYPERCALL_HYPERFAST(sw_trap_number) \ 116 114 ta (sw_trap_number); 117 118 115 119 116 #ifndef __ASSEMBLER__ -
kernel/arch/sparc64/include/arch/trap/interrupt.h
rb2aaaa0 r09ab0a9a 71 71 #endif /* !def __ASSEMBLER__ */ 72 72 73 74 73 #if defined (SUN4U) 75 74 #include <arch/trap/sun4u/interrupt.h> -
kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h
rb2aaaa0 r09ab0a9a 40 40 #include <arch/trap/trap_table.h> 41 41 #include <arch/stack.h> 42 43 42 44 43 /* Interrupt ASI registers. */ -
kernel/arch/sparc64/include/arch/trap/trap.h
rb2aaaa0 r09ab0a9a 42 42 /** @} 43 43 */ 44 -
kernel/arch/sparc64/src/drivers/pci.c
rb2aaaa0 r09ab0a9a 114 114 return pci; 115 115 } 116 117 116 118 117 /** Initialize the Psycho PCI controller. -
kernel/arch/sparc64/src/mm/sun4u/tsb.c
rb2aaaa0 r09ab0a9a 167 167 /** @} 168 168 */ 169 -
kernel/arch/sparc64/src/mm/sun4v/frame.c
rb2aaaa0 r09ab0a9a 86 86 } 87 87 88 89 88 void frame_low_arch_init(void) 90 89 { -
kernel/arch/sparc64/src/smc.c
rb2aaaa0 r09ab0a9a 49 49 #elif defined (US3) 50 50 51 52 51 void smc_coherence(void *a, size_t l) 53 52 { … … 58 57 59 58 #endif /* defined(US3) */ 60 -
kernel/arch/sparc64/src/smp/sun4u/ipi.c
rb2aaaa0 r09ab0a9a 175 175 } 176 176 177 178 177 /* 179 178 * Deliver an IPI to the specified processors (except the current one). -
kernel/arch/sparc64/src/sun4v/md.c
rb2aaaa0 r09ab0a9a 54 54 #define PROP_STR 0x73 /**< Node property with a string value */ 55 55 #define PROP_DATA 0x64 /**< Node property with a block of data */ 56 57 56 58 57 /** machine description header */ … … 105 104 __attribute__((aligned(16))); 106 105 107 108 106 /** returns pointer to the element at the given index */ 109 107 static md_element_t *get_element(element_idx_t idx)
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