Changeset 03c971f in mainline for kernel/arch


Ignore:
Timestamp:
2013-08-15T14:20:16Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bb2a5b2
Parents:
f2c19b0 (diff), 2921602 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Mainline changes.

Location:
kernel/arch
Files:
16 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/abs32le/Makefile.inc

    rf2c19b0 r03c971f  
    3939endif
    4040
    41 ifeq ($(COMPILER),clang)
    42         CLANG_ARCH = i386
    43 endif
    44 
    4541BITS = 32
    4642ENDIANESS = LE

  • kernel/arch/amd64/Makefile.inc

    rf2c19b0 r03c971f  
    3030BFD_ARCH = i386:x86-64
    3131BFD = binary
    32 CLANG_ARCH = x86_64
    3332
    3433FPU_NO_CFLAGS = -mno-sse -mno-sse2
    … …  
    3635GCC_CFLAGS += $(CMN1)
    3736ICC_CFLAGS += $(CMN1)
     37CLANG_CFLAGS += $(CMN1)
    3838
    3939BITS = 64

  • kernel/arch/arm32/include/arch/asm.h

    rf2c19b0 r03c971f  
    3838
    3939#include <typedefs.h>
     40#include <arch/cp15.h>
    4041#include <arch/stack.h>
    4142#include <config.h>
    … …  
    5152 * chapter 2.3.8 p.2-22 (52 in the PDF)
    5253 *
    53  * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
    54  * reference manual for armv4/5 CP15 implementation is mandatory only for
    55  * armv6+.
     54 * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM
     55 * Architecture reference manual for armv4/5, CP15 implementation is mandatory
     56 * only for armv6+.
    5657 */
    5758NO_TRACE static inline void cpu_sleep(void)
    … …  
    6061        asm volatile ( "wfe" );
    6162#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
    62         asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
     63        WFI_write(0);
    6364#endif
    6465}

  • kernel/arch/arm32/include/arch/cp15.h

    rf2c19b0 r03c971f  
    171171        CCSIDR_LINESIZE_MASK = 0x7,
    172172        CCSIDR_LINESIZE_SHIFT = 0,
     173#define CCSIDR_SETS(val) \
     174        (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
     175#define CCSIDR_WAYS(val) \
     176        (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
     177/* The register value is log(linesize_in_words) - 2 */
     178#define CCSIDR_LINESIZE_LOG(val) \
     179        (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
    173180};
    174181CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
    … …  
    187194        CLIDR_UNI_CACHE = 0x4,
    188195        CLIDR_CACHE_MASK = 0x7,
    189 #define CLIDR_CACHE(level, val)   ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK)
     196/** levels counted from 0 */
     197#define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
    190198};
    191199CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
    … …  
    293301
    294302/* Memory protection and control registers */
     303enum {
     304        TTBR_ADDR_MASK = 0xffffff80,
     305        TTBR_NOS_FLAG = 1 << 5,
     306        TTBR_RGN_MASK = 0x3 << 3,
     307        TTBR_RGN_NO_CACHE = 0x0 << 3,
     308        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
     309        TTBR_RGN_WT_CACHE = 0x2 << 3,
     310        TTBR_RGN_WB_CACHE = 0x3 << 3,
     311        TTBR_S_FLAG = 1 << 1,
     312        TTBR_C_FLAG = 1 << 0,
     313};
    295314CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
    296315CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
    … …  
    363382
    364383CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
    365 CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2);
     384CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
    366385
    367386CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
    … …  
    369388CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
    370389CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
    371 CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4);
    372 CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5);
    373 CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6);
    374 CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7);
     390CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
     391CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
     392CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
     393CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
    375394
    376395

  • kernel/arch/arm32/include/arch/mm/page.h

    rf2c19b0 r03c971f  
    4141#include <arch/exception.h>
    4242#include <arch/barrier.h>
     43#include <arch/cp15.h>
    4344#include <trace.h>
    4445
    … …  
    9596/* Set PTE address accessors for each level. */
    9697#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    97         (set_ptl0_addr((pte_t *) (ptl0)))
     98        set_ptl0_addr((pte_t *) (ptl0))
    9899#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    99         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
     100        set_ptl1_addr((pte_t*) (ptl0), i, a)
    100101#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    101102#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    102103#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    103         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
     104        set_ptl3_addr((pte_t*) (ptl3), i, a)
    104105
    105106/* Get PTE flags accessors for each level. */
    … …  
    129130        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    130131
     132
     133#define pt_coherence(page) pt_coherence_m(page, 1)
     134
    131135#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
    132136#include "page_armv6.h"
    … …  
    137141#endif
    138142
     143/** Sets the address of level 0 page table.
     144 *
     145 * @param pt Pointer to the page table to set.
     146 *
     147 * Page tables are always in cacheable memory.
     148 * Make sure the memory type is correct, and in sync with:
     149 * init_boot_pt (boot/arch/arm32/src/mm.c)
     150 * init_ptl0_section (boot/arch/arm32/src/mm.c)
     151 * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     152 */
     153NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
     154{
     155        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
     156        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
     157        TTBR0_write(val);
     158}
     159
     160NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
     161{
     162        pt[i].l0.coarse_table_addr = address >> 10;
     163        pt_coherence(&pt[i].l0);
     164}
     165
     166NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
     167{
     168        pt[i].l1.frame_base_addr = address >> 12;
     169        pt_coherence(&pt[i].l1);
     170}
     171
    139172#endif
    140173

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    rf2c19b0 r03c971f  
    120120#define PTE_DESCRIPTOR_SMALL_PAGE       2
    121121
    122 
    123 /** Sets the address of level 0 page table.
    124  *
    125  * @param pt Pointer to the page table to set.
    126  *
    127  */
    128 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    129 {
    130         asm volatile (
    131                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    132                 :: [pt] "r" (pt)
    133         );
    134 }
    135 
     122#define pt_coherence_m(pt, count) \
     123do { \
     124        for (unsigned i = 0; i < count; ++i) \
     125                DCCMVAU_write((uintptr_t)(pt + i)); \
     126        read_barrier(); \
     127} while (0)
    136128
    137129/** Returns level 0 page table entry flags.
    … …  
    223215       
    224216        /* default access permission */
    225         p->access_permission_0 = p->access_permission_1 = 
     217        p->access_permission_0 = p->access_permission_1 =
    226218            p->access_permission_2 = p->access_permission_3 =
    227219            PTE_AP_USER_NO_KERNEL_RW;
    … …  
    229221        if (flags & PAGE_USER)  {
    230222                if (flags & PAGE_READ) {
    231                         p->access_permission_0 = p->access_permission_1 = 
    232                             p->access_permission_2 = p->access_permission_3 = 
     223                        p->access_permission_0 = p->access_permission_1 =
     224                            p->access_permission_2 = p->access_permission_3 =
    233225                            PTE_AP_USER_RO_KERNEL_RW;
    234226                }
    235227                if (flags & PAGE_WRITE) {
    236                         p->access_permission_0 = p->access_permission_1 = 
    237                             p->access_permission_2 = p->access_permission_3 = 
    238                             PTE_AP_USER_RW_KERNEL_RW; 
     228                        p->access_permission_0 = p->access_permission_1 =
     229                            p->access_permission_2 = p->access_permission_3 =
     230                            PTE_AP_USER_RW_KERNEL_RW;
    239231                }
    240232        }

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    rf2c19b0 r03c971f  
    4040#error "Do not include arch specific page.h directly use generic page.h instead"
    4141#endif
     42
    4243
    4344/* Macros for querying the last-level PTE entries. */
    … …  
    125126#define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
    126127
    127 /** Sets the address of level 0 page table.
    128  *
    129  * @param pt Pointer to the page table to set.
    130  *
    131  */
    132 NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    133 {
    134         asm volatile (
    135                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    136                 :: [pt] "r" (pt)
    137         );
    138 }
     128
     129/**
     130 * For an ARMv7 implementation that does not include the Large Physical Address Extension,
     131 * and in implementations of architecture versions before ARMv7, if the translation tables
     132 * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of
     133 * unification after writing to the translation tables and before the DSB instruction. This
     134 * ensures that the updated translation table are visible to a hardware translation table walk.
     135 *
     136 * Therefore, an example instruction sequence for writing a translation table entry,
     137 * covering changes to the instruction
     138 * or data mappings in a uniprocessor system is:
     139 * STR rx, [Translation table entry]
     140 * ; write new entry to the translation table
     141 * Clean cache line [Translation table entry] : This operation is not required with the
     142 * ; Multiprocessing Extensions.
     143 * DSB
     144 * ; ensures visibility of the data cleaned from the D Cache
     145 * Invalidate TLB entry by MVA (and ASID if non-global) [page address]
     146 * Invalidate BTC
     147 * DSB
     148 * ; ensure completion of the Invalidate TLB operation
     149 * ISB
     150 * ; ensure table changes visible to instruction fetch
     151 *
     152 * ARM Architecture reference chp. B3.10.1 p. B3-1375
     153 * @note: see TTRB0/1 for pt memory type
     154 */
     155#define pt_coherence_m(pt, count) \
     156do { \
     157        for (unsigned i = 0; i < count; ++i) \
     158                DCCMVAU_write((uintptr_t)(pt + i)); \
     159        read_barrier(); \
     160} while (0)
    139161
    140162
    … …  
    206228                p->ns = 0;
    207229        }
     230        pt_coherence(p);
    208231}
    209232
    … …  
    232255                        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX;
    233256        }
    234        
    235         /* tex=0 buf=1 and cache=1 => normal memory
    236          * tex=0 buf=1 and cache=0 => shareable device mmio
    237          */
    238         p->cacheable = (flags & PAGE_CACHEABLE);
    239         p->bufferable = 1;
    240         p->tex = 0;
     257
     258        if (flags & PAGE_CACHEABLE) {
     259                /*
     260                 * Write-through, no write-allocate memory, see ch. B3.8.2
     261                 * (p. B3-1358) of ARM Architecture reference manual.
     262                 * Make sure the memory type is correct, and in sync with:
     263                 * init_boot_pt (boot/arch/arm32/src/mm.c)
     264                 * init_ptl0_section (boot/arch/arm32/src/mm.c)
     265                 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     266                 */
     267                p->tex = 5;
     268                p->cacheable = 0;
     269                p->bufferable = 1;
     270        } else {
     271                /*
     272                 * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of
     273                 * ARM Architecture reference manual.
     274                 */
     275                p->tex = 0;
     276                p->cacheable = 0;
     277                p->bufferable = 1;
     278        }
    241279       
    242280        /* Shareable is ignored for devices (non-cacheable),
    243          * turn it on for normal memory. */
    244         p->shareable = 1;
     281         * turn it off for normal memory. */
     282        p->shareable = 0;
    245283       
    246284        p->non_global = !(flags & PAGE_GLOBAL);
    … …  
    256294                        p->access_permission_1 = PTE_AP1_RO;
    257295        }
     296        pt_coherence(p);
    258297}
    259298
    … …  
    264303        p->should_be_zero_0 = 0;
    265304        p->should_be_zero_1 = 0;
    266         write_barrier();
    267305        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
     306        pt_coherence(p);
    268307}
    269308
    … …  
    273312
    274313        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
     314        pt_coherence(p);
    275315}
    276316

  • kernel/arch/arm32/src/cpu/cpu.c

    rf2c19b0 r03c971f  
    157157#endif
    158158#ifdef PROCESSOR_ARCH_armv7_a
    159          /* ICache coherency is elaborate on in barrier.h.
     159         /* ICache coherency is elaborated on in barrier.h.
    160160          * VIPT and PIPT caches need maintenance only on code modify,
    161161          * so it should be safe for general use.
    … …  
    166166                control_reg |=
    167167                    SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
     168        } else {
     169                control_reg &=
     170                    ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
    168171        }
    169172#endif
    … …  
    204207#ifdef PROCESSOR_ARCH_armv7_a
    205208        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    206         const unsigned ls_log = 2 +
    207             ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
    208         return ls_log + 2; //return log2(bytes)
     209        const uint32_t ccsidr = CCSIDR_read();
     210        return CCSIDR_LINESIZE_LOG(ccsidr);
    209211#endif
    210212        return 0;
    … …  
    217219#ifdef PROCESSOR_ARCH_armv7_a
    218220        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    219         const unsigned ways = 1 +
    220             ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
    221         return ways;
     221        const uint32_t ccsidr = CCSIDR_read();
     222        return CCSIDR_WAYS(ccsidr);
    222223#endif
    223224        return 0;
    … …  
    229230#ifdef PROCESSOR_ARCH_armv7_a
    230231        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    231         const unsigned sets = 1 +
    232             ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
    233         return sets;
     232        const uint32_t ccsidr = CCSIDR_read();
     233        return CCSIDR_SETS(ccsidr);
    234234#endif
    235235        return 0;
    … …  
    241241#ifdef PROCESSOR_ARCH_armv7_a
    242242        const uint32_t val = CLIDR_read();
    243         for (unsigned i = 1; i <= 7; ++i) {
     243        for (unsigned i = 0; i < 8; ++i) {
    244244                const unsigned ctype = CLIDR_CACHE(i, val);
    245245                switch (ctype) {
    … …  
    280280                const unsigned ways = dcache_ways(i);
    281281                const unsigned sets = dcache_sets(i);
    282                 const unsigned way_shift =  31 - log2(ways);
     282                const unsigned way_shift = 32 - log2(ways);
    283283                const unsigned set_shift = dcache_linesize_log(i);
    284284                dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
    … …  
    293293                const unsigned ways = dcache_ways(i);
    294294                const unsigned sets = dcache_sets(i);
    295                 const unsigned way_shift =  31 - log2(ways);
     295                const unsigned way_shift = 32 - log2(ways);
    296296                const unsigned set_shift = dcache_linesize_log(i);
    297297                dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    rf2c19b0 r03c971f  
    8585static void bb_timer_irq_handler(irq_t *irq)
    8686{
     87        amdm37x_gpt_irq_ack(&beagleboard.timer);
     88
    8789        /*
    8890         * We are holding a lock which prevents preemption.
    8991         * Release the lock, call clock() and reacquire the lock again.
    9092         */
    91         amdm37x_gpt_irq_ack(&beagleboard.timer);
    9293        spinlock_unlock(&irq->lock);
    9394        clock();
    … …  
    147148{
    148149        const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
    149         amdm37x_irc_irq_ack(beagleboard.irc_addr);
    150150
    151151        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    159159                    CPU->id, inum);
    160160        }
     161        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
     162         * of ISR. DO this to avoid strange behavior. */
     163        amdm37x_irc_irq_ack(beagleboard.irc_addr);
    161164}
    162165

  • kernel/arch/arm32/src/mach/beaglebone/beaglebone.c

    rf2c19b0 r03c971f  
    177177{
    178178        const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
    179         am335x_irc_irq_ack(bbone.irc_addr);
    180179
    181180        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    187186                printf("Spurious interrupt\n");
    188187        }
     188
     189        am335x_irc_irq_ack(bbone.irc_addr);
    189190}
    190191

  • kernel/arch/arm32/src/mm/tlb.c

    rf2c19b0 r03c971f  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
     39#include <arch/cp15.h>
    3940#include <typedefs.h>
    4041#include <arch/mm/page.h>
     42#include <arch/cache.h>
    4143
    4244/** Invalidate all entries in TLB.
    … …  
    4648void tlb_invalidate_all(void)
    4749{
    48         asm volatile (
    49                 "eor r1, r1\n"
    50                 "mcr p15, 0, r1, c8, c7, 0\n"
    51                 ::: "r1"
    52         );
     50        TLBIALL_write(0);
     51        /*
     52         * "A TLB maintenance operation is only guaranteed to be complete after
     53         * the execution of a DSB instruction."
     54         * "An ISB instruction, or a return from an exception, causes the
     55         * effect of all completed TLB maintenance operations that appear in
     56         * program order before the ISB or return from exception to be visible
     57         * to all subsequent instructions, including the instruction fetches
     58         * for those instructions."
     59         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     60         */
     61        read_barrier();
     62        inst_barrier();
    5363}
    5464
    … …  
    6070{
    6171        tlb_invalidate_all();
     72        // TODO: why not TLBIASID_write(asid) ?
    6273}
    6374
    … …  
    6576 *
    6677 * @param page Virtual adress of the page
    67  */ 
     78 */
    6879static inline void invalidate_page(uintptr_t page)
    6980{
    70         asm volatile (
    71                 "mcr p15, 0, %[page], c8, c7, 1\n"
    72                 :: [page] "r" (page)
    73         );
     81        //TODO: What about TLBIMVAA?
     82        TLBIMVA_write(page);
     83        /*
     84         * "A TLB maintenance operation is only guaranteed to be complete after
     85         * the execution of a DSB instruction."
     86         * "An ISB instruction, or a return from an exception, causes the
     87         * effect of all completed TLB maintenance operations that appear in
     88         * program order before the ISB or return from exception to be visible
     89         * to all subsequent instructions, including the instruction fetches
     90         * for those instructions."
     91         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     92         */
     93        read_barrier();
     94        inst_barrier();
    7495}
    7596
    … …  
    83104void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
    84105{
    85         unsigned int i;
    86 
    87         for (i = 0; i < cnt; i++)
     106        for (unsigned i = 0; i < cnt; i++)
    88107                invalidate_page(page + i * PAGE_SIZE);
    89108}

  • kernel/arch/ia32/Makefile.inc

    rf2c19b0 r03c971f  
    3030BFD_ARCH = i386
    3131BFD = binary
    32 CLANG_ARCH = i386
    3332
    3433BITS = 32

  • kernel/arch/ia32/include/arch/cpu.h

    rf2c19b0 r03c971f  
    4141#define EFLAGS_RF       (1 << 16)
    4242
    43 #define CR4_OSFXSR_MASK (1<<9)
     43#define CR4_OSFXSR_MASK      (1 << 9)
     44#define CR4_OSXMMEXCPT_MASK  (1 << 10)
    4445
    4546/* Support for SYSENTER and SYSEXIT */
    … …  
    5960        unsigned int model;
    6061        unsigned int stepping;
    61         cpuid_feature_info fi;
    62 
     62        cpuid_feature_info_t fi;
     63       
    6364        tss_t *tss;
    6465       

  • kernel/arch/ia32/include/arch/cpuid.h

    rf2c19b0 r03c971f  
    5050        uint32_t cpuid_ecx;
    5151        uint32_t cpuid_edx;
    52 } __attribute__ ((packed)) cpu_info_t;
     52} __attribute__((packed)) cpu_info_t;
    5353
    54 struct __cpuid_extended_feature_info {
    55         unsigned sse3 : 1;
    56         unsigned     : 31;
    57 } __attribute__ ((packed));
     54struct cpuid_extended_feature_info {
     55        unsigned int sse3 : 1;
     56        unsigned int : 31;
     57} __attribute__((packed));
    5858
    59 typedef union cpuid_extended_feature_info {
    60         struct __cpuid_extended_feature_info bits;
     59typedef union {
     60        struct cpuid_extended_feature_info bits;
    6161        uint32_t word;
    62 } cpuid_extended_feature_info;
     62} cpuid_extended_feature_info_t;
    6363
    64 struct __cpuid_feature_info {
    65         unsigned     : 11;
    66         unsigned sep  : 1;
    67         unsigned     : 11;
    68         unsigned mmx  : 1;
    69         unsigned fxsr : 1;
    70         unsigned sse  : 1;
    71         unsigned sse2 : 1;
    72         unsigned      : 5;
    73 } __attribute__ ((packed));
     64struct cpuid_feature_info {
     65        unsigned int : 11;
     66        unsigned int sep  : 1;
     67        unsigned int : 11;
     68        unsigned int mmx  : 1;
     69        unsigned int fxsr : 1;
     70        unsigned int sse  : 1;
     71        unsigned int sse2 : 1;
     72        unsigned int : 5;
     73} __attribute__((packed));
    7474
    75 typedef union cpuid_feature_info {
    76         struct __cpuid_feature_info bits;
     75typedef union {
     76        struct cpuid_feature_info bits;
    7777        uint32_t word;
    78 } cpuid_feature_info;
    79 
     78} cpuid_feature_info_t;
    8079
    8180static inline uint32_t has_cpuid(void)
    8281{
    83         uint32_t val, ret;
     82        uint32_t val;
     83        uint32_t ret;
    8484       
    8585        asm volatile (

  • kernel/arch/ia32/src/cpu/cpu.c

    rf2c19b0 r03c971f  
    115115                        "mov %[help], %%cr4\n"
    116116                        : [help] "+r" (help)
    117                         : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
     117                        : [mask] "i" (CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK)
    118118                );
    119119        }
    120 
     120       
    121121#ifndef PROCESSOR_i486
    122122        if (CPU->arch.fi.bits.sep) {

  • kernel/arch/ia32/src/fpu_context.c

    rf2c19b0 r03c971f  
    2727 */
    2828
    29 /** @addtogroup ia32   
     29/** @addtogroup ia32
    3030 * @{
    3131 */
    … …  
    3737#include <arch.h>
    3838#include <cpu.h>
    39 
    4039
    4140/** x87 FPU scr values (P3+ MMX2) */
    … …  
    6059        X87_DENORMAL_EXC_FLAG = (1 << 1),
    6160        X87_INVALID_OP_EXC_FLAG = (1 << 0),
    62 
     61       
    6362        X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK,
    6463};
    6564
    66 
    6765typedef void (*fpu_context_function)(fpu_context_t *fctx);
    6866
    69 static fpu_context_function fpu_save, fpu_restore;
     67static fpu_context_function fpu_save;
     68static fpu_context_function fpu_restore;
    7069
    7170static void fpu_context_f_save(fpu_context_t *fctx)
    … …  
    104103void fpu_fxsr(void)
    105104{
    106         fpu_save=fpu_context_fx_save;
    107         fpu_restore=fpu_context_fx_restore;
     105        fpu_save = fpu_context_fx_save;
     106        fpu_restore = fpu_context_fx_restore;
    108107}
    109108
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