| 1 | /*
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| 2 | * Copyright (c) 2013 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup arm32
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief System Control Coprocessor (CP15)
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| 34 | */
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| 35 |
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| 36 | #ifndef KERN_arm32_CP15_H_
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| 37 | #define KERN_arm32_CP15_H_
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| 38 |
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| 39 |
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| 40 | /** See ARM Architecture reference manual ch. B3.17.1 page B3-1456
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| 41 | * for the list */
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| 42 |
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| 43 | #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
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| 44 | static inline uint32_t name##_read() \
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| 45 | { \
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| 46 | uint32_t val; \
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| 47 | asm volatile ( "mrc p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" : "=r" (val) ); \
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| 48 | return val; \
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| 49 | }
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| 50 | #define CONTROL_REG_GEN_WRITE(name, crn, opc1, crm, opc2) \
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| 51 | static inline void name##_write(uint32_t val) \
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| 52 | { \
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| 53 | asm volatile ( "mcr p15, "#opc1", %0, "#crn", "#crm", "#opc2"\n" :: "r" (val) ); \
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| 54 | }
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| 55 |
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| 56 | /* Identification registers */
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| 57 | enum {
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| 58 | MIDR_IMPLEMENTER_MASK = 0xff,
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| 59 | MIDR_IMPLEMENTER_SHIFT = 24,
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| 60 | MIDR_VARIANT_MASK = 0xf,
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| 61 | MIDR_VARIANT_SHIFT = 20,
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| 62 | MIDR_ARCHITECTURE_MASK = 0xf,
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| 63 | MIDR_ARCHITECTURE_SHIFT = 16,
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| 64 | MIDR_PART_NUMBER_MASK = 0xfff,
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| 65 | MIDR_PART_NUMBER_SHIFT = 4,
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| 66 | MIDR_REVISION_MASK = 0xf,
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| 67 | MIDR_REVISION_SHIFT = 0,
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| 68 | };
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| 69 | CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
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| 70 |
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| 71 | enum {
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| 72 | CTR_FORMAT_MASK = 0xe0000000,
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| 73 | CTR_FORMAT_ARMv7 = 0x80000000,
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| 74 | CTR_FORMAT_ARMv6 = 0x00000000,
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| 75 | /* ARMv7 format */
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| 76 | CTR_CWG_MASK = 0xf,
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| 77 | CTR_CWG_SHIFT = 24,
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| 78 | CTR_ERG_MASK = 0xf,
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| 79 | CTR_ERG_SHIFT = 20,
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| 80 | CTR_D_MIN_LINE_MASK = 0xf,
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| 81 | CTR_D_MIN_LINE_SHIFT = 16,
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| 82 | CTR_I_MIN_LINE_MASK = 0xf,
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| 83 | CTR_I_MIN_LINE_SHIFT = 0,
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| 84 | CTR_L1I_POLICY_MASK = 0x0000c000,
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| 85 | CTR_L1I_POLICY_AIVIVT = 0x00004000,
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| 86 | CTR_L1I_POLICY_VIPT = 0x00008000,
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| 87 | CTR_L1I_POLICY_PIPT = 0x0000c000,
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| 88 | /* ARMv6 format */
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| 89 | CTR_CTYPE_MASK = 0x1e000000,
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| 90 | CTR_CTYPE_WT = 0x00000000,
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| 91 | CTR_CTYPE_WB_NL = 0x04000000,
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| 92 | CTR_CTYPE_WB_D = 0x0a000000,
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| 93 | CTR_CTYPE_WB_A = 0x0c000000, /**< ARMv5- only */
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| 94 | CTR_CTYPE_WB_B = 0x0e000000, /**< ARMv5- only */
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| 95 | CTR_CTYPE_WB_C = 0x1c000000,
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| 96 | CTR_SEP_FLAG = 1 << 24,
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| 97 | CTR_DCACHE_P_FLAG = 1 << 23,
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| 98 | CTR_DCACHE_SIZE_MASK = 0xf,
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| 99 | CTR_DCACHE_SIZE_SHIFT = 18,
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| 100 | CTR_DCACHE_ASSOC_MASK = 0x7,
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| 101 | CTR_DCACHE_ASSOC_SHIFT = 15,
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| 102 | CTR_DCACHE_M_FLAG = 1 << 14,
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| 103 | CTR_DCACHE_LEN_MASK = 0x3,
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| 104 | CTR_DCACHE_LEN_SHIFT = 0,
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| 105 | CTR_ICACHE_P_FLAG = 1 << 11,
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| 106 | CTR_ICACHE_SIZE_MASK = 0xf,
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| 107 | CTR_ICACHE_SIZE_SHIFT = 6,
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| 108 | CTR_ICACHE_ASSOC_MASK = 0x7,
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| 109 | CTR_ICACHE_ASSOC_SHIFT = 3,
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| 110 | CTR_ICACHE_M_FLAG = 1 << 2,
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| 111 | CTR_ICACHE_LEN_MASK = 0x3,
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| 112 | CTR_ICACHE_LEN_SHIFT = 0,
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| 113 | };
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| 114 | CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
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| 115 | CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
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| 116 | CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3);
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| 117 | CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5);
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| 118 | CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
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| 119 |
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| 120 | enum {
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| 121 | ID_PFR0_THUMBEE_MASK = 0xf << 12,
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| 122 | ID_PFR0_THUMBEE = 0x1 << 12,
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| 123 | ID_PFR0_JAZELLE_MASK = 0xf << 8,
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| 124 | ID_PFR0_JAZELLE = 0x1 << 8,
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| 125 | ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8,
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| 126 | ID_PFR0_THUMB_MASK = 0xf << 4,
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| 127 | ID_PFR0_THUMB = 0x1 << 4,
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| 128 | ID_PFR0_THUMB2 = 0x3 << 4,
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| 129 | ID_PFR0_ARM_MASK = 0xf << 0,
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| 130 | ID_PFR0_ARM = 0x1 << 0,
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| 131 | };
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| 132 | CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0);
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| 133 |
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| 134 | enum {
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| 135 | ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16,
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| 136 | ID_PFR1_GEN_TIMER_EXT = 0x1 << 16,
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| 137 | ID_PFR1_VIRT_EXT_MASK = 0xf << 12,
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| 138 | ID_PFR1_VIRT_EXT = 0x1 << 12,
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| 139 | ID_PFR1_M_PROF_MASK = 0xf << 8,
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| 140 | ID_PFR1_M_PROF_MODEL = 0x2 << 8,
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| 141 | ID_PFR1_SEC_EXT_MASK = 0xf << 4,
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| 142 | ID_PFR1_SEC_EXT = 0x1 << 4,
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| 143 | ID_PFR1_SEC_EXT_RFR = 0x2 << 4,
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| 144 | ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0,
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| 145 | ID_PFR1_ARMV4_MODEL = 0x1 << 0,
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| 146 | };
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| 147 | CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1);
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| 148 | CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2);
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| 149 | CONTROL_REG_GEN_READ(ID_AFR0, c0, 0, c1, 3);
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| 150 | CONTROL_REG_GEN_READ(ID_MMFR0, c0, 0, c1, 4);
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| 151 | CONTROL_REG_GEN_READ(ID_MMFR1, c0, 0, c1, 5);
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| 152 | CONTROL_REG_GEN_READ(ID_MMFR2, c0, 0, c1, 6);
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| 153 | CONTROL_REG_GEN_READ(ID_MMFR3, c0, 0, c1, 7);
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| 154 |
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| 155 | CONTROL_REG_GEN_READ(ID_ISAR0, c0, 0, c2, 0);
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| 156 | CONTROL_REG_GEN_READ(ID_ISAR1, c0, 0, c2, 1);
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| 157 | CONTROL_REG_GEN_READ(ID_ISAR2, c0, 0, c2, 2);
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| 158 | CONTROL_REG_GEN_READ(ID_ISAR3, c0, 0, c2, 3);
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| 159 | CONTROL_REG_GEN_READ(ID_ISAR4, c0, 0, c2, 4);
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| 160 | CONTROL_REG_GEN_READ(ID_ISAR5, c0, 0, c2, 5);
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| 161 |
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| 162 | enum {
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| 163 | CCSIDR_WT_FLAG = 1 << 31,
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| 164 | CCSIDR_WB_FLAG = 1 << 30,
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| 165 | CCSIDR_RA_FLAG = 1 << 29,
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| 166 | CCSIDR_WA_FLAG = 1 << 28,
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| 167 | CCSIDR_NUMSETS_MASK = 0x7fff,
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| 168 | CCSIDR_NUMSETS_SHIFT = 13,
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| 169 | CCSIDR_ASSOC_MASK = 0x3ff,
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| 170 | CCSIDR_ASSOC_SHIFT = 3,
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| 171 | CCSIDR_LINESIZE_MASK = 0x7,
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| 172 | CCSIDR_LINESIZE_SHIFT = 0,
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| 173 | #define CCSIDR_SETS(val) \
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| 174 | (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
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| 175 | #define CCSIDR_WAYS(val) \
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| 176 | (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1)
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| 177 | /* The register value is log(linesize_in_words) - 2 */
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| 178 | #define CCSIDR_LINESIZE_LOG(val) \
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| 179 | (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
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| 180 | };
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| 181 | CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
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| 182 |
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| 183 | enum {
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| 184 | CLIDR_LOUU_MASK = 0x7,
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| 185 | CLIDR_LOUU_SHIFT = 27,
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| 186 | CLIDR_LOC_MASK = 0x7,
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| 187 | CLIDR_LOC_SHIFT = 24,
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| 188 | CLIDR_LOUIS_MASK = 0x7,
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| 189 | CLIDR_LOUIS_SHIFT = 21,
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| 190 | CLIDR_NOCACHE = 0x0,
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| 191 | CLIDR_ICACHE_ONLY = 0x1,
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| 192 | CLIDR_DCACHE_ONLY = 0x2,
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| 193 | CLIDR_SEP_CACHE = 0x3,
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| 194 | CLIDR_UNI_CACHE = 0x4,
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| 195 | CLIDR_CACHE_MASK = 0x7,
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| 196 | /** levels counted from 0 */
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| 197 | #define CLIDR_CACHE(level, val) ((val >> (level * 3)) & CLIDR_CACHE_MASK)
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| 198 | };
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| 199 | CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
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| 200 | CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
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| 201 |
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| 202 | enum {
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| 203 | CCSELR_LEVEL_MASK = 0x7,
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| 204 | CCSELR_LEVEL_SHIFT = 1,
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| 205 | CCSELR_INSTRUCTION_FLAG = 1 << 0,
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| 206 | };
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| 207 | CONTROL_REG_GEN_READ(CSSELR, c0, 2, c0, 0);
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| 208 | CONTROL_REG_GEN_WRITE(CSSELR, c0, 2, c0, 0);
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| 209 | CONTROL_REG_GEN_READ(VPIDR, c0, 4, c0, 0);
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| 210 | CONTROL_REG_GEN_WRITE(VPIDR, c0, 4, c0, 0);
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| 211 | CONTROL_REG_GEN_READ(VMPIDR, c0, 4, c0, 5);
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| 212 | CONTROL_REG_GEN_WRITE(VMPIDR, c0, 4, c0, 5);
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| 213 |
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| 214 | /* System control registers */
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| 215 | /* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
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| 216 | * Manual ARMv7-A and ARMv7-R edition, page 1687 */
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| 217 | enum {
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| 218 | SCTLR_MMU_EN_FLAG = 1 << 0,
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| 219 | SCTLR_ALIGN_CHECK_EN_FLAG = 1 << 1, /* Allow alignemnt check */
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| 220 | SCTLR_CACHE_EN_FLAG = 1 << 2,
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| 221 | SCTLR_CP15_BARRIER_EN_FLAG = 1 << 5,
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| 222 | SCTLR_B_EN_FLAG = 1 << 7, /* ARMv6-, big endian switch */
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| 223 | SCTLR_SWAP_EN_FLAG = 1 << 10,
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| 224 | SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11,
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| 225 | SCTLR_INST_CACHE_EN_FLAG = 1 << 12,
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| 226 | SCTLR_HIGH_VECTORS_EN_FLAG = 1 << 13,
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| 227 | SCTLR_ROUND_ROBIN_EN_FLAG = 1 << 14,
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| 228 | SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17,
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| 229 | SCTLR_WRITE_XN_EN_FLAG = 1 << 19, /* Only if virt. supported */
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| 230 | SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */
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| 231 | SCTLR_FAST_IRQ_EN_FLAG = 1 << 21, /* Disable impl. specific feat*/
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| 232 | SCTLR_UNALIGNED_EN_FLAG = 1 << 22, /* Must be 1 on armv7 */
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| 233 | SCTLR_IRQ_VECTORS_EN_FLAG = 1 << 24,
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| 234 | SCTLR_BIG_ENDIAN_EXC_FLAG = 1 << 25,
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| 235 | SCTLR_NMFI_EN_FLAG = 1 << 27,
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| 236 | SCTLR_TEX_REMAP_EN_FLAG = 1 << 28,
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| 237 | SCTLR_ACCESS_FLAG_EN_FLAG = 1 << 29,
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| 238 | SCTLR_THUMB_EXC_EN_FLAG = 1 << 30,
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| 239 | };
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| 240 | CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0);
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| 241 | CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);
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| 242 | CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1);
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| 243 | CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
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| 244 |
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| 245 | enum {
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| 246 | CPACR_ASEDIS_FLAG = 1 << 31,
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| 247 | CPACR_D32DIS_FLAG = 1 << 30,
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| 248 | CPACR_TRCDIS_FLAG = 1 << 28,
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| 249 | #define CPACR_CP_MASK(cp) (0x3 << (cp * 2))
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| 250 | #define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2))
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| 251 | #define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2))
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| 252 | #define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2))
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| 253 | };
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| 254 | CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2);
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| 255 | CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
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| 256 |
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| 257 | /* Implemented as part of Security extensions */
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| 258 | enum {
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| 259 | SCR_SIF_FLAG = 1 << 9,
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| 260 | SCR_HCE_FLAG = 1 << 8,
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| 261 | SCR_SCD_FLAG = 1 << 7,
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| 262 | SCR_nET_FLAG = 1 << 6,
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| 263 | SCR_AW_FLAG = 1 << 5,
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| 264 | SCR_FW_FLAG = 1 << 4,
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| 265 | SCR_EA_FLAG = 1 << 3,
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| 266 | SCR_FIQ_FLAG = 1 << 2,
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| 267 | SCR_IRQ_FLAG = 1 << 1,
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| 268 | SCR_NS_FLAG = 1 << 0,
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| 269 | };
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| 270 | CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0);
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| 271 | CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
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| 272 | CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1);
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| 273 | CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
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| 274 |
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| 275 | enum {
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| 276 | NSACR_NSTRCDIS_FLAG = 1 << 20,
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| 277 | NSACR_RFR_FLAG = 1 << 19,
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| 278 | NSACR_NSASEDIS = 1 << 15,
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| 279 | NSACR_NSD32DIS = 1 << 14,
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| 280 | #define NSACR_CP_FLAG(cp) (1 << cp)
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| 281 | };
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| 282 | CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2);
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| 283 | CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
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| 284 |
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| 285 | /* Implemented as part of Virtualization extensions */
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| 286 | CONTROL_REG_GEN_READ(HSCTLR, c1, 4, c0, 0);
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| 287 | CONTROL_REG_GEN_WRITE(HSCTLR, c1, 4, c0, 0);
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| 288 | CONTROL_REG_GEN_READ(HACTLR, c1, 4, c0, 1);
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| 289 | CONTROL_REG_GEN_WRITE(HACTLR, c1, 4, c0, 1);
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| 290 |
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| 291 | CONTROL_REG_GEN_READ(HCR, c1, 4, c1, 0);
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| 292 | CONTROL_REG_GEN_WRITE(HCR, c1, 4, c1, 0);
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| 293 | CONTROL_REG_GEN_READ(HDCR, c1, 4, c1, 1);
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| 294 | CONTROL_REG_GEN_WRITE(HDCR, c1, 4, c1, 1);
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| 295 | CONTROL_REG_GEN_READ(HCPTR, c1, 4, c1, 2);
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| 296 | CONTROL_REG_GEN_WRITE(HCPTR, c1, 4, c1, 2);
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| 297 | CONTROL_REG_GEN_READ(HSTR, c1, 4, c1, 3);
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| 298 | CONTROL_REG_GEN_WRITE(HSTR, c1, 4, c1, 3);
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| 299 | CONTROL_REG_GEN_READ(HACR, c1, 4, c1, 7);
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| 300 | CONTROL_REG_GEN_WRITE(HACR, c1, 4, c1, 7);
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| 301 |
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| 302 | /* Memory protection and control registers */
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| 303 | enum {
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| 304 | TTBR_ADDR_MASK = 0xffffff80,
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| 305 | TTBR_NOS_FLAG = 1 << 5,
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| 306 | TTBR_RGN_MASK = 0x3 << 3,
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| 307 | TTBR_RGN_NO_CACHE = 0x0 << 3,
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| 308 | TTBR_RGN_WBWA_CACHE = 0x1 << 3,
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| 309 | TTBR_RGN_WT_CACHE = 0x2 << 3,
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| 310 | TTBR_RGN_WB_CACHE = 0x3 << 3,
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| 311 | TTBR_S_FLAG = 1 << 1,
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| 312 | TTBR_C_FLAG = 1 << 0,
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| 313 | };
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| 314 | CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
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| 315 | CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
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| 316 | CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1);
|
|---|
| 317 | CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
|
|---|
| 318 | CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2);
|
|---|
| 319 | CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
|
|---|
| 320 |
|
|---|
| 321 | CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2);
|
|---|
| 322 | CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
|
|---|
| 323 | CONTROL_REG_GEN_READ(VTCR, c2, 4, c1, 2);
|
|---|
| 324 | CONTROL_REG_GEN_WRITE(VTCR, c2, 4, c1, 2);
|
|---|
| 325 |
|
|---|
| 326 | /* PAE */
|
|---|
| 327 | CONTROL_REG_GEN_READ(TTBR0H, c2, 0, c2, 0);
|
|---|
| 328 | CONTROL_REG_GEN_WRITE(TTBR0H, c2, 0, c2, 0);
|
|---|
| 329 | CONTROL_REG_GEN_READ(TTBR1H, c2, 0, c2, 1);
|
|---|
| 330 | CONTROL_REG_GEN_WRITE(TTBR1H, c2, 0, c2, 1);
|
|---|
| 331 | CONTROL_REG_GEN_READ(HTTBRH, c2, 0, c2, 4);
|
|---|
| 332 | CONTROL_REG_GEN_WRITE(HTTBRH, c2, 0, c2, 4);
|
|---|
| 333 | CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6);
|
|---|
| 334 | CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
|
|---|
| 335 |
|
|---|
| 336 | CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0);
|
|---|
| 337 | CONTROL_REG_GEN_WRITE(DACR, c3, 0, c0, 0);
|
|---|
| 338 |
|
|---|
| 339 | /* Memory system fault registers */
|
|---|
| 340 | CONTROL_REG_GEN_READ(DFSR, c5, 0, c0, 0);
|
|---|
| 341 | CONTROL_REG_GEN_WRITE(DFSR, c5, 0, c0, 0);
|
|---|
| 342 | CONTROL_REG_GEN_READ(IFSR, c5, 0, c0, 1);
|
|---|
| 343 | CONTROL_REG_GEN_WRITE(IFSR, c5, 0, c0, 1);
|
|---|
| 344 |
|
|---|
| 345 | CONTROL_REG_GEN_READ(ADFSR, c5, 0, c1, 0);
|
|---|
| 346 | CONTROL_REG_GEN_WRITE(ADFSR, c5, 0, c1, 0);
|
|---|
| 347 | CONTROL_REG_GEN_READ(AIFSR, c5, 0, c1, 1);
|
|---|
| 348 | CONTROL_REG_GEN_WRITE(AIFSR, c5, 0, c1, 1);
|
|---|
| 349 |
|
|---|
| 350 | CONTROL_REG_GEN_READ(HADFSR, c5, 4, c1, 0);
|
|---|
| 351 | CONTROL_REG_GEN_WRITE(HADFSR, c5, 4, c1, 0);
|
|---|
| 352 | CONTROL_REG_GEN_READ(HAIFSR, c5, 4, c1, 1);
|
|---|
| 353 | CONTROL_REG_GEN_WRITE(HAIFSR, c5, 4, c1, 1);
|
|---|
| 354 | CONTROL_REG_GEN_READ(HSR, c5, 4, c2, 0);
|
|---|
| 355 | CONTROL_REG_GEN_WRITE(HSR, c5, 4, c2, 0);
|
|---|
| 356 |
|
|---|
| 357 | CONTROL_REG_GEN_READ(DFAR, c6, 0, c0, 0);
|
|---|
| 358 | CONTROL_REG_GEN_WRITE(DFAR, c6, 0, c0, 0);
|
|---|
| 359 | CONTROL_REG_GEN_READ(IFAR, c6, 0, c0, 2);
|
|---|
| 360 | CONTROL_REG_GEN_WRITE(IFAR, c6, 0, c0, 2);
|
|---|
| 361 |
|
|---|
| 362 | CONTROL_REG_GEN_READ(HDFAR, c6, 4, c0, 0);
|
|---|
| 363 | CONTROL_REG_GEN_WRITE(HDFAR, c6, 4, c0, 0);
|
|---|
| 364 | CONTROL_REG_GEN_READ(HIFAR, c6, 4, c0, 2);
|
|---|
| 365 | CONTROL_REG_GEN_WRITE(HIFAR, c6, 4, c0, 2);
|
|---|
| 366 | CONTROL_REG_GEN_READ(HPFAR, c6, 4, c0, 4);
|
|---|
| 367 | CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
|
|---|
| 368 |
|
|---|
| 369 | /* Cache maintenance, address translation and other */
|
|---|
| 370 | CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */
|
|---|
| 371 | CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
|
|---|
| 372 | CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
|
|---|
| 373 | CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0);
|
|---|
| 374 | CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0);
|
|---|
| 375 | CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */
|
|---|
| 376 | CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
|
|---|
| 377 | CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
|
|---|
| 378 | CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
|
|---|
| 379 | CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
|
|---|
| 380 | CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
|
|---|
| 381 | CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
|
|---|
| 382 |
|
|---|
| 383 | CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
|
|---|
| 384 | CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
|
|---|
| 385 |
|
|---|
| 386 | CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
|
|---|
| 387 | CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1);
|
|---|
| 388 | CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
|
|---|
| 389 | CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
|
|---|
| 390 | CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
|
|---|
| 391 | CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
|
|---|
| 392 | CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
|
|---|
| 393 | CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
|
|---|
| 394 |
|
|---|
| 395 |
|
|---|
| 396 | CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
|
|---|
| 397 | CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
|
|---|
| 398 | CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
|
|---|
| 399 | CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
|
|---|
| 400 | CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
|
|---|
| 401 |
|
|---|
| 402 | CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */
|
|---|
| 403 |
|
|---|
| 404 | CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
|
|---|
| 405 | CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
|
|---|
| 406 |
|
|---|
| 407 | CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0);
|
|---|
| 408 | CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1);
|
|---|
| 409 |
|
|---|
| 410 | /* TLB maintenance */
|
|---|
| 411 | CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
|
|---|
| 412 | CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
|
|---|
| 413 | CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
|
|---|
| 414 | CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
|
|---|
| 415 |
|
|---|
| 416 | CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
|
|---|
| 417 | CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
|
|---|
| 418 | CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
|
|---|
| 419 |
|
|---|
| 420 | CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
|
|---|
| 421 | CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
|
|---|
| 422 | CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
|
|---|
| 423 |
|
|---|
| 424 | CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
|
|---|
| 425 | CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
|
|---|
| 426 | CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
|
|---|
| 427 | CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
|
|---|
| 428 |
|
|---|
| 429 | CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
|
|---|
| 430 | CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
|
|---|
| 431 | CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
|
|---|
| 432 |
|
|---|
| 433 | CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
|
|---|
| 434 | CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
|
|---|
| 435 | CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
|
|---|
| 436 |
|
|---|
| 437 | /* c9 are performance monitoring resgisters */
|
|---|
| 438 | enum {
|
|---|
| 439 | PMCR_IMP_MASK = 0xff,
|
|---|
| 440 | PMCR_IMP_SHIFT = 24,
|
|---|
| 441 | PMCR_IDCODE_MASK = 0xff,
|
|---|
| 442 | PMCR_IDCODE_SHIFT = 16,
|
|---|
| 443 | PMCR_EVENT_NUM_MASK = 0x1f,
|
|---|
| 444 | PMCR_EVENT_NUM_SHIFT = 11,
|
|---|
| 445 | PMCR_DP_FLAG = 1 << 5,
|
|---|
| 446 | PMCR_X_FLAG = 1 << 4,
|
|---|
| 447 | PMCR_D_FLAG = 1 << 3,
|
|---|
| 448 | PMCR_C_FLAG = 1 << 2,
|
|---|
| 449 | PMCR_P_FLAG = 1 << 1,
|
|---|
| 450 | PMCR_E_FLAG = 1 << 0,
|
|---|
| 451 | };
|
|---|
| 452 | CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0);
|
|---|
| 453 | CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
|
|---|
| 454 | enum {
|
|---|
| 455 | PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31,
|
|---|
| 456 | #define PMCNTENSET_COUNTER_EN_FLAG(c) (1 << c)
|
|---|
| 457 | };
|
|---|
| 458 | CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1);
|
|---|
| 459 | CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
|
|---|
| 460 | CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0);
|
|---|
| 461 | CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
|
|---|
| 462 |
|
|---|
| 463 |
|
|---|
| 464 | /*c10 has tons of reserved too */
|
|---|
| 465 | CONTROL_REG_GEN_READ(PRRR, c10, 0, c2, 0); /* no PAE */
|
|---|
| 466 | CONTROL_REG_GEN_WRITE(PRRR, c10, 0, c2, 0); /* no PAE */
|
|---|
| 467 | CONTROL_REG_GEN_READ(MAIR0, c10, 0, c2, 0); /* PAE */
|
|---|
| 468 | CONTROL_REG_GEN_WRITE(MAIR0, c10, 0, c2, 0); /* PAE */
|
|---|
| 469 | CONTROL_REG_GEN_READ(NMRR, c10, 0, c2, 1); /* no PAE */
|
|---|
| 470 | CONTROL_REG_GEN_WRITE(NMRR, c10, 0, c2, 1); /* no PAE */
|
|---|
| 471 | CONTROL_REG_GEN_READ(MAIR1, c10, 0, c2, 1); /* PAE */
|
|---|
| 472 | CONTROL_REG_GEN_WRITE(MAIR1, c10, 0, c2, 1); /* PAE */
|
|---|
| 473 |
|
|---|
| 474 | CONTROL_REG_GEN_READ(AMAIR0, c10, 0, c3, 0); /* PAE */
|
|---|
| 475 | CONTROL_REG_GEN_WRITE(AMAIR0, c10, 0, c3, 0); /* PAE */
|
|---|
| 476 | CONTROL_REG_GEN_READ(AMAIR1, c10, 0, c3, 1); /* PAE */
|
|---|
| 477 | CONTROL_REG_GEN_WRITE(AMAIR1, c10, 0, c3, 1); /* PAE */
|
|---|
| 478 |
|
|---|
| 479 | CONTROL_REG_GEN_READ(HMAIR0, c10, 4, c2, 0);
|
|---|
| 480 | CONTROL_REG_GEN_WRITE(HMAIR0, c10, 4, c2, 0);
|
|---|
| 481 | CONTROL_REG_GEN_READ(HMAIR1, c10, 4, c2, 1);
|
|---|
| 482 | CONTROL_REG_GEN_WRITE(HMAIR1, c10, 4, c2, 1);
|
|---|
| 483 |
|
|---|
| 484 | CONTROL_REG_GEN_READ(HAMAIR0, c10, 4, c3, 0);
|
|---|
| 485 | CONTROL_REG_GEN_WRITE(HAMAIR0, c10, 4, c3, 0);
|
|---|
| 486 | CONTROL_REG_GEN_READ(HAMAIR1, c10, 4, c3, 1);
|
|---|
| 487 | CONTROL_REG_GEN_WRITE(HAMAIR1, c10, 4, c3, 1);
|
|---|
| 488 |
|
|---|
| 489 | /* c11 is reserved for TCM and DMA */
|
|---|
| 490 |
|
|---|
| 491 | /* Security extensions */
|
|---|
| 492 | CONTROL_REG_GEN_READ(VBAR, c12, 0, c0, 0);
|
|---|
| 493 | CONTROL_REG_GEN_WRITE(VBAR, c12, 0, c0, 0);
|
|---|
| 494 | CONTROL_REG_GEN_READ(MVBAR, c12, 0, c0, 1);
|
|---|
| 495 | CONTROL_REG_GEN_WRITE(MVBAR, c12, 0, c0, 1);
|
|---|
| 496 |
|
|---|
| 497 | CONTROL_REG_GEN_READ(ISR, c12, 0, c1, 0);
|
|---|
| 498 |
|
|---|
| 499 | CONTROL_REG_GEN_READ(HVBAR, c12, 4, c0, 0);
|
|---|
| 500 | CONTROL_REG_GEN_WRITE(HVBAR, c12, 4, c0, 0);
|
|---|
| 501 |
|
|---|
| 502 | /* Process context and thread id (FCSE) */
|
|---|
| 503 | CONTROL_REG_GEN_READ(FCSEIDR, c13, 0, c0, 0);
|
|---|
| 504 |
|
|---|
| 505 | CONTROL_REG_GEN_READ(CONTEXTIDR, c13, 0, c0, 1);
|
|---|
| 506 | CONTROL_REG_GEN_WRITE(CONTEXTIDR, c13, 0, c0, 1);
|
|---|
| 507 | CONTROL_REG_GEN_READ(TPIDRURW, c13, 0, c0, 2);
|
|---|
| 508 | CONTROL_REG_GEN_WRITE(TPIDRURW, c13, 0, c0, 2);
|
|---|
| 509 | CONTROL_REG_GEN_READ(TPIDRURO, c13, 0, c0, 3);
|
|---|
| 510 | CONTROL_REG_GEN_WRITE(TPIDRURO, c13, 0, c0, 3);
|
|---|
| 511 | CONTROL_REG_GEN_READ(TPIDRPRW, c13, 0, c0, 4);
|
|---|
| 512 | CONTROL_REG_GEN_WRITE(TPIDRPRW, c13, 0, c0, 4);
|
|---|
| 513 |
|
|---|
| 514 | CONTROL_REG_GEN_READ(HTPIDR, c13, 4, c0, 2);
|
|---|
| 515 | CONTROL_REG_GEN_WRITE(HTPIDR, c13, 4, c0, 2);
|
|---|
| 516 |
|
|---|
| 517 | /* Generic Timer Extensions */
|
|---|
| 518 | CONTROL_REG_GEN_READ(CNTFRQ, c14, 0, c0, 0);
|
|---|
| 519 | CONTROL_REG_GEN_WRITE(CNTFRQ, c14, 0, c0, 0);
|
|---|
| 520 | CONTROL_REG_GEN_READ(CNTKCTL, c14, 0, c1, 0);
|
|---|
| 521 | CONTROL_REG_GEN_WRITE(CNTKCTL, c14, 0, c1, 0);
|
|---|
| 522 |
|
|---|
| 523 | CONTROL_REG_GEN_READ(CNTP_TVAL, c14, 0, c2, 0);
|
|---|
| 524 | CONTROL_REG_GEN_WRITE(CNTP_TVAL, c14, 0, c2, 0);
|
|---|
| 525 | CONTROL_REG_GEN_READ(CNTP_CTL, c14, 0, c2, 1);
|
|---|
| 526 | CONTROL_REG_GEN_WRITE(CNTP_CTL, c14, 0, c2, 1);
|
|---|
| 527 |
|
|---|
| 528 | CONTROL_REG_GEN_READ(CNTV_TVAL, c14, 0, c3, 0);
|
|---|
| 529 | CONTROL_REG_GEN_WRITE(CNTV_TVAL, c14, 0, c3, 0);
|
|---|
| 530 | CONTROL_REG_GEN_READ(CNTV_CTL, c14, 0, c3, 1);
|
|---|
| 531 | CONTROL_REG_GEN_WRITE(CNTV_CTL, c14, 0, c3, 1);
|
|---|
| 532 |
|
|---|
| 533 | CONTROL_REG_GEN_READ(CNTHCTL, c14, 4, c1, 0);
|
|---|
| 534 | CONTROL_REG_GEN_WRITE(CNTHCTL, c14, 4, c1, 0);
|
|---|
| 535 |
|
|---|
| 536 | CONTROL_REG_GEN_READ(CNTHP_TVAL, c14, 4, c2, 0);
|
|---|
| 537 | CONTROL_REG_GEN_WRITE(CNTHP_TVAL, c14, 4, c2, 0);
|
|---|
| 538 | CONTROL_REG_GEN_READ(CNTHP_CTL, c14, 4, c2, 1);
|
|---|
| 539 | CONTROL_REG_GEN_WRITE(CNTHP_CTL, c14, 4, c2, 1);
|
|---|
| 540 |
|
|---|
| 541 | #endif
|
|---|
| 542 |
|
|---|
| 543 | /** @}
|
|---|
| 544 | */
|
|---|
