source: mainline/uspace/srv/hw/netif/ne2000/dp8390.c@ 544a2e4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 544a2e4 was c7bbf029, checked in by Martin Decky <martin@…>, 15 years ago

improve stack traces and assertions
reduce header files pollution
  • Property mode set to 100644
File size: 16.8 KB
Line 
1/*
2 * Copyright (c) 2009 Lukas Mejdrech
3 * Copyright (c) 2011 Martin Decky
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * This code is based upon the NE2000 driver for MINIX,
32 * distributed according to a BSD-style license.
33 *
34 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
35 * Copyright (c) 1992, 1994 Philip Homburg
36 * Copyright (c) 1996 G. Falzoni
37 *
38 */
39
40/** @addtogroup ne2000
41 * @{
42 */
43
44/** @file
45 *
46 * NE2000 (based on DP8390) network interface core implementation.
47 * Only the basic NE2000 PIO (ISA) interface is supported, remote
48 * DMA is completely absent from this code for simplicity.
49 *
50 */
51
52#include <assert.h>
53#include <byteorder.h>
54#include <errno.h>
55#include <stdio.h>
56#include <libarch/ddi.h>
57#include <net/packet.h>
58#include <packet_client.h>
59#include "dp8390.h"
60
61/** Page size */
62#define DP_PAGE 256
63
64/** 6 * DP_PAGE >= 1514 bytes */
65#define SQ_PAGES 6
66
67/* NE2000 implementation. */
68
69/** NE2000 Data Register */
70#define NE2K_DATA 0x0010
71
72/** NE2000 Reset register */
73#define NE2K_RESET 0x001f
74
75/** NE2000 data start */
76#define NE2K_START 0x4000
77
78/** NE2000 data size */
79#define NE2K_SIZE 0x4000
80
81/** NE2000 retry count */
82#define NE2K_RETRY 0x1000
83
84/** NE2000 error messages rate limiting */
85#define NE2K_ERL 10
86
87/** Minimum Ethernet packet size in bytes */
88#define ETH_MIN_PACK_SIZE 60
89
90/** Maximum Ethernet packet size in bytes */
91#define ETH_MAX_PACK_SIZE_TAGGED 1518
92
93/** Type definition of the receive header
94 *
95 */
96typedef struct {
97 /** Copy of RSR */
98 uint8_t status;
99
100 /** Pointer to next packet */
101 uint8_t next;
102
103 /** Receive Byte Count Low */
104 uint8_t rbcl;
105
106 /** Receive Byte Count High */
107 uint8_t rbch;
108} recv_header_t;
109
110/** Read a memory block word by word.
111 *
112 * @param[in] port Source address.
113 * @param[out] buf Destination buffer.
114 * @param[in] size Memory block size in bytes.
115 *
116 */
117static void pio_read_buf_16(void *port, void *buf, size_t size)
118{
119 size_t i;
120
121 for (i = 0; (i << 1) < size; i++)
122 *((uint16_t *) buf + i) = pio_read_16((ioport16_t *) (port));
123}
124
125/** Write a memory block word by word.
126 *
127 * @param[in] port Destination address.
128 * @param[in] buf Source buffer.
129 * @param[in] size Memory block size in bytes.
130 *
131 */
132static void pio_write_buf_16(void *port, void *buf, size_t size)
133{
134 size_t i;
135
136 for (i = 0; (i << 1) < size; i++)
137 pio_write_16((ioport16_t *) port, *((uint16_t *) buf + i));
138}
139
140static void ne2k_download(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
141{
142 size_t esize = size & ~1;
143
144 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
145 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
146 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
147 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
148 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
149
150 if (esize != 0) {
151 pio_read_buf_16(ne2k->data_port, buf, esize);
152 size -= esize;
153 buf += esize;
154 }
155
156 if (size) {
157 assert(size == 1);
158
159 uint16_t word = pio_read_16(ne2k->data_port);
160 memcpy(buf, &word, 1);
161 }
162}
163
164static void ne2k_upload(ne2k_t *ne2k, void *buf, size_t addr, size_t size)
165{
166 size_t esize = size & ~1;
167
168 pio_write_8(ne2k->port + DP_RBCR0, esize & 0xff);
169 pio_write_8(ne2k->port + DP_RBCR1, (esize >> 8) & 0xff);
170 pio_write_8(ne2k->port + DP_RSAR0, addr & 0xff);
171 pio_write_8(ne2k->port + DP_RSAR1, (addr >> 8) & 0xff);
172 pio_write_8(ne2k->port + DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
173
174 if (esize != 0) {
175 pio_write_buf_16(ne2k->data_port, buf, esize);
176 size -= esize;
177 buf += esize;
178 }
179
180 if (size) {
181 assert(size == 1);
182
183 uint16_t word = 0;
184
185 memcpy(&word, buf, 1);
186 pio_write_16(ne2k->data_port, word);
187 }
188}
189
190static void ne2k_init(ne2k_t *ne2k)
191{
192 unsigned int i;
193
194 /* Reset the ethernet card */
195 uint8_t val = pio_read_8(ne2k->port + NE2K_RESET);
196 usleep(2000);
197 pio_write_8(ne2k->port + NE2K_RESET, val);
198 usleep(2000);
199
200 /* Reset the DP8390 */
201 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
202 for (i = 0; i < NE2K_RETRY; i++) {
203 if (pio_read_8(ne2k->port + DP_ISR) != 0)
204 break;
205 }
206}
207
208/** Probe and initialize the network interface.
209 *
210 * @param[in,out] ne2k Network interface structure.
211 * @param[in] port Device address.
212 * @param[in] irq Device interrupt vector.
213 *
214 * @return EOK on success.
215 * @return EXDEV if the network interface was not recognized.
216 *
217 */
218int ne2k_probe(ne2k_t *ne2k, void *port, int irq)
219{
220 unsigned int i;
221
222 /* General initialization */
223 ne2k->port = port;
224 ne2k->data_port = ne2k->port + NE2K_DATA;
225 ne2k->irq = irq;
226 ne2k->probed = false;
227 ne2k->up = false;
228
229 ne2k_init(ne2k);
230
231 /* Check if the DP8390 is really there */
232 uint8_t val = pio_read_8(ne2k->port + DP_CR);
233 if ((val & (CR_STP | CR_DM_ABORT)) != (CR_STP | CR_DM_ABORT))
234 return EXDEV;
235
236 /* Disable the receiver and init TCR and DCR */
237 pio_write_8(ne2k->port + DP_RCR, RCR_MON);
238 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
239 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
240
241 /* Setup a transfer to get the MAC address */
242 pio_write_8(ne2k->port + DP_RBCR0, ETH_ADDR << 1);
243 pio_write_8(ne2k->port + DP_RBCR1, 0);
244 pio_write_8(ne2k->port + DP_RSAR0, 0);
245 pio_write_8(ne2k->port + DP_RSAR1, 0);
246 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
247
248 for (i = 0; i < ETH_ADDR; i++)
249 ne2k->mac[i] = pio_read_16(ne2k->data_port);
250
251 ne2k->probed = true;
252 return EOK;
253}
254
255/** Start the network interface.
256 *
257 * @param[in,out] ne2k Network interface structure.
258 *
259 * @return EOK on success.
260 * @return EXDEV if the network interface is disabled.
261 *
262 */
263int ne2k_up(ne2k_t *ne2k)
264{
265 if (!ne2k->probed)
266 return EXDEV;
267
268 ne2k_init(ne2k);
269
270 /*
271 * Setup send queue. Use the first
272 * SQ_PAGES of NE2000 memory for the send
273 * buffer.
274 */
275 ne2k->sq.dirty = false;
276 ne2k->sq.page = NE2K_START / DP_PAGE;
277 fibril_mutex_initialize(&ne2k->sq_mutex);
278 fibril_condvar_initialize(&ne2k->sq_cv);
279
280 /*
281 * Setup receive ring buffer. Use all the rest
282 * of the NE2000 memory (except the first SQ_PAGES
283 * reserved for the send buffer) for the receive
284 * ring buffer.
285 */
286 ne2k->start_page = ne2k->sq.page + SQ_PAGES;
287 ne2k->stop_page = ne2k->sq.page + NE2K_SIZE / DP_PAGE;
288
289 /*
290 * Initialization of the DP8390 following the mandatory procedure
291 * in reference manual ("DP8390D/NS32490D NIC Network Interface
292 * Controller", National Semiconductor, July 1995, Page 29).
293 */
294
295 /* Step 1: */
296 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
297
298 /* Step 2: */
299 pio_write_8(ne2k->port + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
300
301 /* Step 3: */
302 pio_write_8(ne2k->port + DP_RBCR0, 0);
303 pio_write_8(ne2k->port + DP_RBCR1, 0);
304
305 /* Step 4: */
306 pio_write_8(ne2k->port + DP_RCR, RCR_AB);
307
308 /* Step 5: */
309 pio_write_8(ne2k->port + DP_TCR, TCR_INTERNAL);
310
311 /* Step 6: */
312 pio_write_8(ne2k->port + DP_BNRY, ne2k->start_page);
313 pio_write_8(ne2k->port + DP_PSTART, ne2k->start_page);
314 pio_write_8(ne2k->port + DP_PSTOP, ne2k->stop_page);
315
316 /* Step 7: */
317 pio_write_8(ne2k->port + DP_ISR, 0xff);
318
319 /* Step 8: */
320 pio_write_8(ne2k->port + DP_IMR,
321 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
322
323 /* Step 9: */
324 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_DM_ABORT | CR_STP);
325
326 pio_write_8(ne2k->port + DP_PAR0, ne2k->mac[0]);
327 pio_write_8(ne2k->port + DP_PAR1, ne2k->mac[1]);
328 pio_write_8(ne2k->port + DP_PAR2, ne2k->mac[2]);
329 pio_write_8(ne2k->port + DP_PAR3, ne2k->mac[3]);
330 pio_write_8(ne2k->port + DP_PAR4, ne2k->mac[4]);
331 pio_write_8(ne2k->port + DP_PAR5, ne2k->mac[5]);
332
333 pio_write_8(ne2k->port + DP_MAR0, 0xff);
334 pio_write_8(ne2k->port + DP_MAR1, 0xff);
335 pio_write_8(ne2k->port + DP_MAR2, 0xff);
336 pio_write_8(ne2k->port + DP_MAR3, 0xff);
337 pio_write_8(ne2k->port + DP_MAR4, 0xff);
338 pio_write_8(ne2k->port + DP_MAR5, 0xff);
339 pio_write_8(ne2k->port + DP_MAR6, 0xff);
340 pio_write_8(ne2k->port + DP_MAR7, 0xff);
341
342 pio_write_8(ne2k->port + DP_CURR, ne2k->start_page + 1);
343
344 /* Step 10: */
345 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_DM_ABORT | CR_STA);
346
347 /* Step 11: */
348 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
349
350 /* Reset counters by reading */
351 pio_read_8(ne2k->port + DP_CNTR0);
352 pio_read_8(ne2k->port + DP_CNTR1);
353 pio_read_8(ne2k->port + DP_CNTR2);
354
355 /* Finish the initialization */
356 ne2k->up = true;
357 return EOK;
358}
359
360/** Stop the network interface.
361 *
362 * @param[in,out] ne2k Network interface structure.
363 *
364 */
365void ne2k_down(ne2k_t *ne2k)
366{
367 if ((ne2k->probed) && (ne2k->up)) {
368 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
369 ne2k_init(ne2k);
370 ne2k->up = false;
371 }
372}
373
374/** Send a frame.
375 *
376 * @param[in,out] ne2k Network interface structure.
377 * @param[in] packet Frame to be sent.
378 *
379 */
380void ne2k_send(ne2k_t *ne2k, packet_t *packet)
381{
382 assert(ne2k->probed);
383 assert(ne2k->up);
384
385 fibril_mutex_lock(&ne2k->sq_mutex);
386
387 while (ne2k->sq.dirty)
388 fibril_condvar_wait(&ne2k->sq_cv, &ne2k->sq_mutex);
389
390 void *buf = packet_get_data(packet);
391 size_t size = packet_get_data_length(packet);
392
393 if ((size < ETH_MIN_PACK_SIZE) || (size > ETH_MAX_PACK_SIZE_TAGGED)) {
394 fibril_mutex_unlock(&ne2k->sq_mutex);
395 fprintf(stderr, "%s: Frame dropped (invalid size %zu bytes)\n",
396 NAME, size);
397 return;
398 }
399
400 /* Upload the frame to the ethernet card */
401 ne2k_upload(ne2k, buf, ne2k->sq.page * DP_PAGE, size);
402 ne2k->sq.dirty = true;
403 ne2k->sq.size = size;
404
405 /* Initialize the transfer */
406 pio_write_8(ne2k->port + DP_TPSR, ne2k->sq.page);
407 pio_write_8(ne2k->port + DP_TBCR0, size & 0xff);
408 pio_write_8(ne2k->port + DP_TBCR1, (size >> 8) & 0xff);
409 pio_write_8(ne2k->port + DP_CR, CR_TXP | CR_STA);
410
411 fibril_mutex_unlock(&ne2k->sq_mutex);
412}
413
414static void ne2k_reset(ne2k_t *ne2k)
415{
416 unsigned int i;
417
418 /* Stop the chip */
419 pio_write_8(ne2k->port + DP_CR, CR_STP | CR_DM_ABORT);
420 pio_write_8(ne2k->port + DP_RBCR0, 0);
421 pio_write_8(ne2k->port + DP_RBCR1, 0);
422
423 for (i = 0; i < NE2K_RETRY; i++) {
424 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RST) != 0)
425 break;
426 }
427
428 pio_write_8(ne2k->port + DP_TCR, TCR_1EXTERNAL | TCR_OFST);
429 pio_write_8(ne2k->port + DP_CR, CR_STA | CR_DM_ABORT);
430 pio_write_8(ne2k->port + DP_TCR, TCR_NORMAL);
431
432 /* Acknowledge the ISR_RDC (remote DMA) interrupt */
433 for (i = 0; i < NE2K_RETRY; i++) {
434 if ((pio_read_8(ne2k->port + DP_ISR) & ISR_RDC) != 0)
435 break;
436 }
437
438 uint8_t val = pio_read_8(ne2k->port + DP_ISR);
439 pio_write_8(ne2k->port + DP_ISR, val & ~ISR_RDC);
440
441 /*
442 * Reset the transmit ring. If we were transmitting a frame,
443 * we pretend that the packet is processed. Higher layers will
444 * retransmit if the packet wasn't actually sent.
445 */
446 fibril_mutex_lock(&ne2k->sq_mutex);
447 ne2k->sq.dirty = false;
448 fibril_mutex_unlock(&ne2k->sq_mutex);
449}
450
451static frame_t *ne2k_receive_frame(ne2k_t *ne2k, uint8_t page, size_t length)
452{
453 frame_t *frame = (frame_t *) malloc(sizeof(frame_t));
454 if (frame == NULL)
455 return NULL;
456
457 link_initialize(&frame->link);
458
459 frame->packet = netif_packet_get_1(length);
460 if (frame->packet == NULL) {
461 free(frame);
462 return NULL;
463 }
464
465 void *buf = packet_suffix(frame->packet, length);
466 bzero(buf, length);
467 uint8_t last = page + length / DP_PAGE;
468
469 if (last >= ne2k->stop_page) {
470 size_t left = (ne2k->stop_page - page) * DP_PAGE
471 - sizeof(recv_header_t);
472
473 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
474 left);
475 ne2k_download(ne2k, buf + left, ne2k->start_page * DP_PAGE,
476 length - left);
477 } else
478 ne2k_download(ne2k, buf, page * DP_PAGE + sizeof(recv_header_t),
479 length);
480
481 ne2k->stats.receive_packets++;
482 return frame;
483}
484
485static link_t *ne2k_receive(ne2k_t *ne2k)
486{
487 /*
488 * Allocate memory for the list of received frames.
489 * If the allocation fails here we still receive the
490 * frames from the network, but they will be lost.
491 */
492 link_t *frames = (link_t *) malloc(sizeof(link_t));
493 if (frames != NULL)
494 list_initialize(frames);
495
496 while (true) {
497 uint8_t boundary = pio_read_8(ne2k->port + DP_BNRY) + 1;
498
499 if (boundary == ne2k->stop_page)
500 boundary = ne2k->start_page;
501
502 pio_write_8(ne2k->port + DP_CR, CR_PS_P1 | CR_STA);
503 uint8_t current = pio_read_8(ne2k->port + DP_CURR);
504 pio_write_8(ne2k->port + DP_CR, CR_PS_P0 | CR_STA);
505
506 if (current == boundary)
507 /* No more frames to process */
508 break;
509
510 recv_header_t header;
511 size_t size = sizeof(header);
512 size_t offset = boundary * DP_PAGE;
513
514 /* Get the frame header */
515 pio_write_8(ne2k->port + DP_RBCR0, size & 0xff);
516 pio_write_8(ne2k->port + DP_RBCR1, (size >> 8) & 0xff);
517 pio_write_8(ne2k->port + DP_RSAR0, offset & 0xff);
518 pio_write_8(ne2k->port + DP_RSAR1, (offset >> 8) & 0xff);
519 pio_write_8(ne2k->port + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
520
521 pio_read_buf_16(ne2k->data_port, (void *) &header, size);
522
523 size_t length =
524 (((size_t) header.rbcl) | (((size_t) header.rbch) << 8)) - size;
525 uint8_t next = header.next;
526
527 if ((length < ETH_MIN_PACK_SIZE)
528 || (length > ETH_MAX_PACK_SIZE_TAGGED)) {
529 fprintf(stderr, "%s: Rant frame (%zu bytes)\n", NAME, length);
530 next = current;
531 } else if ((header.next < ne2k->start_page)
532 || (header.next > ne2k->stop_page)) {
533 fprintf(stderr, "%s: Malformed next frame %u\n", NAME,
534 header.next);
535 next = current;
536 } else if (header.status & RSR_FO) {
537 /*
538 * This is very serious, so we issue a warning and
539 * reset the buffers.
540 */
541 fprintf(stderr, "%s: FIFO overrun\n", NAME);
542 ne2k->overruns++;
543 next = current;
544 } else if ((header.status & RSR_PRX) && (ne2k->up)) {
545 if (frames != NULL) {
546 frame_t *frame = ne2k_receive_frame(ne2k, boundary, length);
547 if (frame != NULL)
548 list_append(&frame->link, frames);
549 }
550 }
551
552 /*
553 * Update the boundary pointer
554 * to the value of the page
555 * prior to the next packet to
556 * be processed.
557 */
558 if (next == ne2k->start_page)
559 next = ne2k->stop_page - 1;
560 else
561 next--;
562
563 pio_write_8(ne2k->port + DP_BNRY, next);
564 }
565
566 return frames;
567}
568
569link_t *ne2k_interrupt(ne2k_t *ne2k, uint8_t isr, uint8_t tsr)
570{
571 /* List of received frames */
572 link_t *frames = NULL;
573
574 if (isr & (ISR_PTX | ISR_TXE)) {
575 if (isr & ISR_TXE)
576 ne2k->stats.send_errors++;
577 else {
578 if (tsr & TSR_PTX)
579 ne2k->stats.send_packets++;
580
581 if (tsr & TSR_COL)
582 ne2k->stats.collisions++;
583
584 if (tsr & TSR_ABT)
585 ne2k->stats.send_aborted_errors++;
586
587 if (tsr & TSR_CRS)
588 ne2k->stats.send_carrier_errors++;
589
590 if (tsr & TSR_FU) {
591 ne2k->underruns++;
592 if (ne2k->underruns < NE2K_ERL)
593 fprintf(stderr, "%s: FIFO underrun\n", NAME);
594 }
595
596 if (tsr & TSR_CDH) {
597 ne2k->stats.send_heartbeat_errors++;
598 if (ne2k->stats.send_heartbeat_errors < NE2K_ERL)
599 fprintf(stderr, "%s: CD heartbeat failure\n", NAME);
600 }
601
602 if (tsr & TSR_OWC)
603 ne2k->stats.send_window_errors++;
604 }
605
606 fibril_mutex_lock(&ne2k->sq_mutex);
607
608 if (ne2k->sq.dirty) {
609 /* Prepare the buffer for next packet */
610 ne2k->sq.dirty = false;
611 ne2k->sq.size = 0;
612
613 /* Signal a next frame to be sent */
614 fibril_condvar_broadcast(&ne2k->sq_cv);
615 } else {
616 ne2k->misses++;
617 if (ne2k->misses < NE2K_ERL)
618 fprintf(stderr, "%s: Spurious PTX interrupt\n", NAME);
619 }
620
621 fibril_mutex_unlock(&ne2k->sq_mutex);
622 }
623
624 if (isr & ISR_RXE)
625 ne2k->stats.receive_errors++;
626
627 if (isr & ISR_CNT) {
628 ne2k->stats.receive_crc_errors +=
629 pio_read_8(ne2k->port + DP_CNTR0);
630 ne2k->stats.receive_frame_errors +=
631 pio_read_8(ne2k->port + DP_CNTR1);
632 ne2k->stats.receive_missed_errors +=
633 pio_read_8(ne2k->port + DP_CNTR2);
634 }
635
636 if (isr & ISR_PRX)
637 frames = ne2k_receive(ne2k);
638
639 if (isr & ISR_RST) {
640 /*
641 * The chip is stopped, and all arrived
642 * frames are delivered.
643 */
644 ne2k_reset(ne2k);
645 }
646
647 /* Unmask interrupts to be processed in the next round */
648 pio_write_8(ne2k->port + DP_IMR,
649 IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE | IMR_CNTE);
650
651 return frames;
652}
653
654/** @}
655 */
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