[5cd136ab] | 1 | /*
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[832cbe7] | 2 | * Copyright (c) 2025 Jiri Svoboda
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[5cd136ab] | 3 | * Copyright (c) 2010 Lenka Trochtova
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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[0adddea] | 29 |
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[ae7d03c] | 30 | /** @addtogroup libc
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[5cd136ab] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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[0adddea] | 35 |
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[5cd136ab] | 36 | #include <device/hw_res.h>
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| 37 | #include <errno.h>
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| 38 | #include <async.h>
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[38d150e] | 39 | #include <stdlib.h>
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[5cd136ab] | 40 |
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[b7fd2a0] | 41 | errno_t hw_res_get_resource_list(async_sess_t *sess,
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[79ae36dd] | 42 | hw_resource_list_t *hw_resources)
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[5cd136ab] | 43 | {
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[96b02eb9] | 44 | sysarg_t count = 0;
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[a35b458] | 45 |
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[79ae36dd] | 46 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 47 |
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[b7fd2a0] | 48 | errno_t rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[f724e82] | 49 | HW_RES_GET_RESOURCE_LIST, &count);
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[a35b458] | 50 |
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[79ae36dd] | 51 | if (rc != EOK) {
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| 52 | async_exchange_end(exch);
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[be942bc] | 53 | return rc;
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[79ae36dd] | 54 | }
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[a35b458] | 55 |
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[5cd136ab] | 56 | size_t size = count * sizeof(hw_resource_t);
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[79ae36dd] | 57 | hw_resource_t *resources = (hw_resource_t *) malloc(size);
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| 58 | if (resources == NULL) {
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| 59 | // FIXME: This is protocol violation
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| 60 | async_exchange_end(exch);
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[be942bc] | 61 | return ENOMEM;
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[79ae36dd] | 62 | }
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[a35b458] | 63 |
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[79ae36dd] | 64 | rc = async_data_read_start(exch, resources, size);
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| 65 | async_exchange_end(exch);
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[a35b458] | 66 |
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[be942bc] | 67 | if (rc != EOK) {
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[79ae36dd] | 68 | free(resources);
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[be942bc] | 69 | return rc;
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[5cd136ab] | 70 | }
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[a35b458] | 71 |
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[79ae36dd] | 72 | hw_resources->resources = resources;
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| 73 | hw_resources->count = count;
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[a35b458] | 74 |
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[be942bc] | 75 | return EOK;
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[5cd136ab] | 76 | }
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| 77 |
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[b7fd2a0] | 78 | errno_t hw_res_enable_interrupt(async_sess_t *sess, int irq)
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[5cd136ab] | 79 | {
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[79ae36dd] | 80 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 81 |
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[b7fd2a0] | 82 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[cccd60c3] | 83 | HW_RES_ENABLE_INTERRUPT, irq);
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[79ae36dd] | 84 | async_exchange_end(exch);
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[a35b458] | 85 |
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[cccd60c3] | 86 | return rc;
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[5cd136ab] | 87 | }
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[0adddea] | 88 |
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[b7fd2a0] | 89 | errno_t hw_res_disable_interrupt(async_sess_t *sess, int irq)
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[d51838f] | 90 | {
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| 91 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 92 |
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[b7fd2a0] | 93 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[d51838f] | 94 | HW_RES_DISABLE_INTERRUPT, irq);
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| 95 | async_exchange_end(exch);
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[a35b458] | 96 |
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[d51838f] | 97 | return rc;
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| 98 | }
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| 99 |
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[b7fd2a0] | 100 | errno_t hw_res_clear_interrupt(async_sess_t *sess, int irq)
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[d51838f] | 101 | {
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| 102 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 103 |
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[b7fd2a0] | 104 | errno_t rc = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[d51838f] | 105 | HW_RES_CLEAR_INTERRUPT, irq);
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| 106 | async_exchange_end(exch);
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[a35b458] | 107 |
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[d51838f] | 108 | return rc;
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| 109 | }
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| 110 |
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[561c301] | 111 | /** Setup DMA channel to specified place and mode.
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| 112 | *
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| 113 | * @param channel DMA channel.
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| 114 | * @param pa Physical address of the buffer.
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| 115 | * @param size DMA buffer size.
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| 116 | * @param mode Mode of the DMA channel:
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| 117 | * - Read or Write
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| 118 | * - Allow automatic reset
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| 119 | * - Use address decrement instead of increment
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| 120 | * - Use SINGLE/BLOCK/ON DEMAND transfer mode
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| 121 | *
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[a0d1d9d] | 122 | * @return Error code.
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[561c301] | 123 | *
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[a0d1d9d] | 124 | */
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[b7fd2a0] | 125 | errno_t hw_res_dma_channel_setup(async_sess_t *sess,
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[301032a] | 126 | unsigned channel, uint32_t pa, uint32_t size, uint8_t mode)
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[9991c47] | 127 | {
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| 128 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 129 |
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[301032a] | 130 | const uint32_t packed = (channel & 0xffff) | (mode << 16);
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[b7fd2a0] | 131 | const errno_t ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[301032a] | 132 | HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
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[a35b458] | 133 |
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[9991c47] | 134 | async_exchange_end(exch);
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[a35b458] | 135 |
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[9991c47] | 136 | return ret;
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| 137 | }
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| 138 |
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[561c301] | 139 | /** Query remaining bytes in the buffer.
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| 140 | *
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| 141 | * @param channel DMA channel.
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| 142 | *
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[c19a5a59] | 143 | * @param[out] rem Number of bytes remaining in the buffer if positive.
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| 144 | *
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| 145 | * @return Error code.
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[561c301] | 146 | *
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[6fd365d] | 147 | */
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[b7fd2a0] | 148 | errno_t hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel, size_t *rem)
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[6fd365d] | 149 | {
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| 150 | async_exch_t *exch = async_exchange_begin(sess);
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[a35b458] | 151 |
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[6fd365d] | 152 | sysarg_t remain;
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[b7fd2a0] | 153 | const errno_t ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[6fd365d] | 154 | HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
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[a35b458] | 155 |
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[6fd365d] | 156 | async_exchange_end(exch);
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[a35b458] | 157 |
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[6fd365d] | 158 | if (ret == EOK)
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[c19a5a59] | 159 | *rem = remain;
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[a35b458] | 160 |
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[6fd365d] | 161 | return ret;
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| 162 | }
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| 163 |
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[832cbe7] | 164 | /** Query legacy IO claims.
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[443695e] | 165 | *
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| 166 | * @param sess HW res session
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[832cbe7] | 167 | * @param rclaims Place to store the claims
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[443695e] | 168 | *
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| 169 | * @return Error code.
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| 170 | *
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| 171 | */
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[832cbe7] | 172 | errno_t hw_res_query_legacy_io(async_sess_t *sess, hw_res_claims_t *rclaims)
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[443695e] | 173 | {
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| 174 | async_exch_t *exch = async_exchange_begin(sess);
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| 175 |
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[832cbe7] | 176 | sysarg_t claims;
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[443695e] | 177 | const errno_t ret = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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[832cbe7] | 178 | HW_RES_QUERY_LEGACY_IO, &claims);
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[443695e] | 179 |
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| 180 | async_exchange_end(exch);
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| 181 |
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| 182 | if (ret == EOK)
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[832cbe7] | 183 | *rclaims = claims;
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| 184 |
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| 185 | return ret;
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| 186 | }
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| 187 |
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| 188 | /** Claim legacy IO devices.
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| 189 | *
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| 190 | * @param sess HW res session
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| 191 | * @param claims Claims
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| 192 | *
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| 193 | * @return Error code.
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| 194 | *
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| 195 | */
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| 196 | errno_t hw_res_claim_legacy_io(async_sess_t *sess, hw_res_claims_t claims)
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| 197 | {
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| 198 | async_exch_t *exch = async_exchange_begin(sess);
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| 199 |
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| 200 | const errno_t ret = async_req_2_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
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| 201 | HW_RES_CLAIM_LEGACY_IO, claims);
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| 202 |
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| 203 | async_exchange_end(exch);
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[443695e] | 204 |
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| 205 | return ret;
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| 206 | }
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| 207 |
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[0adddea] | 208 | /** @}
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[be942bc] | 209 | */
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