source: mainline/uspace/drv/uhci-hcd/uhci_hc.c@ 87037c48

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 87037c48 was eb2a48a, checked in by Jan Vesely <jano.vesely@…>, 15 years ago

Set the value explicitly even if it's the default
  • Property mode set to 100644
File size: 15.9 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci_hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
63static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
64static void uhci_hc_init_hw(uhci_hc_t *instance);
65
66static int uhci_hc_interrupt_emulator(void *arg);
67static int uhci_hc_debug_checker(void *arg);
68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 /* Setup UHCI function. */
100 instance->ddf_instance = fun;
101
102 /* allow access to hc control registers */
103 regs_t *io;
104 ret = pio_enable(regs, reg_size, (void**)&io);
105 CHECK_RET_DEST_FUN_RETURN(ret,
106 "Failed(%d) to gain access to registers at %p: %s.\n",
107 ret, str_error(ret), io);
108 instance->registers = io;
109 usb_log_debug("Device registers at %p(%u) accessible.\n",
110 io, reg_size);
111
112 ret = uhci_hc_init_mem_structures(instance);
113 CHECK_RET_DEST_FUN_RETURN(ret,
114 "Failed to initialize UHCI memory structures.\n");
115
116 uhci_hc_init_hw(instance);
117 if (!interrupts) {
118 instance->cleaner =
119 fibril_create(uhci_hc_interrupt_emulator, instance);
120 fibril_add_ready(instance->cleaner);
121 }
122
123 instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
124 fibril_add_ready(instance->debug_checker);
125
126 usb_log_info("Started UHCI driver.\n");
127 return EOK;
128#undef CHECK_RET_DEST_FUN_RETURN
129}
130/*----------------------------------------------------------------------------*/
131/** Initialize UHCI hc hw resources.
132 *
133 * @param[in] instance UHCI structure to use.
134 * For magic values see UHCI Design Guide
135 */
136void uhci_hc_init_hw(uhci_hc_t *instance)
137{
138 assert(instance);
139 regs_t *registers = instance->registers;
140
141 /* Reset everything, who knows what touched it before us */
142 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
143 async_usleep(10000); /* 10ms according to USB spec */
144 pio_write_16(&registers->usbcmd, 0);
145
146 /* Reset hc, all states and counters */
147 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
148 do { async_usleep(10); }
149 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
150
151 /* Set frame to exactly 1ms */
152 pio_write_8(&registers->sofmod, 64);
153
154 /* Set frame list pointer */
155 const uint32_t pa = addr_to_phys(instance->frame_list);
156 pio_write_32(&registers->flbaseadd, pa);
157
158 if (instance->hw_interrupts) {
159 /* Enable all interrupts, but resume interrupt */
160 pio_write_16(&instance->registers->usbintr,
161 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
162 }
163
164 uint16_t status = pio_read_16(&registers->usbcmd);
165 if (status != 0)
166 usb_log_warning("Previous command value: %x.\n", status);
167
168 /* Start the hc with large(64B) packet FSBR */
169 pio_write_16(&registers->usbcmd,
170 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
171}
172/*----------------------------------------------------------------------------*/
173/** Initialize UHCI hc memory structures.
174 *
175 * @param[in] instance UHCI structure to use.
176 * @return Error code
177 * @note Should be called only once on any structure.
178 *
179 * Structures:
180 * - interrupt code (I/O addressses are customized per instance)
181 * - transfer lists (queue heads need to be accessible by the hw)
182 * - frame list page (needs to be one UHCI hw accessible 4K page)
183 */
184int uhci_hc_init_mem_structures(uhci_hc_t *instance)
185{
186 assert(instance);
187#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
188 if (ret != EOK) { \
189 usb_log_error(message); \
190 if (instance->interrupt_code.cmds != NULL) \
191 free(instance->interrupt_code.cmds); \
192 return ret; \
193 } else (void) 0
194
195 /* Init interrupt code */
196 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
197 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
198 CHECK_RET_DEST_CMDS_RETURN(ret,
199 "Failed to allocate interrupt cmds space.\n");
200
201 {
202 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
203 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
204 interrupt_commands[0].addr =
205 (void*)&instance->registers->usbsts;
206 interrupt_commands[1].addr =
207 (void*)&instance->registers->usbsts;
208 instance->interrupt_code.cmdcount =
209 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
210 }
211
212 /* Init transfer lists */
213 ret = uhci_hc_init_transfer_lists(instance);
214 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
215 usb_log_debug("Initialized transfer lists.\n");
216
217 /* Init USB frame list page*/
218 instance->frame_list = get_page();
219 ret = instance ? EOK : ENOMEM;
220 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
221 usb_log_debug("Initialized frame list.\n");
222
223 /* Set all frames to point to the first queue head */
224 const uint32_t queue =
225 instance->transfers_interrupt.queue_head_pa
226 | LINK_POINTER_QUEUE_HEAD_FLAG;
227
228 unsigned i = 0;
229 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
230 instance->frame_list[i] = queue;
231 }
232
233 /* Init device keeper*/
234 device_keeper_init(&instance->device_manager);
235 usb_log_debug("Initialized device manager.\n");
236
237 return EOK;
238#undef CHECK_RET_DEST_CMDS_RETURN
239}
240/*----------------------------------------------------------------------------*/
241/** Initialize UHCI hc transfer lists.
242 *
243 * @param[in] instance UHCI structure to use.
244 * @return Error code
245 * @note Should be called only once on any structure.
246 *
247 * Initializes transfer lists and sets them in one chain to support proper
248 * USB scheduling. Sets pointer table for quick access.
249 */
250int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
251{
252 assert(instance);
253#define CHECK_RET_CLEAR_RETURN(ret, message...) \
254 if (ret != EOK) { \
255 usb_log_error(message); \
256 transfer_list_fini(&instance->transfers_bulk_full); \
257 transfer_list_fini(&instance->transfers_control_full); \
258 transfer_list_fini(&instance->transfers_control_slow); \
259 transfer_list_fini(&instance->transfers_interrupt); \
260 return ret; \
261 } else (void) 0
262
263 /* initialize TODO: check errors */
264 int ret;
265 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
266 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
267
268 ret = transfer_list_init(
269 &instance->transfers_control_full, "CONTROL_FULL");
270 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
271
272 ret = transfer_list_init(
273 &instance->transfers_control_slow, "CONTROL_SLOW");
274 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
275
276 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
277 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
278
279 transfer_list_set_next(&instance->transfers_control_full,
280 &instance->transfers_bulk_full);
281 transfer_list_set_next(&instance->transfers_control_slow,
282 &instance->transfers_control_full);
283 transfer_list_set_next(&instance->transfers_interrupt,
284 &instance->transfers_control_slow);
285
286 /*FSBR*/
287#ifdef FSBR
288 transfer_list_set_next(&instance->transfers_bulk_full,
289 &instance->transfers_control_full);
290#endif
291
292 /* Assign pointers to be used during scheduling */
293 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
294 &instance->transfers_interrupt;
295 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
296 &instance->transfers_interrupt;
297 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
298 &instance->transfers_control_full;
299 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
300 &instance->transfers_control_slow;
301 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
302 &instance->transfers_bulk_full;
303
304 return EOK;
305#undef CHECK_RET_CLEAR_RETURN
306}
307/*----------------------------------------------------------------------------*/
308/** Schedule batch for execution.
309 *
310 * @param[in] instance UHCI structure to use.
311 * @param[in] batch Transfer batch to schedule.
312 * @return Error code
313 *
314 * Checks for bandwidth availability and appends the batch to the proper queue.
315 */
316int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
317{
318 assert(instance);
319 assert(batch);
320 const int low_speed = (batch->speed == USB_SPEED_LOW);
321 if (!allowed_usb_packet(
322 low_speed, batch->transfer_type, batch->max_packet_size)) {
323 usb_log_warning(
324 "Invalid USB packet specified %s SPEED %d %zu.\n",
325 low_speed ? "LOW" : "FULL" , batch->transfer_type,
326 batch->max_packet_size);
327 return ENOTSUP;
328 }
329 /* TODO: check available bandwidth here */
330
331 transfer_list_t *list =
332 instance->transfers[batch->speed][batch->transfer_type];
333 assert(list);
334 transfer_list_add_batch(list, batch);
335
336 return EOK;
337}
338/*----------------------------------------------------------------------------*/
339/** Take action based on the interrupt cause.
340 *
341 * @param[in] instance UHCI structure to use.
342 * @param[in] status Value of the status register at the time of interrupt.
343 *
344 * Interrupt might indicate:
345 * - transaction completed, either by triggering IOC, SPD, or an error
346 * - some kind of device error
347 * - resume from suspend state (not implemented)
348 */
349void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
350{
351 assert(instance);
352 /* TODO: Resume interrupts are not supported */
353 /* Lower 2 bits are transaction error and transaction complete */
354 if (status & 0x3) {
355 transfer_list_remove_finished(&instance->transfers_interrupt);
356 transfer_list_remove_finished(&instance->transfers_control_slow);
357 transfer_list_remove_finished(&instance->transfers_control_full);
358 transfer_list_remove_finished(&instance->transfers_bulk_full);
359 }
360 /* bits 4 and 5 indicate hc error */
361 if (status & 0x18) {
362 transfer_list_abort_all(&instance->transfers_interrupt);
363 transfer_list_abort_all(&instance->transfers_control_slow);
364 transfer_list_abort_all(&instance->transfers_control_full);
365 transfer_list_abort_all(&instance->transfers_bulk_full);
366 /* reinitialize hw, this triggers virtual disconnect*/
367 uhci_hc_init_hw(instance);
368 }
369}
370/*----------------------------------------------------------------------------*/
371/** Polling function, emulates interrupts.
372 *
373 * @param[in] arg UHCI hc structure to use.
374 * @return EOK (should never return)
375 */
376int uhci_hc_interrupt_emulator(void* arg)
377{
378 usb_log_debug("Started interrupt emulator.\n");
379 uhci_hc_t *instance = (uhci_hc_t*)arg;
380 assert(instance);
381
382 while (1) {
383 /* read and ack interrupts */
384 uint16_t status = pio_read_16(&instance->registers->usbsts);
385 pio_write_16(&instance->registers->usbsts, 0x1f);
386 if (status != 0)
387 usb_log_debug2("UHCI status: %x.\n", status);
388 uhci_hc_interrupt(instance, status);
389 async_usleep(UHCI_CLEANER_TIMEOUT);
390 }
391 return EOK;
392}
393/*---------------------------------------------------------------------------*/
394/** Debug function, checks consistency of memory structures.
395 *
396 * @param[in] arg UHCI structure to use.
397 * @return EOK (should never return)
398 */
399int uhci_hc_debug_checker(void *arg)
400{
401 uhci_hc_t *instance = (uhci_hc_t*)arg;
402 assert(instance);
403
404#define QH(queue) \
405 instance->transfers_##queue.queue_head
406
407 while (1) {
408 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
409 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
410 const uint16_t intr =
411 pio_read_16(&instance->registers->usbintr);
412
413 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
414 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
415 cmd, sts, intr);
416 }
417
418 uintptr_t frame_list =
419 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
420 if (frame_list != addr_to_phys(instance->frame_list)) {
421 usb_log_debug("Framelist address: %p vs. %p.\n",
422 frame_list, addr_to_phys(instance->frame_list));
423 }
424
425 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
426
427 uintptr_t expected_pa = instance->frame_list[frnum]
428 & LINK_POINTER_ADDRESS_MASK;
429 uintptr_t real_pa = addr_to_phys(QH(interrupt));
430 if (expected_pa != real_pa) {
431 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
432 expected_pa, frnum, real_pa);
433 }
434
435 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
436 real_pa = addr_to_phys(QH(control_slow));
437 if (expected_pa != real_pa) {
438 usb_log_debug("Control Slow QH: %p vs. %p.\n",
439 expected_pa, real_pa);
440 }
441
442 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
443 real_pa = addr_to_phys(QH(control_full));
444 if (expected_pa != real_pa) {
445 usb_log_debug("Control Full QH: %p vs. %p.\n",
446 expected_pa, real_pa);
447 }
448
449 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
450 real_pa = addr_to_phys(QH(bulk_full));
451 if (expected_pa != real_pa ) {
452 usb_log_debug("Bulk QH: %p vs. %p.\n",
453 expected_pa, real_pa);
454 }
455 async_usleep(UHCI_DEBUGER_TIMEOUT);
456 }
457 return EOK;
458#undef QH
459}
460/*----------------------------------------------------------------------------*/
461/** Check transfer packets, for USB validity
462 *
463 * @param[in] low_speed Transfer speed.
464 * @param[in] transfer Transer type
465 * @param[in] size Maximum size of used packets
466 * @return True if transaction is allowed by USB specs, false otherwise
467 */
468bool allowed_usb_packet(
469 bool low_speed, usb_transfer_type_t transfer, size_t size)
470{
471 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
472 switch(transfer)
473 {
474 case USB_TRANSFER_ISOCHRONOUS:
475 return (!low_speed && size < 1024);
476 case USB_TRANSFER_INTERRUPT:
477 return size <= (low_speed ? 8 : 64);
478 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
479 return (size <= (low_speed ? 8 : 64));
480 case USB_TRANSFER_BULK: /* device specifies its own max size */
481 return (!low_speed && size <= 64);
482 }
483 return false;
484}
485/**
486 * @}
487 */
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