source: mainline/uspace/drv/uhci-hcd/uhci_hc.c@ a963a68

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a963a68 was a963a68, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Hw error handling.
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File size: 15.8 KB
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1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "uhci_hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
63static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
64static void uhci_hc_init_hw(uhci_hc_t *instance);
65
66static int uhci_hc_interrupt_emulator(void *arg);
67static int uhci_hc_debug_checker(void *arg);
68
69static bool allowed_usb_packet(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71/*----------------------------------------------------------------------------*/
72/** Initialize UHCI hcd driver structure
73 *
74 * @param[in] instance Memory place to initialize.
75 * @param[in] fun DDF function.
76 * @param[in] regs Address of I/O control registers.
77 * @param[in] size Size of I/O control registers.
78 * @return Error code.
79 * @note Should be called only once on any structure.
80 *
81 * Initializes memory structures, starts up hw, and launches debugger and
82 * interrupt fibrils.
83 */
84int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun,
85 void *regs, size_t reg_size, bool interrupts)
86{
87 assert(reg_size >= sizeof(regs_t));
88 int ret;
89
90#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
91 if (ret != EOK) { \
92 usb_log_error(message); \
93 if (instance->ddf_instance) \
94 ddf_fun_destroy(instance->ddf_instance); \
95 return ret; \
96 } else (void) 0
97
98 instance->hw_interrupts = interrupts;
99 /* Setup UHCI function. */
100 instance->ddf_instance = fun;
101
102 /* allow access to hc control registers */
103 regs_t *io;
104 ret = pio_enable(regs, reg_size, (void**)&io);
105 CHECK_RET_DEST_FUN_RETURN(ret,
106 "Failed(%d) to gain access to registers at %p: %s.\n",
107 ret, str_error(ret), io);
108 instance->registers = io;
109 usb_log_debug("Device registers at %p(%u) accessible.\n",
110 io, reg_size);
111
112 ret = uhci_hc_init_mem_structures(instance);
113 CHECK_RET_DEST_FUN_RETURN(ret,
114 "Failed to initialize UHCI memory structures.\n");
115
116 uhci_hc_init_hw(instance);
117 if (!interrupts) {
118 instance->cleaner =
119 fibril_create(uhci_hc_interrupt_emulator, instance);
120 fibril_add_ready(instance->cleaner);
121 }
122
123 instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
124 fibril_add_ready(instance->debug_checker);
125
126 usb_log_info("Started UHCI driver.\n");
127 return EOK;
128#undef CHECK_RET_DEST_FUN_RETURN
129}
130/*----------------------------------------------------------------------------*/
131/** Initialize UHCI hc hw resources.
132 *
133 * @param[in] instance UHCI structure to use.
134 * For magic values see UHCI Design Guide
135 */
136void uhci_hc_init_hw(uhci_hc_t *instance)
137{
138 assert(instance);
139 regs_t *registers = instance->registers;
140
141 /* Reset everything, who knows what touched it before us */
142 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
143 async_usleep(10000); /* 10ms according to USB spec */
144 pio_write_16(&registers->usbcmd, 0);
145
146 /* Reset hc, all states and counters */
147 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
148 do { async_usleep(10); }
149 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
150
151 /* Set framelist pointer */
152 const uint32_t pa = addr_to_phys(instance->frame_list);
153 pio_write_32(&registers->flbaseadd, pa);
154
155 if (instance->hw_interrupts) {
156 /* Enable all interrupts, but resume interrupt */
157 pio_write_16(&instance->registers->usbintr,
158 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
159 }
160
161 uint16_t status = pio_read_16(&registers->usbcmd);
162 if (status != 0)
163 usb_log_warning("Previous command value: %x.\n", status);
164
165 /* Start the hc with large(64B) packet FSBR */
166 pio_write_16(&registers->usbcmd,
167 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
168}
169/*----------------------------------------------------------------------------*/
170/** Initialize UHCI hc memory structures.
171 *
172 * @param[in] instance UHCI structure to use.
173 * @return Error code
174 * @note Should be called only once on any structure.
175 *
176 * Structures:
177 * - interrupt code (I/O addressses are customized per instance)
178 * - transfer lists (queue heads need to be accessible by the hw)
179 * - frame list page (needs to be one UHCI hw accessible 4K page)
180 */
181int uhci_hc_init_mem_structures(uhci_hc_t *instance)
182{
183 assert(instance);
184#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
185 if (ret != EOK) { \
186 usb_log_error(message); \
187 if (instance->interrupt_code.cmds != NULL) \
188 free(instance->interrupt_code.cmds); \
189 return ret; \
190 } else (void) 0
191
192 /* Init interrupt code */
193 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
194 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
195 CHECK_RET_DEST_CMDS_RETURN(ret,
196 "Failed to allocate interrupt cmds space.\n");
197
198 {
199 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
200 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
201 interrupt_commands[0].addr =
202 (void*)&instance->registers->usbsts;
203 interrupt_commands[1].addr =
204 (void*)&instance->registers->usbsts;
205 instance->interrupt_code.cmdcount =
206 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
207 }
208
209 /* Init transfer lists */
210 ret = uhci_hc_init_transfer_lists(instance);
211 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
212 usb_log_debug("Initialized transfer lists.\n");
213
214 /* Init USB frame list page*/
215 instance->frame_list = get_page();
216 ret = instance ? EOK : ENOMEM;
217 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
218 usb_log_debug("Initialized frame list.\n");
219
220 /* Set all frames to point to the first queue head */
221 const uint32_t queue =
222 instance->transfers_interrupt.queue_head_pa
223 | LINK_POINTER_QUEUE_HEAD_FLAG;
224
225 unsigned i = 0;
226 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
227 instance->frame_list[i] = queue;
228 }
229
230 /* Init device keeper*/
231 device_keeper_init(&instance->device_manager);
232 usb_log_debug("Initialized device manager.\n");
233
234 return EOK;
235#undef CHECK_RET_DEST_CMDS_RETURN
236}
237/*----------------------------------------------------------------------------*/
238/** Initialize UHCI hc transfer lists.
239 *
240 * @param[in] instance UHCI structure to use.
241 * @return Error code
242 * @note Should be called only once on any structure.
243 *
244 * Initializes transfer lists and sets them in one chain to support proper
245 * USB scheduling. Sets pointer table for quick access.
246 */
247int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
248{
249 assert(instance);
250#define CHECK_RET_CLEAR_RETURN(ret, message...) \
251 if (ret != EOK) { \
252 usb_log_error(message); \
253 transfer_list_fini(&instance->transfers_bulk_full); \
254 transfer_list_fini(&instance->transfers_control_full); \
255 transfer_list_fini(&instance->transfers_control_slow); \
256 transfer_list_fini(&instance->transfers_interrupt); \
257 return ret; \
258 } else (void) 0
259
260 /* initialize TODO: check errors */
261 int ret;
262 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
263 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
264
265 ret = transfer_list_init(
266 &instance->transfers_control_full, "CONTROL_FULL");
267 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
268
269 ret = transfer_list_init(
270 &instance->transfers_control_slow, "CONTROL_SLOW");
271 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
272
273 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
274 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
275
276 transfer_list_set_next(&instance->transfers_control_full,
277 &instance->transfers_bulk_full);
278 transfer_list_set_next(&instance->transfers_control_slow,
279 &instance->transfers_control_full);
280 transfer_list_set_next(&instance->transfers_interrupt,
281 &instance->transfers_control_slow);
282
283 /*FSBR*/
284#ifdef FSBR
285 transfer_list_set_next(&instance->transfers_bulk_full,
286 &instance->transfers_control_full);
287#endif
288
289 /* Assign pointers to be used during scheduling */
290 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
291 &instance->transfers_interrupt;
292 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
293 &instance->transfers_interrupt;
294 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
295 &instance->transfers_control_full;
296 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
297 &instance->transfers_control_slow;
298 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
299 &instance->transfers_bulk_full;
300
301 return EOK;
302#undef CHECK_RET_CLEAR_RETURN
303}
304/*----------------------------------------------------------------------------*/
305/** Schedule batch for execution.
306 *
307 * @param[in] instance UHCI structure to use.
308 * @param[in] batch Transfer batch to schedule.
309 * @return Error code
310 *
311 * Checks for bandwidth availability and appends the batch to the proper queue.
312 */
313int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
314{
315 assert(instance);
316 assert(batch);
317 const int low_speed = (batch->speed == USB_SPEED_LOW);
318 if (!allowed_usb_packet(
319 low_speed, batch->transfer_type, batch->max_packet_size)) {
320 usb_log_warning(
321 "Invalid USB packet specified %s SPEED %d %zu.\n",
322 low_speed ? "LOW" : "FULL" , batch->transfer_type,
323 batch->max_packet_size);
324 return ENOTSUP;
325 }
326 /* TODO: check available bandwidth here */
327
328 transfer_list_t *list =
329 instance->transfers[batch->speed][batch->transfer_type];
330 assert(list);
331 transfer_list_add_batch(list, batch);
332
333 return EOK;
334}
335/*----------------------------------------------------------------------------*/
336/** Take action based on the interrupt cause.
337 *
338 * @param[in] instance UHCI structure to use.
339 * @param[in] status Value of the status register at the time of interrupt.
340 *
341 * Interrupt might indicate:
342 * - transaction completed, either by triggering IOC, SPD, or an error
343 * - some kind of device error
344 * - resume from suspend state (not implemented)
345 */
346void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
347{
348 assert(instance);
349 /* TODO: Resume interrupts are not supported */
350 /* Lower 2 bits are transaction error and transaction complete */
351 if (status & 0x3) {
352 transfer_list_remove_finished(&instance->transfers_interrupt);
353 transfer_list_remove_finished(&instance->transfers_control_slow);
354 transfer_list_remove_finished(&instance->transfers_control_full);
355 transfer_list_remove_finished(&instance->transfers_bulk_full);
356 }
357 /* bits 4 and 5 indicate hc error */
358 if (status & 0x18) {
359 transfer_list_abort_all(&instance->transfers_interrupt);
360 transfer_list_abort_all(&instance->transfers_control_slow);
361 transfer_list_abort_all(&instance->transfers_control_full);
362 transfer_list_abort_all(&instance->transfers_bulk_full);
363 /* reinitialize hw, this triggers virtual disconnect*/
364 uhci_hc_init_hw(instance);
365 }
366}
367/*----------------------------------------------------------------------------*/
368/** Polling function, emulates interrupts.
369 *
370 * @param[in] arg UHCI hc structure to use.
371 * @return EOK (should never return)
372 */
373int uhci_hc_interrupt_emulator(void* arg)
374{
375 usb_log_debug("Started interrupt emulator.\n");
376 uhci_hc_t *instance = (uhci_hc_t*)arg;
377 assert(instance);
378
379 while (1) {
380 /* read and ack interrupts */
381 uint16_t status = pio_read_16(&instance->registers->usbsts);
382 pio_write_16(&instance->registers->usbsts, 0x1f);
383 if (status != 0)
384 usb_log_debug2("UHCI status: %x.\n", status);
385 uhci_hc_interrupt(instance, status);
386 async_usleep(UHCI_CLEANER_TIMEOUT);
387 }
388 return EOK;
389}
390/*---------------------------------------------------------------------------*/
391/** Debug function, checks consistency of memory structures.
392 *
393 * @param[in] arg UHCI structure to use.
394 * @return EOK (should never return)
395 */
396int uhci_hc_debug_checker(void *arg)
397{
398 uhci_hc_t *instance = (uhci_hc_t*)arg;
399 assert(instance);
400
401#define QH(queue) \
402 instance->transfers_##queue.queue_head
403
404 while (1) {
405 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
406 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
407 const uint16_t intr =
408 pio_read_16(&instance->registers->usbintr);
409
410 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
411 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
412 cmd, sts, intr);
413 }
414
415 uintptr_t frame_list =
416 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
417 if (frame_list != addr_to_phys(instance->frame_list)) {
418 usb_log_debug("Framelist address: %p vs. %p.\n",
419 frame_list, addr_to_phys(instance->frame_list));
420 }
421
422 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
423
424 uintptr_t expected_pa = instance->frame_list[frnum]
425 & LINK_POINTER_ADDRESS_MASK;
426 uintptr_t real_pa = addr_to_phys(QH(interrupt));
427 if (expected_pa != real_pa) {
428 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
429 expected_pa, frnum, real_pa);
430 }
431
432 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
433 real_pa = addr_to_phys(QH(control_slow));
434 if (expected_pa != real_pa) {
435 usb_log_debug("Control Slow QH: %p vs. %p.\n",
436 expected_pa, real_pa);
437 }
438
439 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
440 real_pa = addr_to_phys(QH(control_full));
441 if (expected_pa != real_pa) {
442 usb_log_debug("Control Full QH: %p vs. %p.\n",
443 expected_pa, real_pa);
444 }
445
446 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
447 real_pa = addr_to_phys(QH(bulk_full));
448 if (expected_pa != real_pa ) {
449 usb_log_debug("Bulk QH: %p vs. %p.\n",
450 expected_pa, real_pa);
451 }
452 async_usleep(UHCI_DEBUGER_TIMEOUT);
453 }
454 return EOK;
455#undef QH
456}
457/*----------------------------------------------------------------------------*/
458/** Check transfer packets, for USB validity
459 *
460 * @param[in] low_speed Transfer speed.
461 * @param[in] transfer Transer type
462 * @param[in] size Maximum size of used packets
463 * @return True if transaction is allowed by USB specs, false otherwise
464 */
465bool allowed_usb_packet(
466 bool low_speed, usb_transfer_type_t transfer, size_t size)
467{
468 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
469 switch(transfer)
470 {
471 case USB_TRANSFER_ISOCHRONOUS:
472 return (!low_speed && size < 1024);
473 case USB_TRANSFER_INTERRUPT:
474 return size <= (low_speed ? 8 : 64);
475 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
476 return (size <= (low_speed ? 8 : 64));
477 case USB_TRANSFER_BULK: /* device specifies its own max size */
478 return (!low_speed && size <= 64);
479 }
480 return false;
481}
482/**
483 * @}
484 */
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