| [9351353] | 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| [17ceb72] | 28 | /** @addtogroup drvusbuhcihc
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| [9351353] | 29 | * @{
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| 30 | */
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| 31 | /** @file
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| [17ceb72] | 32 | * @brief UHCI Host controller driver routines
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| [9351353] | 33 | */
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| 34 | #include <errno.h>
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| 35 | #include <str_error.h>
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| 36 | #include <adt/list.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include <usb/debug.h>
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| 40 | #include <usb/usb.h>
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| 41 | #include <usb/ddfiface.h>
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| 42 | #include <usb_iface.h>
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| 43 |
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| 44 | #include "uhci_hc.h"
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| 45 |
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| 46 | static irq_cmd_t uhci_cmds[] = {
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| 47 | {
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| 48 | .cmd = CMD_PIO_READ_16,
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| 49 | .addr = NULL, /* patched for every instance */
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| 50 | .dstarg = 1
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| 51 | },
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| 52 | {
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| 53 | .cmd = CMD_PIO_WRITE_16,
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| 54 | .addr = NULL, /* pathed for every instance */
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| 55 | .value = 0x1f
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| 56 | },
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| 57 | {
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| 58 | .cmd = CMD_ACCEPT
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| 59 | }
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| 60 | };
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| 61 | /*----------------------------------------------------------------------------*/
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| [a9f91cd] | 62 | static int uhci_hc_init_transfer_lists(uhci_hc_t *instance);
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| 63 | static int uhci_hc_init_mem_structures(uhci_hc_t *instance);
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| 64 | static void uhci_hc_init_hw(uhci_hc_t *instance);
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| [9351353] | 65 |
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| [a9f91cd] | 66 | static int uhci_hc_interrupt_emulator(void *arg);
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| 67 | static int uhci_hc_debug_checker(void *arg);
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| [9351353] | 68 |
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| 69 | static bool allowed_usb_packet(
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| 70 | bool low_speed, usb_transfer_type_t transfer, size_t size);
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| 71 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 72 | /** Initialize UHCI hcd driver structure
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| [9351353] | 73 | *
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| 74 | * @param[in] instance Memory place to initialize.
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| 75 | * @param[in] fun DDF function.
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| 76 | * @param[in] regs Address of I/O control registers.
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| 77 | * @param[in] size Size of I/O control registers.
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| 78 | * @return Error code.
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| 79 | * @note Should be called only once on any structure.
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| [17ceb72] | 80 | *
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| 81 | * Initializes memory structures, starts up hw, and launches debugger and
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| 82 | * interrupt fibrils.
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| [9351353] | 83 | */
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| [ff34e5a] | 84 | int uhci_hc_init(uhci_hc_t *instance, ddf_fun_t *fun,
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| 85 | void *regs, size_t reg_size, bool interrupts)
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| [9351353] | 86 | {
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| 87 | assert(reg_size >= sizeof(regs_t));
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| 88 | int ret;
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| 89 |
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| 90 | #define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
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| 91 | if (ret != EOK) { \
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| 92 | usb_log_error(message); \
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| 93 | if (instance->ddf_instance) \
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| 94 | ddf_fun_destroy(instance->ddf_instance); \
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| 95 | return ret; \
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| 96 | } else (void) 0
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| 97 |
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| [ff34e5a] | 98 | instance->hw_interrupts = interrupts;
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| [9351353] | 99 | /* Setup UHCI function. */
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| 100 | instance->ddf_instance = fun;
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| 101 |
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| 102 | /* allow access to hc control registers */
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| 103 | regs_t *io;
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| 104 | ret = pio_enable(regs, reg_size, (void**)&io);
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| 105 | CHECK_RET_DEST_FUN_RETURN(ret,
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| 106 | "Failed(%d) to gain access to registers at %p: %s.\n",
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| 107 | ret, str_error(ret), io);
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| 108 | instance->registers = io;
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| 109 | usb_log_debug("Device registers at %p(%u) accessible.\n",
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| 110 | io, reg_size);
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| 111 |
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| [a9f91cd] | 112 | ret = uhci_hc_init_mem_structures(instance);
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| [9351353] | 113 | CHECK_RET_DEST_FUN_RETURN(ret,
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| 114 | "Failed to initialize UHCI memory structures.\n");
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| 115 |
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| [a9f91cd] | 116 | uhci_hc_init_hw(instance);
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| [ff34e5a] | 117 | if (!interrupts) {
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| 118 | instance->cleaner =
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| 119 | fibril_create(uhci_hc_interrupt_emulator, instance);
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| 120 | fibril_add_ready(instance->cleaner);
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| 121 | }
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| [9351353] | 122 |
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| [a9f91cd] | 123 | instance->debug_checker = fibril_create(uhci_hc_debug_checker, instance);
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| [9351353] | 124 | fibril_add_ready(instance->debug_checker);
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| 125 |
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| 126 | usb_log_info("Started UHCI driver.\n");
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| 127 | return EOK;
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| 128 | #undef CHECK_RET_DEST_FUN_RETURN
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| 129 | }
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| 130 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 131 | /** Initialize UHCI hc hw resources.
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| [9351353] | 132 | *
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| 133 | * @param[in] instance UHCI structure to use.
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| [17ceb72] | 134 | * For magic values see UHCI Design Guide
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| [9351353] | 135 | */
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| [a9f91cd] | 136 | void uhci_hc_init_hw(uhci_hc_t *instance)
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| [9351353] | 137 | {
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| 138 | assert(instance);
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| 139 | regs_t *registers = instance->registers;
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| 140 |
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| 141 | /* Reset everything, who knows what touched it before us */
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| 142 | pio_write_16(®isters->usbcmd, UHCI_CMD_GLOBAL_RESET);
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| 143 | async_usleep(10000); /* 10ms according to USB spec */
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| 144 | pio_write_16(®isters->usbcmd, 0);
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| 145 |
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| 146 | /* Reset hc, all states and counters */
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| 147 | pio_write_16(®isters->usbcmd, UHCI_CMD_HCRESET);
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| 148 | do { async_usleep(10); }
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| 149 | while ((pio_read_16(®isters->usbcmd) & UHCI_CMD_HCRESET) != 0);
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| 150 |
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| [eb2a48a] | 151 | /* Set frame to exactly 1ms */
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| 152 | pio_write_8(®isters->sofmod, 64);
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| 153 |
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| 154 | /* Set frame list pointer */
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| [9351353] | 155 | const uint32_t pa = addr_to_phys(instance->frame_list);
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| 156 | pio_write_32(®isters->flbaseadd, pa);
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| 157 |
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| [ff34e5a] | 158 | if (instance->hw_interrupts) {
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| 159 | /* Enable all interrupts, but resume interrupt */
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| 160 | pio_write_16(&instance->registers->usbintr,
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| 161 | UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
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| 162 | }
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| [9351353] | 163 |
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| 164 | uint16_t status = pio_read_16(®isters->usbcmd);
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| 165 | if (status != 0)
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| 166 | usb_log_warning("Previous command value: %x.\n", status);
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| 167 |
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| 168 | /* Start the hc with large(64B) packet FSBR */
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| 169 | pio_write_16(®isters->usbcmd,
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| 170 | UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
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| 171 | }
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| 172 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 173 | /** Initialize UHCI hc memory structures.
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| [9351353] | 174 | *
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| 175 | * @param[in] instance UHCI structure to use.
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| 176 | * @return Error code
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| 177 | * @note Should be called only once on any structure.
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| [17ceb72] | 178 | *
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| 179 | * Structures:
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| 180 | * - interrupt code (I/O addressses are customized per instance)
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| 181 | * - transfer lists (queue heads need to be accessible by the hw)
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| 182 | * - frame list page (needs to be one UHCI hw accessible 4K page)
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| [9351353] | 183 | */
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| [a9f91cd] | 184 | int uhci_hc_init_mem_structures(uhci_hc_t *instance)
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| [9351353] | 185 | {
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| 186 | assert(instance);
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| 187 | #define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
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| 188 | if (ret != EOK) { \
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| 189 | usb_log_error(message); \
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| 190 | if (instance->interrupt_code.cmds != NULL) \
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| 191 | free(instance->interrupt_code.cmds); \
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| 192 | return ret; \
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| 193 | } else (void) 0
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| 194 |
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| 195 | /* Init interrupt code */
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| 196 | instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
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| 197 | int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
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| 198 | CHECK_RET_DEST_CMDS_RETURN(ret,
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| 199 | "Failed to allocate interrupt cmds space.\n");
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| 200 |
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| 201 | {
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| 202 | irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
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| 203 | memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
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| 204 | interrupt_commands[0].addr =
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| 205 | (void*)&instance->registers->usbsts;
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| 206 | interrupt_commands[1].addr =
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| 207 | (void*)&instance->registers->usbsts;
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| 208 | instance->interrupt_code.cmdcount =
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| 209 | sizeof(uhci_cmds) / sizeof(irq_cmd_t);
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| 210 | }
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| 211 |
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| 212 | /* Init transfer lists */
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| [a9f91cd] | 213 | ret = uhci_hc_init_transfer_lists(instance);
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| [9351353] | 214 | CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
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| 215 | usb_log_debug("Initialized transfer lists.\n");
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| 216 |
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| 217 | /* Init USB frame list page*/
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| 218 | instance->frame_list = get_page();
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| 219 | ret = instance ? EOK : ENOMEM;
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| 220 | CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
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| 221 | usb_log_debug("Initialized frame list.\n");
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| 222 |
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| 223 | /* Set all frames to point to the first queue head */
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| 224 | const uint32_t queue =
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| 225 | instance->transfers_interrupt.queue_head_pa
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| 226 | | LINK_POINTER_QUEUE_HEAD_FLAG;
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| 227 |
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| 228 | unsigned i = 0;
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| 229 | for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
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| 230 | instance->frame_list[i] = queue;
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| 231 | }
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| 232 |
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| 233 | /* Init device keeper*/
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| 234 | device_keeper_init(&instance->device_manager);
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| 235 | usb_log_debug("Initialized device manager.\n");
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| 236 |
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| 237 | return EOK;
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| 238 | #undef CHECK_RET_DEST_CMDS_RETURN
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| 239 | }
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| 240 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 241 | /** Initialize UHCI hc transfer lists.
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| [9351353] | 242 | *
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| 243 | * @param[in] instance UHCI structure to use.
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| 244 | * @return Error code
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| 245 | * @note Should be called only once on any structure.
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| [17ceb72] | 246 | *
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| 247 | * Initializes transfer lists and sets them in one chain to support proper
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| 248 | * USB scheduling. Sets pointer table for quick access.
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| [9351353] | 249 | */
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| [a9f91cd] | 250 | int uhci_hc_init_transfer_lists(uhci_hc_t *instance)
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| [9351353] | 251 | {
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| 252 | assert(instance);
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| 253 | #define CHECK_RET_CLEAR_RETURN(ret, message...) \
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| 254 | if (ret != EOK) { \
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| 255 | usb_log_error(message); \
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| 256 | transfer_list_fini(&instance->transfers_bulk_full); \
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| 257 | transfer_list_fini(&instance->transfers_control_full); \
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| 258 | transfer_list_fini(&instance->transfers_control_slow); \
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| 259 | transfer_list_fini(&instance->transfers_interrupt); \
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| 260 | return ret; \
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| 261 | } else (void) 0
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| 262 |
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| 263 | /* initialize TODO: check errors */
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| 264 | int ret;
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| 265 | ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
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| 266 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
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| 267 |
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| 268 | ret = transfer_list_init(
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| 269 | &instance->transfers_control_full, "CONTROL_FULL");
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| 270 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
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| 271 |
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| 272 | ret = transfer_list_init(
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| 273 | &instance->transfers_control_slow, "CONTROL_SLOW");
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| 274 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
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| 275 |
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| 276 | ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
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| 277 | CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
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| 278 |
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| 279 | transfer_list_set_next(&instance->transfers_control_full,
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| 280 | &instance->transfers_bulk_full);
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| 281 | transfer_list_set_next(&instance->transfers_control_slow,
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| 282 | &instance->transfers_control_full);
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| 283 | transfer_list_set_next(&instance->transfers_interrupt,
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| 284 | &instance->transfers_control_slow);
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| 285 |
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| 286 | /*FSBR*/
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| 287 | #ifdef FSBR
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| 288 | transfer_list_set_next(&instance->transfers_bulk_full,
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| 289 | &instance->transfers_control_full);
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| 290 | #endif
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| 291 |
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| 292 | /* Assign pointers to be used during scheduling */
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| 293 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
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| 294 | &instance->transfers_interrupt;
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| 295 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
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| 296 | &instance->transfers_interrupt;
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| 297 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
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| 298 | &instance->transfers_control_full;
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| 299 | instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
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| 300 | &instance->transfers_control_slow;
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| 301 | instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
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| 302 | &instance->transfers_bulk_full;
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| 303 |
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| 304 | return EOK;
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| 305 | #undef CHECK_RET_CLEAR_RETURN
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| 306 | }
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| 307 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 308 | /** Schedule batch for execution.
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| [9351353] | 309 | *
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| 310 | * @param[in] instance UHCI structure to use.
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| 311 | * @param[in] batch Transfer batch to schedule.
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| 312 | * @return Error code
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| [17ceb72] | 313 | *
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| 314 | * Checks for bandwidth availability and appends the batch to the proper queue.
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| [9351353] | 315 | */
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| [a9f91cd] | 316 | int uhci_hc_schedule(uhci_hc_t *instance, batch_t *batch)
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| [9351353] | 317 | {
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| 318 | assert(instance);
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| 319 | assert(batch);
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| 320 | const int low_speed = (batch->speed == USB_SPEED_LOW);
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| 321 | if (!allowed_usb_packet(
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| 322 | low_speed, batch->transfer_type, batch->max_packet_size)) {
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| 323 | usb_log_warning(
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| 324 | "Invalid USB packet specified %s SPEED %d %zu.\n",
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| 325 | low_speed ? "LOW" : "FULL" , batch->transfer_type,
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| 326 | batch->max_packet_size);
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| 327 | return ENOTSUP;
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| 328 | }
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| [17ceb72] | 329 | /* TODO: check available bandwidth here */
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| [9351353] | 330 |
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| 331 | transfer_list_t *list =
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| 332 | instance->transfers[batch->speed][batch->transfer_type];
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| 333 | assert(list);
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| 334 | transfer_list_add_batch(list, batch);
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| 335 |
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| 336 | return EOK;
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| 337 | }
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| 338 | /*----------------------------------------------------------------------------*/
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| [17ceb72] | 339 | /** Take action based on the interrupt cause.
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| [9351353] | 340 | *
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| 341 | * @param[in] instance UHCI structure to use.
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| [17ceb72] | 342 | * @param[in] status Value of the status register at the time of interrupt.
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| 343 | *
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| 344 | * Interrupt might indicate:
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| 345 | * - transaction completed, either by triggering IOC, SPD, or an error
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| 346 | * - some kind of device error
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| 347 | * - resume from suspend state (not implemented)
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| [9351353] | 348 | */
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| [a9f91cd] | 349 | void uhci_hc_interrupt(uhci_hc_t *instance, uint16_t status)
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| [9351353] | 350 | {
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| 351 | assert(instance);
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| [a963a68] | 352 | /* TODO: Resume interrupts are not supported */
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| [9351353] | 353 | /* Lower 2 bits are transaction error and transaction complete */
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| 354 | if (status & 0x3) {
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| 355 | transfer_list_remove_finished(&instance->transfers_interrupt);
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| 356 | transfer_list_remove_finished(&instance->transfers_control_slow);
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| 357 | transfer_list_remove_finished(&instance->transfers_control_full);
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| 358 | transfer_list_remove_finished(&instance->transfers_bulk_full);
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| 359 | }
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| [a963a68] | 360 | /* bits 4 and 5 indicate hc error */
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| 361 | if (status & 0x18) {
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| 362 | transfer_list_abort_all(&instance->transfers_interrupt);
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| 363 | transfer_list_abort_all(&instance->transfers_control_slow);
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| 364 | transfer_list_abort_all(&instance->transfers_control_full);
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| 365 | transfer_list_abort_all(&instance->transfers_bulk_full);
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| 366 | /* reinitialize hw, this triggers virtual disconnect*/
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| 367 | uhci_hc_init_hw(instance);
|
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| 368 | }
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| [9351353] | 369 | }
|
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| 370 | /*----------------------------------------------------------------------------*/
|
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| 371 | /** Polling function, emulates interrupts.
|
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| 372 | *
|
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| [17ceb72] | 373 | * @param[in] arg UHCI hc structure to use.
|
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| 374 | * @return EOK (should never return)
|
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| [9351353] | 375 | */
|
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| [a9f91cd] | 376 | int uhci_hc_interrupt_emulator(void* arg)
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| [9351353] | 377 | {
|
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| 378 | usb_log_debug("Started interrupt emulator.\n");
|
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| 379 | uhci_hc_t *instance = (uhci_hc_t*)arg;
|
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| 380 | assert(instance);
|
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| 381 |
|
|---|
| 382 | while (1) {
|
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| 383 | /* read and ack interrupts */
|
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| 384 | uint16_t status = pio_read_16(&instance->registers->usbsts);
|
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| 385 | pio_write_16(&instance->registers->usbsts, 0x1f);
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| 386 | if (status != 0)
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| 387 | usb_log_debug2("UHCI status: %x.\n", status);
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| [a9f91cd] | 388 | uhci_hc_interrupt(instance, status);
|
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| [9351353] | 389 | async_usleep(UHCI_CLEANER_TIMEOUT);
|
|---|
| 390 | }
|
|---|
| 391 | return EOK;
|
|---|
| 392 | }
|
|---|
| 393 | /*---------------------------------------------------------------------------*/
|
|---|
| 394 | /** Debug function, checks consistency of memory structures.
|
|---|
| 395 | *
|
|---|
| 396 | * @param[in] arg UHCI structure to use.
|
|---|
| [17ceb72] | 397 | * @return EOK (should never return)
|
|---|
| [9351353] | 398 | */
|
|---|
| [a9f91cd] | 399 | int uhci_hc_debug_checker(void *arg)
|
|---|
| [9351353] | 400 | {
|
|---|
| 401 | uhci_hc_t *instance = (uhci_hc_t*)arg;
|
|---|
| 402 | assert(instance);
|
|---|
| 403 |
|
|---|
| 404 | #define QH(queue) \
|
|---|
| 405 | instance->transfers_##queue.queue_head
|
|---|
| 406 |
|
|---|
| 407 | while (1) {
|
|---|
| 408 | const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
|
|---|
| 409 | const uint16_t sts = pio_read_16(&instance->registers->usbsts);
|
|---|
| 410 | const uint16_t intr =
|
|---|
| 411 | pio_read_16(&instance->registers->usbintr);
|
|---|
| 412 |
|
|---|
| 413 | if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
|
|---|
| 414 | usb_log_debug2("Command: %X Status: %X Intr: %x\n",
|
|---|
| 415 | cmd, sts, intr);
|
|---|
| 416 | }
|
|---|
| 417 |
|
|---|
| 418 | uintptr_t frame_list =
|
|---|
| 419 | pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
|
|---|
| 420 | if (frame_list != addr_to_phys(instance->frame_list)) {
|
|---|
| 421 | usb_log_debug("Framelist address: %p vs. %p.\n",
|
|---|
| 422 | frame_list, addr_to_phys(instance->frame_list));
|
|---|
| 423 | }
|
|---|
| 424 |
|
|---|
| 425 | int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
|
|---|
| 426 |
|
|---|
| 427 | uintptr_t expected_pa = instance->frame_list[frnum]
|
|---|
| 428 | & LINK_POINTER_ADDRESS_MASK;
|
|---|
| 429 | uintptr_t real_pa = addr_to_phys(QH(interrupt));
|
|---|
| 430 | if (expected_pa != real_pa) {
|
|---|
| 431 | usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
|
|---|
| 432 | expected_pa, frnum, real_pa);
|
|---|
| 433 | }
|
|---|
| 434 |
|
|---|
| 435 | expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
|
|---|
| 436 | real_pa = addr_to_phys(QH(control_slow));
|
|---|
| 437 | if (expected_pa != real_pa) {
|
|---|
| 438 | usb_log_debug("Control Slow QH: %p vs. %p.\n",
|
|---|
| 439 | expected_pa, real_pa);
|
|---|
| 440 | }
|
|---|
| 441 |
|
|---|
| 442 | expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
|
|---|
| 443 | real_pa = addr_to_phys(QH(control_full));
|
|---|
| 444 | if (expected_pa != real_pa) {
|
|---|
| 445 | usb_log_debug("Control Full QH: %p vs. %p.\n",
|
|---|
| 446 | expected_pa, real_pa);
|
|---|
| 447 | }
|
|---|
| 448 |
|
|---|
| 449 | expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
|
|---|
| 450 | real_pa = addr_to_phys(QH(bulk_full));
|
|---|
| 451 | if (expected_pa != real_pa ) {
|
|---|
| 452 | usb_log_debug("Bulk QH: %p vs. %p.\n",
|
|---|
| 453 | expected_pa, real_pa);
|
|---|
| 454 | }
|
|---|
| 455 | async_usleep(UHCI_DEBUGER_TIMEOUT);
|
|---|
| 456 | }
|
|---|
| 457 | return EOK;
|
|---|
| 458 | #undef QH
|
|---|
| 459 | }
|
|---|
| 460 | /*----------------------------------------------------------------------------*/
|
|---|
| [17ceb72] | 461 | /** Check transfer packets, for USB validity
|
|---|
| [9351353] | 462 | *
|
|---|
| 463 | * @param[in] low_speed Transfer speed.
|
|---|
| 464 | * @param[in] transfer Transer type
|
|---|
| 465 | * @param[in] size Maximum size of used packets
|
|---|
| [17ceb72] | 466 | * @return True if transaction is allowed by USB specs, false otherwise
|
|---|
| [9351353] | 467 | */
|
|---|
| 468 | bool allowed_usb_packet(
|
|---|
| 469 | bool low_speed, usb_transfer_type_t transfer, size_t size)
|
|---|
| 470 | {
|
|---|
| 471 | /* see USB specification chapter 5.5-5.8 for magic numbers used here */
|
|---|
| 472 | switch(transfer)
|
|---|
| 473 | {
|
|---|
| 474 | case USB_TRANSFER_ISOCHRONOUS:
|
|---|
| 475 | return (!low_speed && size < 1024);
|
|---|
| 476 | case USB_TRANSFER_INTERRUPT:
|
|---|
| 477 | return size <= (low_speed ? 8 : 64);
|
|---|
| 478 | case USB_TRANSFER_CONTROL: /* device specifies its own max size */
|
|---|
| 479 | return (size <= (low_speed ? 8 : 64));
|
|---|
| 480 | case USB_TRANSFER_BULK: /* device specifies its own max size */
|
|---|
| 481 | return (!low_speed && size <= 64);
|
|---|
| 482 | }
|
|---|
| 483 | return false;
|
|---|
| 484 | }
|
|---|
| 485 | /**
|
|---|
| 486 | * @}
|
|---|
| 487 | */
|
|---|