source: mainline/uspace/drv/uhci-hcd/hc.c@ 9d2d444

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9d2d444 was 4c70554, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Refactoring, doxygen

Remove queue_head_pa, it was not really needed as this value was use exactly once for every list.
qh_set_next_qh accepts virtual address and does the conversion internally.
Removed unused qh function
  • Property mode set to 100644
File size: 16.1 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvusbuhcihc
29 * @{
30 */
31/** @file
32 * @brief UHCI Host controller driver routines
33 */
34#include <errno.h>
35#include <str_error.h>
36#include <adt/list.h>
37#include <libarch/ddi.h>
38
39#include <usb/debug.h>
40#include <usb/usb.h>
41#include <usb/ddfiface.h>
42#include <usb_iface.h>
43
44#include "hc.h"
45
46static irq_cmd_t uhci_cmds[] = {
47 {
48 .cmd = CMD_PIO_READ_16,
49 .addr = NULL, /* patched for every instance */
50 .dstarg = 1
51 },
52 {
53 .cmd = CMD_PIO_WRITE_16,
54 .addr = NULL, /* pathed for every instance */
55 .value = 0x1f
56 },
57 {
58 .cmd = CMD_ACCEPT
59 }
60};
61/*----------------------------------------------------------------------------*/
62static int hc_init_transfer_lists(hc_t *instance);
63static int hc_init_mem_structures(hc_t *instance);
64static void hc_init_hw(hc_t *instance);
65
66static int hc_interrupt_emulator(void *arg);
67static int hc_debug_checker(void *arg);
68#if 0
69static bool usb_is_allowed(
70 bool low_speed, usb_transfer_type_t transfer, size_t size);
71#endif
72/*----------------------------------------------------------------------------*/
73/** Initialize UHCI hcd driver structure
74 *
75 * @param[in] instance Memory place to initialize.
76 * @param[in] fun DDF function.
77 * @param[in] regs Address of I/O control registers.
78 * @param[in] size Size of I/O control registers.
79 * @return Error code.
80 * @note Should be called only once on any structure.
81 *
82 * Initializes memory structures, starts up hw, and launches debugger and
83 * interrupt fibrils.
84 */
85int hc_init(hc_t *instance, ddf_fun_t *fun,
86 void *regs, size_t reg_size, bool interrupts)
87{
88 assert(reg_size >= sizeof(regs_t));
89 int ret;
90
91#define CHECK_RET_DEST_FUN_RETURN(ret, message...) \
92 if (ret != EOK) { \
93 usb_log_error(message); \
94 if (instance->ddf_instance) \
95 ddf_fun_destroy(instance->ddf_instance); \
96 return ret; \
97 } else (void) 0
98
99 instance->hw_interrupts = interrupts;
100 instance->hw_failures = 0;
101
102 /* Setup UHCI function. */
103 instance->ddf_instance = fun;
104
105 /* allow access to hc control registers */
106 regs_t *io;
107 ret = pio_enable(regs, reg_size, (void**)&io);
108 CHECK_RET_DEST_FUN_RETURN(ret,
109 "Failed(%d) to gain access to registers at %p: %s.\n",
110 ret, str_error(ret), io);
111 instance->registers = io;
112 usb_log_debug("Device registers at %p(%u) accessible.\n",
113 io, reg_size);
114
115 ret = hc_init_mem_structures(instance);
116 CHECK_RET_DEST_FUN_RETURN(ret,
117 "Failed to initialize UHCI memory structures.\n");
118
119 hc_init_hw(instance);
120 if (!interrupts) {
121 instance->cleaner =
122 fibril_create(hc_interrupt_emulator, instance);
123 fibril_add_ready(instance->cleaner);
124 } else {
125 /* TODO: enable interrupts here */
126 }
127
128 instance->debug_checker =
129 fibril_create(hc_debug_checker, instance);
130// fibril_add_ready(instance->debug_checker);
131
132 return EOK;
133#undef CHECK_RET_DEST_FUN_RETURN
134}
135/*----------------------------------------------------------------------------*/
136/** Initialize UHCI hc hw resources.
137 *
138 * @param[in] instance UHCI structure to use.
139 * For magic values see UHCI Design Guide
140 */
141void hc_init_hw(hc_t *instance)
142{
143 assert(instance);
144 regs_t *registers = instance->registers;
145
146 /* Reset everything, who knows what touched it before us */
147 pio_write_16(&registers->usbcmd, UHCI_CMD_GLOBAL_RESET);
148 async_usleep(10000); /* 10ms according to USB spec */
149 pio_write_16(&registers->usbcmd, 0);
150
151 /* Reset hc, all states and counters */
152 pio_write_16(&registers->usbcmd, UHCI_CMD_HCRESET);
153 do { async_usleep(10); }
154 while ((pio_read_16(&registers->usbcmd) & UHCI_CMD_HCRESET) != 0);
155
156 /* Set frame to exactly 1ms */
157 pio_write_8(&registers->sofmod, 64);
158
159 /* Set frame list pointer */
160 const uint32_t pa = addr_to_phys(instance->frame_list);
161 pio_write_32(&registers->flbaseadd, pa);
162
163 if (instance->hw_interrupts) {
164 /* Enable all interrupts, but resume interrupt */
165 pio_write_16(&instance->registers->usbintr,
166 UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
167 }
168
169 uint16_t status = pio_read_16(&registers->usbcmd);
170 if (status != 0)
171 usb_log_warning("Previous command value: %x.\n", status);
172
173 /* Start the hc with large(64B) packet FSBR */
174 pio_write_16(&registers->usbcmd,
175 UHCI_CMD_RUN_STOP | UHCI_CMD_MAX_PACKET | UHCI_CMD_CONFIGURE);
176}
177/*----------------------------------------------------------------------------*/
178/** Initialize UHCI hc memory structures.
179 *
180 * @param[in] instance UHCI structure to use.
181 * @return Error code
182 * @note Should be called only once on any structure.
183 *
184 * Structures:
185 * - interrupt code (I/O addressses are customized per instance)
186 * - transfer lists (queue heads need to be accessible by the hw)
187 * - frame list page (needs to be one UHCI hw accessible 4K page)
188 */
189int hc_init_mem_structures(hc_t *instance)
190{
191 assert(instance);
192#define CHECK_RET_DEST_CMDS_RETURN(ret, message...) \
193 if (ret != EOK) { \
194 usb_log_error(message); \
195 if (instance->interrupt_code.cmds != NULL) \
196 free(instance->interrupt_code.cmds); \
197 return ret; \
198 } else (void) 0
199
200 /* Init interrupt code */
201 instance->interrupt_code.cmds = malloc(sizeof(uhci_cmds));
202 int ret = (instance->interrupt_code.cmds == NULL) ? ENOMEM : EOK;
203 CHECK_RET_DEST_CMDS_RETURN(ret,
204 "Failed to allocate interrupt cmds space.\n");
205
206 {
207 irq_cmd_t *interrupt_commands = instance->interrupt_code.cmds;
208 memcpy(interrupt_commands, uhci_cmds, sizeof(uhci_cmds));
209 interrupt_commands[0].addr =
210 (void*)&instance->registers->usbsts;
211 interrupt_commands[1].addr =
212 (void*)&instance->registers->usbsts;
213 instance->interrupt_code.cmdcount =
214 sizeof(uhci_cmds) / sizeof(irq_cmd_t);
215 }
216
217 /* Init transfer lists */
218 ret = hc_init_transfer_lists(instance);
219 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to init transfer lists.\n");
220 usb_log_debug("Initialized transfer lists.\n");
221
222 /* Init USB frame list page*/
223 instance->frame_list = get_page();
224 ret = instance ? EOK : ENOMEM;
225 CHECK_RET_DEST_CMDS_RETURN(ret, "Failed to get frame list page.\n");
226 usb_log_debug("Initialized frame list at %p.\n", instance->frame_list);
227
228 /* Set all frames to point to the first queue head */
229 const uint32_t queue =
230 LINK_POINTER_QH(addr_to_phys(
231 instance->transfers_interrupt.queue_head));
232
233 unsigned i = 0;
234 for(; i < UHCI_FRAME_LIST_COUNT; ++i) {
235 instance->frame_list[i] = queue;
236 }
237
238 /* Init device keeper */
239 usb_device_keeper_init(&instance->manager);
240 usb_log_debug("Initialized device manager.\n");
241
242 ret = usb_endpoint_manager_init(&instance->ep_manager,
243 BANDWIDTH_AVAILABLE_USB11);
244 assert(ret == EOK);
245
246 return EOK;
247#undef CHECK_RET_DEST_CMDS_RETURN
248}
249/*----------------------------------------------------------------------------*/
250/** Initialize UHCI hc transfer lists.
251 *
252 * @param[in] instance UHCI structure to use.
253 * @return Error code
254 * @note Should be called only once on any structure.
255 *
256 * Initializes transfer lists and sets them in one chain to support proper
257 * USB scheduling. Sets pointer table for quick access.
258 */
259int hc_init_transfer_lists(hc_t *instance)
260{
261 assert(instance);
262#define CHECK_RET_CLEAR_RETURN(ret, message...) \
263 if (ret != EOK) { \
264 usb_log_error(message); \
265 transfer_list_fini(&instance->transfers_bulk_full); \
266 transfer_list_fini(&instance->transfers_control_full); \
267 transfer_list_fini(&instance->transfers_control_slow); \
268 transfer_list_fini(&instance->transfers_interrupt); \
269 return ret; \
270 } else (void) 0
271
272 /* initialize TODO: check errors */
273 int ret;
274 ret = transfer_list_init(&instance->transfers_bulk_full, "BULK_FULL");
275 CHECK_RET_CLEAR_RETURN(ret, "Failed to init BULK list.");
276
277 ret = transfer_list_init(
278 &instance->transfers_control_full, "CONTROL_FULL");
279 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL FULL list.");
280
281 ret = transfer_list_init(
282 &instance->transfers_control_slow, "CONTROL_SLOW");
283 CHECK_RET_CLEAR_RETURN(ret, "Failed to init CONTROL SLOW list.");
284
285 ret = transfer_list_init(&instance->transfers_interrupt, "INTERRUPT");
286 CHECK_RET_CLEAR_RETURN(ret, "Failed to init INTERRUPT list.");
287
288 transfer_list_set_next(&instance->transfers_control_full,
289 &instance->transfers_bulk_full);
290 transfer_list_set_next(&instance->transfers_control_slow,
291 &instance->transfers_control_full);
292 transfer_list_set_next(&instance->transfers_interrupt,
293 &instance->transfers_control_slow);
294
295 /*FSBR*/
296#ifdef FSBR
297 transfer_list_set_next(&instance->transfers_bulk_full,
298 &instance->transfers_control_full);
299#endif
300
301 /* Assign pointers to be used during scheduling */
302 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_INTERRUPT] =
303 &instance->transfers_interrupt;
304 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_INTERRUPT] =
305 &instance->transfers_interrupt;
306 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_CONTROL] =
307 &instance->transfers_control_full;
308 instance->transfers[USB_SPEED_LOW][USB_TRANSFER_CONTROL] =
309 &instance->transfers_control_slow;
310 instance->transfers[USB_SPEED_FULL][USB_TRANSFER_BULK] =
311 &instance->transfers_bulk_full;
312
313 return EOK;
314#undef CHECK_RET_CLEAR_RETURN
315}
316/*----------------------------------------------------------------------------*/
317/** Schedule batch for execution.
318 *
319 * @param[in] instance UHCI structure to use.
320 * @param[in] batch Transfer batch to schedule.
321 * @return Error code
322 *
323 * Checks for bandwidth availability and appends the batch to the proper queue.
324 */
325int hc_schedule(hc_t *instance, usb_transfer_batch_t *batch)
326{
327 assert(instance);
328 assert(batch);
329
330 transfer_list_t *list =
331 instance->transfers[batch->ep->speed][batch->ep->transfer_type];
332 assert(list);
333 transfer_list_add_batch(list, batch);
334
335 return EOK;
336}
337/*----------------------------------------------------------------------------*/
338/** Take action based on the interrupt cause.
339 *
340 * @param[in] instance UHCI structure to use.
341 * @param[in] status Value of the status register at the time of interrupt.
342 *
343 * Interrupt might indicate:
344 * - transaction completed, either by triggering IOC, SPD, or an error
345 * - some kind of device error
346 * - resume from suspend state (not implemented)
347 */
348void hc_interrupt(hc_t *instance, uint16_t status)
349{
350 assert(instance);
351// status |= 1; //Uncomment to work around qemu hang
352 /* TODO: Resume interrupts are not supported */
353 /* Lower 2 bits are transaction error and transaction complete */
354 if (status & 0x3) {
355 LIST_INITIALIZE(done);
356 transfer_list_remove_finished(
357 &instance->transfers_interrupt, &done);
358 transfer_list_remove_finished(
359 &instance->transfers_control_slow, &done);
360 transfer_list_remove_finished(
361 &instance->transfers_control_full, &done);
362 transfer_list_remove_finished(
363 &instance->transfers_bulk_full, &done);
364
365 while (!list_empty(&done)) {
366 link_t *item = done.next;
367 list_remove(item);
368 usb_transfer_batch_t *batch =
369 list_get_instance(item, usb_transfer_batch_t, link);
370 usb_transfer_batch_finish(batch);
371 }
372 }
373 /* bits 4 and 5 indicate hc error */
374 if (status & 0x18) {
375 usb_log_error("UHCI hardware failure!.\n");
376 ++instance->hw_failures;
377 transfer_list_abort_all(&instance->transfers_interrupt);
378 transfer_list_abort_all(&instance->transfers_control_slow);
379 transfer_list_abort_all(&instance->transfers_control_full);
380 transfer_list_abort_all(&instance->transfers_bulk_full);
381
382 if (instance->hw_failures < UHCI_ALLOWED_HW_FAIL) {
383 /* reinitialize hw, this triggers virtual disconnect*/
384 hc_init_hw(instance);
385 } else {
386 usb_log_fatal("Too many UHCI hardware failures!.\n");
387 hc_fini(instance);
388 }
389 }
390}
391/*----------------------------------------------------------------------------*/
392/** Polling function, emulates interrupts.
393 *
394 * @param[in] arg UHCI hc structure to use.
395 * @return EOK (should never return)
396 */
397int hc_interrupt_emulator(void* arg)
398{
399 usb_log_debug("Started interrupt emulator.\n");
400 hc_t *instance = (hc_t*)arg;
401 assert(instance);
402
403 while (1) {
404 /* read and ack interrupts */
405 uint16_t status = pio_read_16(&instance->registers->usbsts);
406 pio_write_16(&instance->registers->usbsts, 0x1f);
407 if (status != 0)
408 usb_log_debug2("UHCI status: %x.\n", status);
409 hc_interrupt(instance, status);
410 async_usleep(UHCI_CLEANER_TIMEOUT);
411 }
412 return EOK;
413}
414/*---------------------------------------------------------------------------*/
415/** Debug function, checks consistency of memory structures.
416 *
417 * @param[in] arg UHCI structure to use.
418 * @return EOK (should never return)
419 */
420int hc_debug_checker(void *arg)
421{
422 hc_t *instance = (hc_t*)arg;
423 assert(instance);
424
425#define QH(queue) \
426 instance->transfers_##queue.queue_head
427
428 while (1) {
429 const uint16_t cmd = pio_read_16(&instance->registers->usbcmd);
430 const uint16_t sts = pio_read_16(&instance->registers->usbsts);
431 const uint16_t intr =
432 pio_read_16(&instance->registers->usbintr);
433
434 if (((cmd & UHCI_CMD_RUN_STOP) != 1) || (sts != 0)) {
435 usb_log_debug2("Command: %X Status: %X Intr: %x\n",
436 cmd, sts, intr);
437 }
438
439 uintptr_t frame_list =
440 pio_read_32(&instance->registers->flbaseadd) & ~0xfff;
441 if (frame_list != addr_to_phys(instance->frame_list)) {
442 usb_log_debug("Framelist address: %p vs. %p.\n",
443 frame_list, addr_to_phys(instance->frame_list));
444 }
445
446 int frnum = pio_read_16(&instance->registers->frnum) & 0x3ff;
447
448 uintptr_t expected_pa = instance->frame_list[frnum]
449 & LINK_POINTER_ADDRESS_MASK;
450 uintptr_t real_pa = addr_to_phys(QH(interrupt));
451 if (expected_pa != real_pa) {
452 usb_log_debug("Interrupt QH: %p(frame: %d) vs. %p.\n",
453 expected_pa, frnum, real_pa);
454 }
455
456 expected_pa = QH(interrupt)->next & LINK_POINTER_ADDRESS_MASK;
457 real_pa = addr_to_phys(QH(control_slow));
458 if (expected_pa != real_pa) {
459 usb_log_debug("Control Slow QH: %p vs. %p.\n",
460 expected_pa, real_pa);
461 }
462
463 expected_pa = QH(control_slow)->next & LINK_POINTER_ADDRESS_MASK;
464 real_pa = addr_to_phys(QH(control_full));
465 if (expected_pa != real_pa) {
466 usb_log_debug("Control Full QH: %p vs. %p.\n",
467 expected_pa, real_pa);
468 }
469
470 expected_pa = QH(control_full)->next & LINK_POINTER_ADDRESS_MASK;
471 real_pa = addr_to_phys(QH(bulk_full));
472 if (expected_pa != real_pa ) {
473 usb_log_debug("Bulk QH: %p vs. %p.\n",
474 expected_pa, real_pa);
475 }
476 async_usleep(UHCI_DEBUGER_TIMEOUT);
477 }
478 return EOK;
479#undef QH
480}
481/*----------------------------------------------------------------------------*/
482/** Check transfers for USB validity
483 *
484 * @param[in] low_speed Transfer speed.
485 * @param[in] transfer Transer type
486 * @param[in] size Size of data packets
487 * @return True if transaction is allowed by USB specs, false otherwise
488 */
489#if 0
490bool usb_is_allowed(
491 bool low_speed, usb_transfer_type_t transfer, size_t size)
492{
493 /* see USB specification chapter 5.5-5.8 for magic numbers used here */
494 switch(transfer)
495 {
496 case USB_TRANSFER_ISOCHRONOUS:
497 return (!low_speed && size < 1024);
498 case USB_TRANSFER_INTERRUPT:
499 return size <= (low_speed ? 8 : 64);
500 case USB_TRANSFER_CONTROL: /* device specifies its own max size */
501 return (size <= (low_speed ? 8 : 64));
502 case USB_TRANSFER_BULK: /* device specifies its own max size */
503 return (!low_speed && size <= 64);
504 }
505 return false;
506}
507#endif
508/**
509 * @}
510 */
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