| [8c06905] | 1 | /*
|
|---|
| [663f41c4] | 2 | * Copyright (c) 2010 Lenka Trochtova
|
|---|
| [8c06905] | 3 | * All rights reserved.
|
|---|
| 4 | *
|
|---|
| 5 | * Redistribution and use in source and binary forms, with or without
|
|---|
| 6 | * modification, are permitted provided that the following conditions
|
|---|
| 7 | * are met:
|
|---|
| 8 | *
|
|---|
| 9 | * - Redistributions of source code must retain the above copyright
|
|---|
| 10 | * notice, this list of conditions and the following disclaimer.
|
|---|
| 11 | * - Redistributions in binary form must reproduce the above copyright
|
|---|
| 12 | * notice, this list of conditions and the following disclaimer in the
|
|---|
| 13 | * documentation and/or other materials provided with the distribution.
|
|---|
| 14 | * - The name of the author may not be used to endorse or promote products
|
|---|
| 15 | * derived from this software without specific prior written permission.
|
|---|
| 16 | *
|
|---|
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
|---|
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
|---|
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
|---|
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|---|
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|---|
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|---|
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|---|
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|---|
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|---|
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|---|
| 27 | */
|
|---|
| 28 |
|
|---|
| 29 | /** @addtogroup pciintel
|
|---|
| 30 | * @{
|
|---|
| 31 | */
|
|---|
| 32 | /** @file
|
|---|
| 33 | */
|
|---|
| 34 |
|
|---|
| [663f41c4] | 35 | #ifndef PCI_REGS_H_
|
|---|
| 36 | #define PCI_REGS_H_
|
|---|
| [8c06905] | 37 |
|
|---|
| [663f41c4] | 38 | /* Header types */
|
|---|
| 39 | #define PCI_HEADER_TYPE_DEV 0
|
|---|
| 40 | #define PCI_HEADER_TYPE_BRIDGE 1
|
|---|
| 41 | #define PCI_HEADER_TYPE_CARDBUS 2
|
|---|
| [8c06905] | 42 |
|
|---|
| [663f41c4] | 43 | /* Header type 0 and 1 */
|
|---|
| 44 | #define PCI_VENDOR_ID 0x00
|
|---|
| 45 | #define PCI_DEVICE_ID 0x02
|
|---|
| 46 | #define PCI_COMMAND 0x04
|
|---|
| 47 | #define PCI_STATUS 0x06
|
|---|
| 48 | #define PCI_REVISION_ID 0x08
|
|---|
| 49 | #define PCI_PROG_IF 0x09
|
|---|
| 50 | #define PCI_SUB_CLASS 0x0A
|
|---|
| 51 | #define PCI_BASE_CLASS 0x0B
|
|---|
| 52 | #define PCI_CACHE_LINE_SIZE 0x0C
|
|---|
| 53 | #define PCI_LATENCY_TIMER 0x0D
|
|---|
| 54 | #define PCI_HEADER_TYPE 0x0E
|
|---|
| 55 | #define PCI_BIST 0x0F
|
|---|
| [8c06905] | 56 |
|
|---|
| [663f41c4] | 57 | #define PCI_BASE_ADDR_0 0x10
|
|---|
| 58 | #define PCI_BASE_ADDR_1 0x14
|
|---|
| [8c06905] | 59 |
|
|---|
| [663f41c4] | 60 | /* Header type 0 */
|
|---|
| 61 | #define PCI_BASE_ADDR_2 0x18
|
|---|
| 62 | #define PCI_BASE_ADDR_3 0x1B
|
|---|
| 63 | #define PCI_BASE_ADDR_4 0x20
|
|---|
| 64 | #define PCI_BASE_ADDR_5 0x24
|
|---|
| [8c06905] | 65 |
|
|---|
| [663f41c4] | 66 | #define PCI_CARDBUS_CIS_PTR 0x28
|
|---|
| 67 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2C
|
|---|
| 68 | #define PCI_SUBSYSTEM_ID 0x2E
|
|---|
| 69 | #define PCI_EXP_ROM_BASE 0x30
|
|---|
| 70 | #define PCI_CAP_PTR 0x34
|
|---|
| 71 | #define PCI_INT_LINE 0x3C
|
|---|
| 72 | #define PCI_INT_PIN 0x3D
|
|---|
| 73 | #define PCI_MIN_GNT 0x3E
|
|---|
| 74 | #define PCI_MAX_LAT 0x3F
|
|---|
| 75 |
|
|---|
| 76 | /* Header type 1 */
|
|---|
| 77 | #define PCI_BRIDGE_PRIM_BUS_NUM 0x18
|
|---|
| 78 | #define PCI_BRIDGE_SEC_BUS_NUM 0x19
|
|---|
| 79 | #define PCI_BRIDGE_SUBORD_BUS_NUM 0x1A
|
|---|
| 80 | #define PCI_BRIDGE_SEC_LATENCY_TIMER 0x1B
|
|---|
| 81 | #define PCI_BRIDGE_IO_BASE 0x1C
|
|---|
| 82 | #define PCI_BRIDGE_IO_LIMIT 0x1D
|
|---|
| 83 | #define PCI_BRIDGE_SEC_STATUS 0x1E
|
|---|
| 84 | #define PCI_BRIDGE_MEMORY_BASE 0x20
|
|---|
| 85 | #define PCI_BRIDGE_MEMORY_LIMIT 0x22
|
|---|
| 86 | #define PCI_BRIDGE_PREF_MEMORY_BASE 0x24
|
|---|
| [8c06905] | 87 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT 0x26
|
|---|
| 88 | #define PCI_BRIDGE_PREF_MEMORY_BASE_UP 0x28
|
|---|
| 89 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT_UP 0x2C
|
|---|
| [663f41c4] | 90 | #define PCI_BRIDGE_IO_BASE_UP 0x30
|
|---|
| 91 | #define PCI_BRIDGE_IO_LIMIT_UP 0x32
|
|---|
| 92 | #define PCI_BRIDGE_EXP_ROM_BASE 0x38
|
|---|
| 93 | #define PCI_BRIDGE_INT_LINE 0x3C
|
|---|
| 94 | #define PCI_BRIDGE_INT_PIN 0x3D
|
|---|
| 95 | #define PCI_BRIDGE_CTL 0x3E
|
|---|
| [8c06905] | 96 |
|
|---|
| 97 | #endif
|
|---|
| 98 |
|
|---|
| 99 | /**
|
|---|
| 100 | * @}
|
|---|
| [663f41c4] | 101 | */
|
|---|
