| 1 | /*
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| 2 | * Copyright (c) 2010 Lenka Trochtova
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup pciintel
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #ifndef PCI_REGS_H_
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| 36 | #define PCI_REGS_H_
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| 37 |
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| 38 | /* Header types */
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| 39 | #define PCI_HEADER_TYPE_DEV 0
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| 40 | #define PCI_HEADER_TYPE_BRIDGE 1
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| 41 | #define PCI_HEADER_TYPE_CARDBUS 2
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| 42 |
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| 43 | /* Header type 0 and 1 */
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| 44 | #define PCI_VENDOR_ID 0x00
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| 45 | #define PCI_DEVICE_ID 0x02
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| 46 | #define PCI_COMMAND 0x04
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| 47 | #define PCI_STATUS 0x06
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| 48 | #define PCI_REVISION_ID 0x08
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| 49 | #define PCI_PROG_IF 0x09
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| 50 | #define PCI_SUB_CLASS 0x0A
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| 51 | #define PCI_BASE_CLASS 0x0B
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| 52 | #define PCI_CACHE_LINE_SIZE 0x0C
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| 53 | #define PCI_LATENCY_TIMER 0x0D
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| 54 | #define PCI_HEADER_TYPE 0x0E
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| 55 | #define PCI_BIST 0x0F
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| 56 |
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| 57 | #define PCI_BASE_ADDR_0 0x10
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| 58 | #define PCI_BASE_ADDR_1 0x14
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| 59 |
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| 60 | /* Header type 0 */
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| 61 | #define PCI_BASE_ADDR_2 0x18
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| 62 | #define PCI_BASE_ADDR_3 0x1B
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| 63 | #define PCI_BASE_ADDR_4 0x20
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| 64 | #define PCI_BASE_ADDR_5 0x24
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| 65 |
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| 66 | #define PCI_CARDBUS_CIS_PTR 0x28
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| 67 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2C
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| 68 | #define PCI_SUBSYSTEM_ID 0x2E
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| 69 | #define PCI_EXP_ROM_BASE 0x30
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| 70 | #define PCI_CAP_PTR 0x34
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| 71 | #define PCI_INT_LINE 0x3C
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| 72 | #define PCI_INT_PIN 0x3D
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| 73 | #define PCI_MIN_GNT 0x3E
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| 74 | #define PCI_MAX_LAT 0x3F
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| 75 |
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| 76 | /* Header type 1 */
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| 77 | #define PCI_BRIDGE_PRIM_BUS_NUM 0x18
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| 78 | #define PCI_BRIDGE_SEC_BUS_NUM 0x19
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| 79 | #define PCI_BRIDGE_SUBORD_BUS_NUM 0x1A
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| 80 | #define PCI_BRIDGE_SEC_LATENCY_TIMER 0x1B
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| 81 | #define PCI_BRIDGE_IO_BASE 0x1C
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| 82 | #define PCI_BRIDGE_IO_LIMIT 0x1D
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| 83 | #define PCI_BRIDGE_SEC_STATUS 0x1E
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| 84 | #define PCI_BRIDGE_MEMORY_BASE 0x20
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| 85 | #define PCI_BRIDGE_MEMORY_LIMIT 0x22
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| 86 | #define PCI_BRIDGE_PREF_MEMORY_BASE 0x24
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| 87 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT 0x26
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| 88 | #define PCI_BRIDGE_PREF_MEMORY_BASE_UP 0x28
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| 89 | #define PCI_BRIDGE_PREF_MEMORY_LIMIT_UP 0x2C
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| 90 | #define PCI_BRIDGE_IO_BASE_UP 0x30
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| 91 | #define PCI_BRIDGE_IO_LIMIT_UP 0x32
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| 92 | #define PCI_BRIDGE_EXP_ROM_BASE 0x38
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| 93 | #define PCI_BRIDGE_INT_LINE 0x3C
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| 94 | #define PCI_BRIDGE_INT_PIN 0x3D
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| 95 | #define PCI_BRIDGE_CTL 0x3E
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| 96 |
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| 97 | #endif
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| 98 |
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| 99 | /**
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| 100 | * @}
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| 101 | */
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