source: mainline/uspace/drv/nic/rtl8139/defs.h@ a9654bf

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a9654bf was 0f323d3, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

uhcirh, rtl8139: Include ddi.h header.

This prevents breakage in the next commits.

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File size: 19.5 KB
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1/*
2 * Copyright (c) 2011 Jiri Michalec
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file rtl8139_defs.h
30 *
31 * Registers, bit positions and masks definition
32 * of the RTL8139 network family cards
33 */
34
35#ifndef RTL8139_DEFS_H_
36#define RTL8139_DEFS_H_
37
38#include <sys/types.h>
39#include <ddi.h>
40#include <libarch/ddi.h>
41
42/** Size of RTL8139 registers address space */
43#define RTL8139_IO_SIZE 256
44
45/** Maximal transmitted frame length
46 *
47 * Maximal transmitted frame length in bytes
48 * allowed according to the RTL8139 documentation
49 * (see SIZE part of TSD documentation).
50 *
51 */
52#define RTL8139_FRAME_MAX_LENGTH 1792
53
54/** HW version
55 *
56 * As can be detected from HWVERID part of TCR
57 * (Transmit Configuration Register).
58 *
59 */
60typedef enum {
61 RTL8139 = 0, /**< RTL8139 */
62 RTL8139A, /**< RTL8139A */
63 RTL8139A_G, /**< RTL8139A-G */
64 RTL8139B, /**< RTL8139B */
65 RTL8130, /**< RTL8130 */
66 RTL8139C, /**< RTL8139C */
67 RTL8100, /**< RTL8100 */
68 RTL8139Cp, /**< RTL8139C+ */
69 RTL8139D, /**< RTL8139D */
70 RTL8100B = RTL8139D, /**< RTL8100B and RTL8139D, the same HWVERID in TCR */
71 RTL8101, /**< RTL8101 */
72 RTL8139_VER_COUNT /**< Count of known RTL versions, the last value */
73} rtl8139_version_id_t;
74
75/** Registers of RTL8139 family card offsets from the memory address base */
76enum rtl8139_registers {
77 IDR0 = 0x00, /**< First MAC address bit, 6 1b registres sequence */
78 MAC0 = IDR0, /**< Alias for IDR0 */
79
80 // 0x06 - 0x07 reserved
81
82 MAR0 = 0x08, /**< Multicast mask registers 8 1b registers sequence */
83
84 TSD0 = 0x10, /**< Transmit status of descriptor 0 */
85 TSD1 = 0x14, /**< Transmit status of descriptor 1 */
86 TSD2 = 0x18, /**< Transmit status of descriptor 2 */
87 TSD3 = 0x1C, /**< Transmit status of descriptor 3 */
88
89 TSAD0 = 0x20, /**< Physical address of the 1st transmitter buffer, 4b */
90 TSAD1 = 0x24, /**< Physical address of the 2nd transmitter buffer, 4b */
91 TSAD2 = 0x28, /**< Physical address of the 3rd transmitter buffer, 4b */
92 TSAD3 = 0x3C, /**< Physical address of the 4th transmitter buffer, 4b */
93
94 RBSTART = 0x30, /**< Receive (Rx) buffer start address, 4b */
95 ERBCR = 0x34, /**< Early receive (Rx) byte count register, 2b */
96 ERSR = 0x36, /**< Early receive (Rx) status register, 1b */
97
98 CR = 0x37, /**< Command register, 1b */
99 CAPR = 0x38, /**< Current address of frame read, 2b */
100 CBA = 0x3a, /**< Current buffer address, 2b */
101
102 IMR = 0x3c, /**< Interrupt mask register, 2b */
103 ISR = 0x3e, /**< Interrupt status register, 2b */
104
105 TCR = 0x40, /**< Transmit (Tx) configuration register, 4b */
106 RCR = 0x44, /**< Receive (Rx) configuration register, 4b */
107
108 TCTR = 0x48, /**< Timer count register */
109 MPC = 0x4c, /**< Missed packet count */
110
111 CR9346 = 0x50, /**< 93C46 command register (locking of registers) */
112
113 CONFIG0 = 0x51, /**< Configuration register 0, 1b */
114 CONFIG1 = 0x52, /**< Configuration register 1, 1b */
115
116 // 0x53 reserved
117
118 TIMERINT = 0x54, /**< Timer interrupt register, 4b */
119 MSR = 0x58, /**< Media status register, 1b */
120
121 CONFIG3 = 0x59, /**< Configuration register 3, 1b */
122 CONFIG4 = 0x5a, /**< Configuration register 4, 1b */
123
124 // 0x5b reserved
125
126 MULINT = 0x5c, /**< Multiple interrupt select, 2b */
127 RERID = 0x5e, /**< PCI revision ID = 0x10, 1b */
128
129 // 0x5f reserved
130
131 TSALLD = 0x60, /**< Transmit status of all descriptors, 2b */
132
133 BMCR = 0x62, /**< Basic mode control register */
134 BMSR = 0x64, /**< Basic mode status register */
135
136 ANAR = 0x66, /**< Auto-negotiation advertisement register */
137 ANLPAR = 0x68, /**< Auto-negotiation link partner register */
138 ANER = 0x6a, /**< Auto-negotiation expansion register */
139 DIS = 0x6c, /**< Disconnect counter */
140 FCSC = 0x6e, /**< False carrier sense counter */
141 NWAYTR = 0x70, /**< n-way test register */
142 REC = 0x72, /**< RX_ER counter */
143 CSCR = 0x74, /**< CS configuration register */
144
145 // 0x76 - 0x77 reserved
146
147 PHY1_PARM = 0x78, /**< PHY parameter 1 */
148 TW_PARM = 0x7c, /**< Twister parameter */
149 PHY2_PARM = 0x80, /**< PHY parameter 2 */
150
151 // 0x81 reserved
152
153 TDOKLA = 0x82, /**< Low Address of a Tx Descriptor with Tx DMA Ok */
154 CRC0 = 0x84, /**< Power Management CRC register0 for wakeup frame 0 */
155 WAKEUP0 = 0x8c, /**< Power Management wakeup frame 0 */
156 LSBCRC0 = 0xcc, /**< Least significant masked byte of WF0 */
157 FLASH = 0xd4, /**< Flash memory read/write register */
158
159 CONFIG5 = 0xd8, /**< Configuration register 5 */
160
161 TPPOL = 0xd9, /**< Transmit priority polling register */
162
163 // 0xda - 0xdf reserved
164
165 CPCR = 0xe0, /**< C+ mode command register */
166
167 // 0xe2 - 0xe3 reserved
168
169 RDSAR = 0xe4, /**< Receive Descriptor Start Address Register */
170 ETTHR = 0xec, /**< Early transmit threshold register */
171
172 // 0xed - 0xef reserved
173
174 FER = 0xf0, /**< Function event register */
175 FEMR = 0xf4, /**< Function event mask register */
176 FPSR = 0xf8, /**< Function present state register */
177 FFER = 0xfc, /**< Function force event register */
178 MIIR = 0xfc /**< MII register */
179};
180
181/** Mask of valid bits in MPC value */
182#define MPC_VMASK UINT32_C(0xFFFFFF);
183
184/** Command register bits */
185enum rtl8139_cr {
186 CR_BUFE = (1 << 0), /**< Buffer empty bit - read only */
187 CR_TE = (1 << 2), /**< Transmitter enable bit */
188 CR_RE = (1 << 3), /**< Receiver enable bit */
189 CR_RST = (1 << 4) /**< Reset - set to 1 to force software reset */
190};
191
192/** Config1 register bits */
193enum rtl8139_config1 {
194 CONFIG1_LEDS_SHIFT = 6, /**< Shift of CONFIG1_LEDS bits */
195 CONFIG1_LEDS_SIZE = 2, /**< Size of CONFIG1_LEDS bits */
196
197 CONFIG1_DVRLOAD = (1 << 5), /**< Driver load */
198 CONFIG1_LWACT = (1 << 4), /**< LWAKE active mode */
199 CONFIG1_MEMMAP = (1 << 3), /**< Memory mapping */
200 CONFIG1_IOMAP = (1 << 2), /**< I/O space mapping */
201 CONFIG1_VPD = (1 << 1), /**< Set to enable Vital Product Data */
202 CONFIG1_PMEn = (1 << 0) /**< Power management enabled */
203};
204
205/** Mask of 9346CR register for lock configuration registers */
206#define RTL8139_REGS_LOCKED 0
207/** Mask of 9346CR register for unlock configuration registers */
208#define RTL8139_REGS_UNLOCKED 0xC0
209
210/** Put rtl8139 to normal mode.
211 *
212 * Writing to Config0-4 and part of BMCR registers is not allowed
213 */
214static inline void rtl8139_regs_lock(void *io_base)
215{
216 pio_write_8(io_base + CR9346, RTL8139_REGS_LOCKED);
217}
218
219/** Allow to change Config0-4 and BMCR register */
220static inline void rtl8139_regs_unlock(void *io_base)
221{
222 pio_write_8((io_base) + CR9346, RTL8139_REGS_UNLOCKED);
223}
224
225/** Force soft reset of the chip. After it:
226 * receiver and transmitter are disabled
227 * transmitter FIFO is cleared
228 * transmitter buffer is set to TSDA0
229 * receiver buffer is empty
230 *
231 * The reset bit in command register must be set to 1, the value of the
232 * the register is 1 during reset operation
233 *
234 * @param base_port The base address of the port mappings
235 */
236#define rtl8139_hw_reset(base_port)\
237 {\
238 pio_write_8(base_port + CR, CR_RST);\
239 while((pio_read_8(base_port + CR) & CR_RST) != 0);\
240 }
241
242/** Interrupt_masks
243 *
244 * The masks are the same for both IMR and ISR
245 */
246enum rtl8139_interrupts {
247 INT_SERR = (1 << 15), /**< System error interrupt */
248 INT_TIME_OUT = (1 << 14), /**< Time out interrupt */
249 INT_LENGTH_CHANGE = (1 << 13), /**< Cable length change interrupt */
250
251 /* bits 7 - 12 reserved */
252
253 INT_FIFOOVW = (1 << 6), /**< Receiver FIFO overflow interrupt */
254 INT_PUN = (1 << 5), /**< Packet Underrun/Link Change Interrupt */
255 INT_RXOVW = (1 << 4), /**< Receiver buffer overflow */
256 INT_TER = (1 << 3), /**< Transmit error interrupt */
257 INT_TOK = (1 << 2), /**< Transmit OK interrupt */
258 INT_RER = (1 << 1), /**< Receive error interrupt */
259 INT_ROK = (1 << 0) /**< Receive OK interrupt */
260};
261
262/** Transmit status descriptor registers bits */
263enum rtl8139_tsd {
264 TSD_CRS = (1 << 31), /**< Carrier Sense Lost */
265 TSD_TABT = (1 << 30), /**< Transmit Abort */
266 TSD_OWC = (1 << 29), /**< Out of Window Collision */
267 TSD_CDH = (1 << 28), /**< CD Heart Beat */
268 TSD_NCC_SHIFT = 24, /**< Collision Count - bit shift */
269 TSD_NCC_SIZE = 4, /**< Collision Count - bit size */
270 TSD_NCC_MASK = (1 << 4)-1, /**< Collision Count - bit size */
271 TSD_ERTXTH_SHIFT = 16, /**< Early Tx Threshold - bit shift */
272 TSD_ERTXTH_SIZE = 6, /**< Early Tx Treshold - bit size */
273 TSD_TOK = (1 << 15), /**< Transmit OK */
274 TSD_TUN = (1 << 14), /**< Transmit FIFO Underrun */
275 TSD_OWN = (1 << 13), /**< OWN */
276 TSD_SIZE_SHIFT = 0, /**< Size - bit shift */
277 TSD_SIZE_SIZE = 13, /**< Size - bit size */
278 TSD_SIZE_MASK = 0x1fff /**< Size - bit mask */
279};
280
281/** Receiver control register values */
282enum rtl8139_rcr {
283 RCR_ERTH_SHIFT = 24, /**< Early Rx treshold part shift */
284 RCR_ERTH_SIZE = 4, /**< Early Rx treshold part size */
285
286 RCR_MulERINT = 1 << 17, /**< Multiple early interrupt select */
287
288 /** Minimal error frame length (1 = 8B, 0 = 64B). If AER/AR is set, RER8
289 * is "Don't care"
290 */
291 RCR_RER8 = 1 << 16,
292
293 RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */
294 RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */
295
296 RCR_RBLEN_SHIFT = 11, /**< Rx buffer length part shift */
297 RCR_RBLEN_SIZE = 2, /**< Rx buffer length part size */
298
299 RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, /**< 8K + 16 byte rx buffer */
300 RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, /**< 16K + 16 byte rx buffer */
301 RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, /**< 32K + 16 byte rx buffer */
302 RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, /**< 64K + 16 byte rx buffer */
303
304 RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */
305 RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */
306
307 RCR_WRAP = 1 << 7, /**< Rx buffer wrapped */
308 RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error frame */
309 RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) frames */
310 RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */
311 RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */
312 RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */
313 RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all frames with
314 * phys. desticnation
315 */
316 RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */
317};
318
319
320/** CSCR register bits */
321enum rtl8139_cscr {
322 CS_Testfun = (1 << 15),
323 CS_LD = (1 << 9), /**< Low TPI link disable signal */
324 CS_HEART_BEAT = (1 << 8), /**< Heart beat enable; 10Mbit mode only */
325 CS_JABBER_ENABLE = (1 << 7), /**< Enable jabber function */
326 CS_F_LINK100 = (1 << 6),
327 CS_F_CONNECT = (1 << 5),
328 CS_CON_STATUS = (1 << 3), /**< connection status:
329 * 1 = valid, 0 = disconnected
330 */
331 CS_CON_STATUS_EN = (1 << 2), /**< LED1 pin connection status indication */
332 CS_PASS_SCR = (1 << 0) /**< Bypass Scramble */
333};
334
335/** MSR register bits */
336enum rtl8139_msr {
337 MSR_TXFCE = (1 << 7), /**< Transmitter flow control enable */
338 MSR_RXFCE = (1 << 6), /**< Receiver flow control enable */
339
340 MSR_AUX_PRESENT = (1 << 4), /**< Aux. Power present Status */
341 MSR_SPEED10 = (1 << 3), /**< 10MBit mode sign (1 = 10Mb, 0 = 100Mb) */
342 MSR_LINKB = (1 << 2), /**< Link Bad (fail) */
343 MSR_TXPF = (1 << 1), /**< Transmitter pause flag */
344 MSR_RXPF = (1 << 0) /**< Receiver pause flag */
345};
346
347/** BMCR register bits (basic mode control register) */
348enum rtl8139_bmcr {
349 BMCR_Reset = (1 << 15), /**< Software reset */
350 BMCR_Spd_100 = (1 << 13), /**< 100 MBit mode set, 10 MBit otherwise */
351 BMCR_AN_ENABLE = (1 << 12), /**< Autonegotion enable */
352
353 /* 10,11 reserved*/
354
355 BMCR_AN_RESTART = (1 << 9), /**< Restart autonegotion */
356 BMCR_DUPLEX = (1 << 8) /**< Duplex mode: 1=full duplex */
357
358 /* 0-7 reserved */
359};
360
361/** Auto-negotiation advertisement register */
362enum rtl8139_anar {
363 ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability
364 * 1 - protocol specific
365 */
366 ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */
367 ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */
368 ANAR_PAUSE = (1 << 10), /**< Symetric pause frame capability */
369 ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */
370 ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */
371 ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */
372 ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */
373 ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */
374 ANAR_SELECTOR = 0x1 /**< Selector,
375 * CSMA/CD (0x1) supported only
376 */
377};
378
379/** Autonegotiation expansion register bits */
380enum rtl8139_aner {
381 ANER_MFL = (1 << 4), /**< Multiple link fault occured */
382 ANER_LP_NP_ABLE = (1 << 3), /**< Link parent supports next page */
383 ANER_NP_ABLE = (1 << 2), /**< Local node is able to send next pages */
384 ANER_PAGE_RX = (1 << 1), /** New page received, cleared on LPAR read */
385 ANER_LP_NW_ABLE = (1 << 0) /**< Link partner autonegotiation support */
386};
387
388enum rtl8139_config5 {
389 CONFIG5_BROADCAST_WAKEUP = (1 << 6), /**< Broadcast wakeup frame enable */
390 CONFIG5_MULTICAST_WAKEUP = (1 << 5), /**< Multicast wakeup frame enable */
391 CONFIG5_UNICAST_WAKEUP = (1 << 4), /**< Unicast wakeup frame enable */
392
393 /** Descending/ascending grow of Rx/Tx FIFO (to test FIFO SRAM only) */
394 CONFIG5_FIFO_ADDR_PTR = (1 << 3),
395 /** Powersave if cable is disconnected */
396 CONFIG5_LINK_DOWN_POWERSAVE = (1 << 2),
397
398 CONFIG5_LAN_WAKE = (1 << 1), /**< LANWake signal enabled */
399 CONFIG5_PME_STATUS = (1 << 0) /**< PMEn change: 0 = SW, 1 = SW+PCI */
400};
401
402enum rtl8139_config3 {
403 CONFIG3_GNT_SELECT = (1 << 7), /**< Gnt select */
404 CONFIG3_PARM_EN = (1 << 6), /**< Parameter enabled (100MBit mode) */
405 CONFIG3_MAGIC = (1 << 5), /**< WoL Magic frame enable */
406 CONFIG3_LINK_UP = (1 << 4), /**< Wakeup if link is reestablished */
407 CONFIG3_CLKRUN_EN = (1 << 2), /**< CLKRUN enabled */ /* TODO: check what does it mean */
408 CONFIG3_FBTBEN = (1 << 0) /**< Fast back to back enabled */
409};
410
411enum rtl8139_config4 {
412 CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */
413 CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */
414 CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame
415 * (2xCRC8 + 3xCRC16)
416 */
417 CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */
418 CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */
419 CONFIG4_PBWakeup = (1 << 0) /**< Preboot wakeup */
420};
421
422/** Maximal runt frame size + 1 */
423#define RTL8139_RUNT_MAX_SIZE 64
424
425/** Bits in frame header */
426enum rtl8139_frame_header {
427 RSR_MAR = (1 << 15), /**< Multicast received */
428 RSR_PAM = (1 << 14), /**< Physical address match */
429 RSR_BAR = (1 << 13), /**< Broadcast match */
430
431 RSR_ISE = (1 << 5), /**< Invalid symbol error, 100BASE-TX only */
432 RSR_RUNT = (1 << 4), /**< Runt frame (< RTL8139_RUNT_MAX_SIZE bytes) */
433
434 RSR_LONG = (1 << 3), /**< Long frame (size > 4k bytes) */
435 RSR_CRC = (1 << 2), /**< CRC error */
436 RSR_FAE = (1 << 1), /**< Frame alignment error */
437 RSR_ROK = (1 << 0) /**< Good frame received */
438};
439
440enum rtl8139_tcr_bits {
441 HWVERID_A_SHIFT = 26, /**< HW version id, part A shift */
442 HWVERID_A_SIZE = 5, /**< HW version id, part A bit size */
443 HWVERID_A_MASK = (1 << 5) - 1, /**< HW version id, part A mask */
444
445 IFG_SHIFT = 24, /**< The interframe gap time setting shift */
446 IFG_SIZE = 2, /**< The interframe gap time setting bit size */
447
448 HWVERID_B_SHIFT = 22, /**< HW version id, part B shift */
449 HWVERID_B_SIZE = 2, /**< HW version id, part B bit size */
450 HWVERID_B_MASK = (1 << 2) - 1, /**< HW version id, part B mask */
451
452 LOOPBACK_SHIFT = 17, /**< Loopback mode shift */
453 LOOPBACK_SIZE = 2, /**< Loopback mode size
454 * 00 = normal, 11 = loopback
455 */
456
457 APPEND_CRC = 1 << 16, /**< Append CRC at the end of a frame */
458
459 MXTxDMA_SHIFT = 8, /**< Max. DMA Burst per TxDMA shift, burst = 16^value */
460 MXTxDMA_SIZE = 3, /**< Max. DMA Burst per TxDMA bit size */
461
462 TX_RETRY_COUNT_SHIFT = 4, /**< Retries before aborting shift */
463 TX_RETRY_COUNT_SIZE = 4, /**< Retries before aborting size */
464
465 CLEAR_ABORT = 1 << 0 /**< Retransmit aborted frame at the last
466 * transmitted descriptor
467 */
468};
469
470#define RTL8139_HWVERID_A(tcr) (((tcr) >> HWVERID_A_SHIFT) & HWVERID_A_MASK)
471#define RTL8139_HWVERID_B(tcr) (((tcr) >> HWVERID_B_SHIFT) & HWVERID_B_MASK)
472#define RTL8139_HWVERID(tcr) ((RTL8139_HWVERID_A(tcr) << HWVERID_B_SIZE) | \
473 RTL8139_HWVERID_B(tcr))
474
475/** Mapping of HW version -> version ID */
476struct rtl8139_hwver_map {
477 uint32_t hwverid; /**< HW version value in the register */
478 rtl8139_version_id_t ver_id; /**< appropriate version id */
479};
480
481/** Mapping of HW version -> version ID */
482extern const struct rtl8139_hwver_map rtl8139_versions[RTL8139_VER_COUNT + 1];
483extern const char* model_names[RTL8139_VER_COUNT];
484
485/** Size in the frame header while copying from RxFIFO to Rx buffer */
486#define RTL8139_EARLY_SIZE UINT16_C(0xfff0)
487
488/** The only supported pause frame time value */
489#define RTL8139_PAUSE_VAL UINT16_C(0xFFFF)
490
491/** Size of the frame header in front of the received frame */
492#define RTL_FRAME_HEADER_SIZE 4
493
494/** 8k buffer */
495#define RTL8139_RXFLAGS_SIZE_8 0
496/** 16k buffer */
497#define RTL8139_RXFLAGS_SIZE_16 1
498/** 32k buffer */
499#define RTL8139_RXFLAGS_SIZE_32 2
500/** 64k buffer */
501#define RTL8139_RXFLAGS_SIZE_64 3
502
503/** Get the buffer initial size without 16B padding
504 * Size is (8 + 2^flags) kB (^ in mean power)
505 *
506 * @param flags The flags for Rx buffer size, 0-3
507 */
508#define RTL8139_RXSIZE(flags) (1 << (13 + (flags)))
509
510/** Padding of the receiver buffer */
511#define RTL8139_RXBUF_PAD 16
512/** Size needed for buffer allocation */
513#define RTL8139_RXBUF_LENGTH(flags) (RTL8139_RXSIZE(flags) + RTL8139_RXBUF_PAD)
514
515#endif
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