source: mainline/uspace/drv/nic/rtl8139/defs.h

Last change on this file was d1582b50, checked in by Jiri Svoboda <jiri@…>, 5 years ago

Fix spacing in single-line comments using latest ccheck

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1/*
2 * Copyright (c) 2011 Jiri Michalec
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file rtl8139_defs.h
30 *
31 * Registers, bit positions and masks definition
32 * of the RTL8139 network family cards
33 */
34
35#ifndef RTL8139_DEFS_H_
36#define RTL8139_DEFS_H_
37
38#include <stdint.h>
39#include <ddi.h>
40
41/** Size of RTL8139 registers address space */
42#define RTL8139_IO_SIZE 256
43
44/** Maximal transmitted frame length
45 *
46 * Maximal transmitted frame length in bytes
47 * allowed according to the RTL8139 documentation
48 * (see SIZE part of TSD documentation).
49 *
50 */
51#define RTL8139_FRAME_MAX_LENGTH 1792
52
53/** HW version
54 *
55 * As can be detected from HWVERID part of TCR
56 * (Transmit Configuration Register).
57 *
58 */
59typedef enum {
60 RTL8139 = 0, /**< RTL8139 */
61 RTL8139A, /**< RTL8139A */
62 RTL8139A_G, /**< RTL8139A-G */
63 RTL8139B, /**< RTL8139B */
64 RTL8130, /**< RTL8130 */
65 RTL8139C, /**< RTL8139C */
66 RTL8100, /**< RTL8100 */
67 RTL8139Cp, /**< RTL8139C+ */
68 RTL8139D, /**< RTL8139D */
69 RTL8100B = RTL8139D, /**< RTL8100B and RTL8139D, the same HWVERID in TCR */
70 RTL8101, /**< RTL8101 */
71 RTL8139_VER_COUNT /**< Count of known RTL versions, the last value */
72} rtl8139_version_id_t;
73
74/** Registers of RTL8139 family card offsets from the memory address base */
75enum rtl8139_registers {
76 IDR0 = 0x00, /**< First MAC address bit, 6 1b registres sequence */
77 MAC0 = IDR0, /**< Alias for IDR0 */
78
79 // 0x06 - 0x07 reserved
80
81 MAR0 = 0x08, /**< Multicast mask registers 8 1b registers sequence */
82
83 TSD0 = 0x10, /**< Transmit status of descriptor 0 */
84 TSD1 = 0x14, /**< Transmit status of descriptor 1 */
85 TSD2 = 0x18, /**< Transmit status of descriptor 2 */
86 TSD3 = 0x1C, /**< Transmit status of descriptor 3 */
87
88 TSAD0 = 0x20, /**< Physical address of the 1st transmitter buffer, 4b */
89 TSAD1 = 0x24, /**< Physical address of the 2nd transmitter buffer, 4b */
90 TSAD2 = 0x28, /**< Physical address of the 3rd transmitter buffer, 4b */
91 TSAD3 = 0x3C, /**< Physical address of the 4th transmitter buffer, 4b */
92
93 RBSTART = 0x30, /**< Receive (Rx) buffer start address, 4b */
94 ERBCR = 0x34, /**< Early receive (Rx) byte count register, 2b */
95 ERSR = 0x36, /**< Early receive (Rx) status register, 1b */
96
97 CR = 0x37, /**< Command register, 1b */
98 CAPR = 0x38, /**< Current address of frame read, 2b */
99 CBA = 0x3a, /**< Current buffer address, 2b */
100
101 IMR = 0x3c, /**< Interrupt mask register, 2b */
102 ISR = 0x3e, /**< Interrupt status register, 2b */
103
104 TCR = 0x40, /**< Transmit (Tx) configuration register, 4b */
105 RCR = 0x44, /**< Receive (Rx) configuration register, 4b */
106
107 TCTR = 0x48, /**< Timer count register */
108 MPC = 0x4c, /**< Missed packet count */
109
110 CR9346 = 0x50, /**< 93C46 command register (locking of registers) */
111
112 CONFIG0 = 0x51, /**< Configuration register 0, 1b */
113 CONFIG1 = 0x52, /**< Configuration register 1, 1b */
114
115 // 0x53 reserved
116
117 TIMERINT = 0x54, /**< Timer interrupt register, 4b */
118 MSR = 0x58, /**< Media status register, 1b */
119
120 CONFIG3 = 0x59, /**< Configuration register 3, 1b */
121 CONFIG4 = 0x5a, /**< Configuration register 4, 1b */
122
123 // 0x5b reserved
124
125 MULINT = 0x5c, /**< Multiple interrupt select, 2b */
126 RERID = 0x5e, /**< PCI revision ID = 0x10, 1b */
127
128 // 0x5f reserved
129
130 TSALLD = 0x60, /**< Transmit status of all descriptors, 2b */
131
132 BMCR = 0x62, /**< Basic mode control register */
133 BMSR = 0x64, /**< Basic mode status register */
134
135 ANAR = 0x66, /**< Auto-negotiation advertisement register */
136 ANLPAR = 0x68, /**< Auto-negotiation link partner register */
137 ANER = 0x6a, /**< Auto-negotiation expansion register */
138 DIS = 0x6c, /**< Disconnect counter */
139 FCSC = 0x6e, /**< False carrier sense counter */
140 NWAYTR = 0x70, /**< n-way test register */
141 REC = 0x72, /**< RX_ER counter */
142 CSCR = 0x74, /**< CS configuration register */
143
144 // 0x76 - 0x77 reserved
145
146 PHY1_PARM = 0x78, /**< PHY parameter 1 */
147 TW_PARM = 0x7c, /**< Twister parameter */
148 PHY2_PARM = 0x80, /**< PHY parameter 2 */
149
150 // 0x81 reserved
151
152 TDOKLA = 0x82, /**< Low Address of a Tx Descriptor with Tx DMA Ok */
153 CRC0 = 0x84, /**< Power Management CRC register0 for wakeup frame 0 */
154 WAKEUP0 = 0x8c, /**< Power Management wakeup frame 0 */
155 LSBCRC0 = 0xcc, /**< Least significant masked byte of WF0 */
156 FLASH = 0xd4, /**< Flash memory read/write register */
157
158 CONFIG5 = 0xd8, /**< Configuration register 5 */
159
160 TPPOL = 0xd9, /**< Transmit priority polling register */
161
162 // 0xda - 0xdf reserved
163
164 CPCR = 0xe0, /**< C+ mode command register */
165
166 // 0xe2 - 0xe3 reserved
167
168 RDSAR = 0xe4, /**< Receive Descriptor Start Address Register */
169 ETTHR = 0xec, /**< Early transmit threshold register */
170
171 // 0xed - 0xef reserved
172
173 FER = 0xf0, /**< Function event register */
174 FEMR = 0xf4, /**< Function event mask register */
175 FPSR = 0xf8, /**< Function present state register */
176 FFER = 0xfc, /**< Function force event register */
177 MIIR = 0xfc /**< MII register */
178};
179
180/** Mask of valid bits in MPC value */
181#define MPC_VMASK UINT32_C(0xFFFFFF);
182
183/** Command register bits */
184enum rtl8139_cr {
185 CR_BUFE = (1 << 0), /**< Buffer empty bit - read only */
186 CR_TE = (1 << 2), /**< Transmitter enable bit */
187 CR_RE = (1 << 3), /**< Receiver enable bit */
188 CR_RST = (1 << 4) /**< Reset - set to 1 to force software reset */
189};
190
191/** Config1 register bits */
192enum rtl8139_config1 {
193 CONFIG1_LEDS_SHIFT = 6, /**< Shift of CONFIG1_LEDS bits */
194 CONFIG1_LEDS_SIZE = 2, /**< Size of CONFIG1_LEDS bits */
195
196 CONFIG1_DVRLOAD = (1 << 5), /**< Driver load */
197 CONFIG1_LWACT = (1 << 4), /**< LWAKE active mode */
198 CONFIG1_MEMMAP = (1 << 3), /**< Memory mapping */
199 CONFIG1_IOMAP = (1 << 2), /**< I/O space mapping */
200 CONFIG1_VPD = (1 << 1), /**< Set to enable Vital Product Data */
201 CONFIG1_PMEn = (1 << 0) /**< Power management enabled */
202};
203
204/** Mask of 9346CR register for lock configuration registers */
205#define RTL8139_REGS_LOCKED 0
206/** Mask of 9346CR register for unlock configuration registers */
207#define RTL8139_REGS_UNLOCKED 0xC0
208
209/** Put rtl8139 to normal mode.
210 *
211 * Writing to Config0-4 and part of BMCR registers is not allowed
212 */
213static inline void rtl8139_regs_lock(void *io_base)
214{
215 pio_write_8(io_base + CR9346, RTL8139_REGS_LOCKED);
216}
217
218/** Allow to change Config0-4 and BMCR register */
219static inline void rtl8139_regs_unlock(void *io_base)
220{
221 pio_write_8(io_base + CR9346, RTL8139_REGS_UNLOCKED);
222}
223
224/** Force soft reset of the chip. After it:
225 * receiver and transmitter are disabled
226 * transmitter FIFO is cleared
227 * transmitter buffer is set to TSDA0
228 * receiver buffer is empty
229 *
230 * The reset bit in command register must be set to 1, the value of the
231 * the register is 1 during reset operation
232 *
233 * @param base_port The base address of the port mappings
234 */
235#define rtl8139_hw_reset(base_port)\
236 {\
237 pio_write_8(base_port + CR, CR_RST);\
238 while((pio_read_8(base_port + CR) & CR_RST) != 0);\
239 }
240
241/** Interrupt_masks
242 *
243 * The masks are the same for both IMR and ISR
244 */
245enum rtl8139_interrupts {
246 INT_SERR = (1 << 15), /**< System error interrupt */
247 INT_TIME_OUT = (1 << 14), /**< Time out interrupt */
248 INT_LENGTH_CHANGE = (1 << 13), /**< Cable length change interrupt */
249
250 /* bits 7 - 12 reserved */
251
252 INT_FIFOOVW = (1 << 6), /**< Receiver FIFO overflow interrupt */
253 INT_PUN = (1 << 5), /**< Packet Underrun/Link Change Interrupt */
254 INT_RXOVW = (1 << 4), /**< Receiver buffer overflow */
255 INT_TER = (1 << 3), /**< Transmit error interrupt */
256 INT_TOK = (1 << 2), /**< Transmit OK interrupt */
257 INT_RER = (1 << 1), /**< Receive error interrupt */
258 INT_ROK = (1 << 0) /**< Receive OK interrupt */
259};
260
261/** Transmit status descriptor registers bits */
262enum rtl8139_tsd {
263 TSD_CRS = (1 << 31), /**< Carrier Sense Lost */
264 TSD_TABT = (1 << 30), /**< Transmit Abort */
265 TSD_OWC = (1 << 29), /**< Out of Window Collision */
266 TSD_CDH = (1 << 28), /**< CD Heart Beat */
267 TSD_NCC_SHIFT = 24, /**< Collision Count - bit shift */
268 TSD_NCC_SIZE = 4, /**< Collision Count - bit size */
269 TSD_NCC_MASK = (1 << 4) - 1, /**< Collision Count - bit size */
270 TSD_ERTXTH_SHIFT = 16, /**< Early Tx Threshold - bit shift */
271 TSD_ERTXTH_SIZE = 6, /**< Early Tx Treshold - bit size */
272 TSD_TOK = (1 << 15), /**< Transmit OK */
273 TSD_TUN = (1 << 14), /**< Transmit FIFO Underrun */
274 TSD_OWN = (1 << 13), /**< OWN */
275 TSD_SIZE_SHIFT = 0, /**< Size - bit shift */
276 TSD_SIZE_SIZE = 13, /**< Size - bit size */
277 TSD_SIZE_MASK = 0x1fff /**< Size - bit mask */
278};
279
280/** Receiver control register values */
281enum rtl8139_rcr {
282 /** Early Rx treshold part shift */
283 RCR_ERTH_SHIFT = 24,
284 /** Early Rx treshold part size */
285 RCR_ERTH_SIZE = 4,
286
287 /** Multiple early interrupt select */
288 RCR_MulERINT = 1 << 17,
289
290 /** Minimal error frame length (1 = 8B, 0 = 64B).
291 * If AER/AR is set, RER8 is "Don't care"
292 */
293 RCR_RER8 = 1 << 16,
294
295 /** Rx FIFO treshold part shift */
296 RCR_RXFTH_SHIFT = 13,
297 /** Rx FIFO treshold part size */
298 RCR_RXFTH_SIZE = 3,
299
300 /** Rx buffer length part shift */
301 RCR_RBLEN_SHIFT = 11,
302 /** Rx buffer length part size */
303 RCR_RBLEN_SIZE = 2,
304
305 /** 8K + 16 byte rx buffer */
306 RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT,
307 /** 16K + 16 byte rx buffer */
308 RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT,
309 /** 32K + 16 byte rx buffer */
310 RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT,
311 /** 64K + 16 byte rx buffer */
312 RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT,
313
314 /** Max DMA Burst Size part shift */
315 RCR_MXDMA_SHIFT = 8,
316 /** Max DMA Burst Size part size */
317 RCR_MXDMA_SIZE = 3,
318
319 /** Rx buffer wrapped */
320 RCR_WRAP = 1 << 7,
321 /** Accept error frame */
322 RCR_ACCEPT_ERROR = 1 << 5,
323 /** Accept Runt (8-64 bytes) frames */
324 RCR_ACCEPT_RUNT = 1 << 4,
325 /** Accept broadcast */
326 RCR_ACCEPT_BROADCAST = 1 << 3,
327 /** Accept multicast */
328 RCR_ACCEPT_MULTICAST = 1 << 2,
329 /** Accept device MAC address match */
330 RCR_ACCEPT_PHYS_MATCH = 1 << 1,
331 /** Accept all frames with phys. destination */
332 RCR_ACCEPT_ALL_PHYS = 1 << 0,
333 /** Mask of accept part */
334 RCR_ACCEPT_MASK = (1 << 6) - 1
335};
336
337/** CSCR register bits */
338enum rtl8139_cscr {
339 CS_Testfun = (1 << 15),
340 /** Low TPI link disable signal */
341 CS_LD = (1 << 9),
342 /** Heart beat enable; 10Mbit mode only */
343 CS_HEART_BEAT = (1 << 8),
344 /** Enable jabber function */
345 CS_JABBER_ENABLE = (1 << 7),
346 CS_F_LINK100 = (1 << 6),
347 CS_F_CONNECT = (1 << 5),
348 /** connection status: 1 = valid, 0 = disconnected */
349 CS_CON_STATUS = (1 << 3),
350 /** LED1 pin connection status indication */
351 CS_CON_STATUS_EN = (1 << 2),
352 /** Bypass Scramble */
353 CS_PASS_SCR = (1 << 0)
354};
355
356/** MSR register bits */
357enum rtl8139_msr {
358 MSR_TXFCE = (1 << 7), /**< Transmitter flow control enable */
359 MSR_RXFCE = (1 << 6), /**< Receiver flow control enable */
360
361 MSR_AUX_PRESENT = (1 << 4), /**< Aux. Power present Status */
362 MSR_SPEED10 = (1 << 3), /**< 10MBit mode sign (1 = 10Mb, 0 = 100Mb) */
363 MSR_LINKB = (1 << 2), /**< Link Bad (fail) */
364 MSR_TXPF = (1 << 1), /**< Transmitter pause flag */
365 MSR_RXPF = (1 << 0) /**< Receiver pause flag */
366};
367
368/** BMCR register bits (basic mode control register) */
369enum rtl8139_bmcr {
370 BMCR_Reset = (1 << 15), /**< Software reset */
371 BMCR_Spd_100 = (1 << 13), /**< 100 MBit mode set, 10 MBit otherwise */
372 BMCR_AN_ENABLE = (1 << 12), /**< Autonegotion enable */
373
374 /* 10,11 reserved */
375
376 BMCR_AN_RESTART = (1 << 9), /**< Restart autonegotion */
377 BMCR_DUPLEX = (1 << 8) /**< Duplex mode: 1=full duplex */
378
379 /* 0-7 reserved */
380};
381
382/** Auto-negotiation advertisement register */
383enum rtl8139_anar {
384 /** Next page bit, 0 - primary capability, 1 - protocol specific */
385 ANAR_NEXT_PAGE = (1 << 15),
386 /** Capability reception acknowledge */
387 ANAR_ACK = (1 << 14),
388 /** Remote fault detection capability */
389 ANAR_REMOTE_FAULT = (1 << 13),
390 /** Symetric pause frame capability */
391 ANAR_PAUSE = (1 << 10),
392 /** T4, not supported by the device */
393 ANAR_100T4 = (1 << 9),
394 /** 100BASE_TX full duplex */
395 ANAR_100TX_FD = (1 << 8),
396 /** 100BASE_TX half duplex */
397 ANAR_100TX_HD = (1 << 7),
398 /** 10BASE_T full duplex */
399 ANAR_10_FD = (1 << 6),
400 /** 10BASE_T half duplex */
401 ANAR_10_HD = (1 << 5),
402 /** Selector, CSMA/CD (0x1) supported only */
403 ANAR_SELECTOR = 0x1
404};
405
406/** Autonegotiation expansion register bits */
407enum rtl8139_aner {
408 ANER_MFL = (1 << 4), /**< Multiple link fault occured */
409 ANER_LP_NP_ABLE = (1 << 3), /**< Link parent supports next page */
410 ANER_NP_ABLE = (1 << 2), /**< Local node is able to send next pages */
411 ANER_PAGE_RX = (1 << 1), /** New page received, cleared on LPAR read */
412 ANER_LP_NW_ABLE = (1 << 0) /**< Link partner autonegotiation support */
413};
414
415enum rtl8139_config5 {
416 CONFIG5_BROADCAST_WAKEUP = (1 << 6), /**< Broadcast wakeup frame enable */
417 CONFIG5_MULTICAST_WAKEUP = (1 << 5), /**< Multicast wakeup frame enable */
418 CONFIG5_UNICAST_WAKEUP = (1 << 4), /**< Unicast wakeup frame enable */
419
420 /** Descending/ascending grow of Rx/Tx FIFO (to test FIFO SRAM only) */
421 CONFIG5_FIFO_ADDR_PTR = (1 << 3),
422 /** Powersave if cable is disconnected */
423 CONFIG5_LINK_DOWN_POWERSAVE = (1 << 2),
424
425 CONFIG5_LAN_WAKE = (1 << 1), /**< LANWake signal enabled */
426 CONFIG5_PME_STATUS = (1 << 0) /**< PMEn change: 0 = SW, 1 = SW+PCI */
427};
428
429enum rtl8139_config3 {
430 CONFIG3_GNT_SELECT = (1 << 7), /**< Gnt select */
431 CONFIG3_PARM_EN = (1 << 6), /**< Parameter enabled (100MBit mode) */
432 CONFIG3_MAGIC = (1 << 5), /**< WoL Magic frame enable */
433 CONFIG3_LINK_UP = (1 << 4), /**< Wakeup if link is reestablished */
434 CONFIG3_CLKRUN_EN = (1 << 2), /**< CLKRUN enabled */ /* TODO: check what does it mean */
435 CONFIG3_FBTBEN = (1 << 0) /**< Fast back to back enabled */
436};
437
438enum rtl8139_config4 {
439 /** Automatic RxFIFO owerflow clear */
440 CONFIG4_RxFIFOAutoClr = (1 << 7),
441 /** Analog poweroff */
442 CONFIG4_AnaOff = (1 << 6),
443 /** Long wakeup frame (2xCRC8 + 3xCRC16) */
444 CONFIG4_LongWF = (1 << 5),
445 /** LWAKE and PMEB assertion */
446 CONFIG4_LWPME = (1 << 4),
447 /** LWake pattern */
448 CONFIG4_LWPTN = (1 << 2),
449 /** Preboot wakeup */
450 CONFIG4_PBWakeup = (1 << 0)
451};
452
453/** Maximal runt frame size + 1 */
454#define RTL8139_RUNT_MAX_SIZE 64
455
456/** Bits in frame header */
457enum rtl8139_frame_header {
458 RSR_MAR = (1 << 15), /**< Multicast received */
459 RSR_PAM = (1 << 14), /**< Physical address match */
460 RSR_BAR = (1 << 13), /**< Broadcast match */
461
462 RSR_ISE = (1 << 5), /**< Invalid symbol error, 100BASE-TX only */
463 RSR_RUNT = (1 << 4), /**< Runt frame (< RTL8139_RUNT_MAX_SIZE bytes) */
464
465 RSR_LONG = (1 << 3), /**< Long frame (size > 4k bytes) */
466 RSR_CRC = (1 << 2), /**< CRC error */
467 RSR_FAE = (1 << 1), /**< Frame alignment error */
468 RSR_ROK = (1 << 0) /**< Good frame received */
469};
470
471enum rtl8139_tcr_bits {
472 /** HW version id, part A shift */
473 HWVERID_A_SHIFT = 26,
474 /** HW version id, part A bit size */
475 HWVERID_A_SIZE = 5,
476 /** HW version id, part A mask */
477 HWVERID_A_MASK = (1 << 5) - 1,
478
479 /** The interframe gap time setting shift */
480 IFG_SHIFT = 24,
481 /** The interframe gap time setting bit size */
482 IFG_SIZE = 2,
483
484 /** HW version id, part B shift */
485 HWVERID_B_SHIFT = 22,
486 /** HW version id, part B bit size */
487 HWVERID_B_SIZE = 2,
488 /** HW version id, part B mask */
489 HWVERID_B_MASK = (1 << 2) - 1,
490
491 /** Loopback mode shift */
492 LOOPBACK_SHIFT = 17,
493 /** Loopback mode size. 00 = normal, 11 = loopback */
494 LOOPBACK_SIZE = 2,
495
496 /** Append CRC at the end of a frame */
497 APPEND_CRC = 1 << 16,
498
499 /** Max. DMA Burst per TxDMA shift, burst = 16^value */
500 MXTxDMA_SHIFT = 8,
501 /** Max. DMA Burst per TxDMA bit size */
502 MXTxDMA_SIZE = 3,
503
504 /** Retries before aborting shift */
505 TX_RETRY_COUNT_SHIFT = 4,
506 /** Retries before aborting size */
507 TX_RETRY_COUNT_SIZE = 4,
508
509 /** Retransmit aborted frame at the last transmitted descriptor */
510 CLEAR_ABORT = 1 << 0
511};
512
513#define RTL8139_HWVERID_A(tcr) (((tcr) >> HWVERID_A_SHIFT) & HWVERID_A_MASK)
514#define RTL8139_HWVERID_B(tcr) (((tcr) >> HWVERID_B_SHIFT) & HWVERID_B_MASK)
515#define RTL8139_HWVERID(tcr) ((RTL8139_HWVERID_A(tcr) << HWVERID_B_SIZE) | \
516 RTL8139_HWVERID_B(tcr))
517
518/** Mapping of HW version -> version ID */
519struct rtl8139_hwver_map {
520 uint32_t hwverid; /**< HW version value in the register */
521 rtl8139_version_id_t ver_id; /**< appropriate version id */
522};
523
524/** Mapping of HW version -> version ID */
525extern const struct rtl8139_hwver_map rtl8139_versions[RTL8139_VER_COUNT + 1];
526extern const char *model_names[RTL8139_VER_COUNT];
527
528/** Size in the frame header while copying from RxFIFO to Rx buffer */
529#define RTL8139_EARLY_SIZE UINT16_C(0xfff0)
530
531/** The only supported pause frame time value */
532#define RTL8139_PAUSE_VAL UINT16_C(0xFFFF)
533
534/** Size of the frame header in front of the received frame */
535#define RTL_FRAME_HEADER_SIZE 4
536
537/** 8k buffer */
538#define RTL8139_RXFLAGS_SIZE_8 0
539/** 16k buffer */
540#define RTL8139_RXFLAGS_SIZE_16 1
541/** 32k buffer */
542#define RTL8139_RXFLAGS_SIZE_32 2
543/** 64k buffer */
544#define RTL8139_RXFLAGS_SIZE_64 3
545
546/** Get the buffer initial size without 16B padding
547 * Size is (8 + 2^flags) kB (^ in mean power)
548 *
549 * @param flags The flags for Rx buffer size, 0-3
550 */
551#define RTL8139_RXSIZE(flags) (1 << (13 + (flags)))
552
553/** Padding of the receiver buffer */
554#define RTL8139_RXBUF_PAD 16
555/** Size needed for buffer allocation */
556#define RTL8139_RXBUF_LENGTH(flags) (RTL8139_RXSIZE(flags) + RTL8139_RXBUF_PAD)
557
558#endif
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