source: mainline/uspace/drv/nic/rtl8139/defs.h@ d8da56b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d8da56b was 1bc35b5, checked in by Jiri Svoboda <jiri@…>, 14 years ago

Remove most use of packet_t from NIC drivers.
  • Property mode set to 100644
File size: 19.4 KB
RevLine 
[bf84871]1/*
2 * Copyright (c) 2011 Jiri Michalec
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file rtl8139_defs.h
30 *
31 * Registers, bit positions and masks definition of the RTL8139 network family
32 * cards
33 */
34
35#ifndef RTL8139_DEFS_H_INCLUDED_
36#define RTL8139_DEFS_H_INCLUDED_
37#include <sys/types.h>
38#include <libarch/ddi.h>
39
40
41/** The size of RTL8139 registers address space */
42#define RTL8139_IO_SIZE 256
43
[1bc35b5]44/** The maximal transmitted frame length in bytes allowed according to RTL8139
[bf84871]45 * documentation (see SIZE part of TSD documentation)
46 */
[1bc35b5]47#define RTL8139_FRAME_MAX_LENGTH 1792
[bf84871]48
49
50/** HW version
51 *
52 * as can be detected from HWVERID part of TCR
53 * (Transmit Configuration Register)
54 */
55enum rtl8139_version_id {
56 RTL8139 = 0, /**< RTL8139 */
57 RTL8139A, /**< RTL8139A */
58 RTL8139A_G, /**< RTL8139A-G */
59 RTL8139B, /**< RTL8139B */
60 RTL8130, /**< RTL8130 */
61 RTL8139C, /**< RTL8139C */
62 RTL8100, /**< RTL8100 */
63 RTL8139Cp, /**< RTL8139C+ */
64 RTL8139D, /**< RTL8139D */
65 RTL8100B = RTL8139D, /**< RTL8100B and RTL8139D, the same HWVERID in TCR */
66 RTL8101, /**< RTL8101 */
67 RTL8139_VER_COUNT /**< Count of known RTL versions, the last value */
68};
69
70extern const char* model_names[RTL8139_VER_COUNT];
71
72/** Registers of RTL8139 family card offsets from the memory address base */
73enum rtl8139_registers {
74 IDR0 = 0x00, /**< First MAC address bit, 6 1b registres sequence */
75 MAC0 = IDR0, /**< Alias for IDR0 */
76
77 // 0x6 - 0x7 reserved
78
79 MAR0 = 0x08, /**< Multicast mask registers 8 1b registers sequence */
80
81 TSD0 = 0x10, /**< Transmit status of descriptor 0 */
82 TSD1 = 0x14, /**< Transmit status of descriptor 1 */
83 TSD2 = 0x18, /**< Transmit status of descriptor 2 */
84 TSD3 = 0x1C, /**< Transmit status of descriptor 3 */
85
86 TSAD0 = 0x20, /**< Physical address of the 1st transmitter buffer, 4b */
87 TSAD1 = 0x24, /**< Physical address of the 2nd transmitter buffer, 4b */
88 TSAD2 = 0x28, /**< Physical address of the 3rd transmitter buffer, 4b */
89 TSAD3 = 0x3C, /**< Physical address of the 4th transmitter buffer, 4b */
90
91 RBSTART = 0x30, /**< Receive (Rx) buffer start address, 4b */
92 ERBCR = 0x34, /**< Early receive (Rx) byte count register, 2b */
93 ERSR = 0x36, /**< Early receive (Rx) status register, 1b */
94
95 CR = 0x37, /**< Command register, 1b */
[1bc35b5]96 CAPR = 0x38, /**< Current address of frame read, 2b */
[bf84871]97 CBA = 0x3a, /**< Current buffer address, 2b */
98
99 IMR = 0x3c, /**< Interrupt mask register, 2b */
100 ISR = 0x3e, /**< Interrupt status register, 2b */
101
102 TCR = 0x40, /**< Transmit (Tx) configuration register, 4b */
103 RCR = 0x44, /**< Receive (Rx) configuration register, 4b */
104
105 TCTR = 0x48, /**< Timer count register */
106 MPC = 0x4c, /**< Missed packet count */
107
108 CR9346 = 0x50, /**< 93C46 command register (locking of registers) */
109
110 CONFIG0 = 0x51, /**< Configuration register 0, 1b */
111 CONFIG1 = 0x52, /**< Configuration register 1, 1b */
112
113 // 0x53 reserved
114
115 TIMERINT = 0x54, /**< Timer interrupt register, 4b */
116 MSR = 0x58, /**< Media status register, 1b */
117
118 CONFIG3 = 0x59, /**< Configuration register 3, 1b */
119 CONFIG4 = 0x5a, /**< Configuration register 4, 1b */
120
121 // 0x5b reserved
122
123 MULINT = 0x5c, /**< Multiple interrupt select, 2b */
124 RERID = 0x5e, /**< PCI revision ID = 0x10, 1b */
125
126 // 0x5f reserved
127
128 TSALLD = 0x60, /**< Transmit status of all descriptors, 2b */
129
130 BMCR = 0x62, /**< Basic mode control register */
131 BMSR = 0x64, /**< Basic mode status register */
132
133 ANAR = 0x66, /**< Auto-negotiation advertisement register */
134 ANLPAR = 0x68, /**< Auto-negotiation link partner register */
135 ANER = 0x6a, /**< Auto-negotiation expansion register */
136 DIS = 0x6c, /**< Disconnect counter */
137 FCSC = 0x6e, /**< False carrier sense counter */
138 NWAYTR = 0x70, /**< n-way test register */
139 REC = 0x72, /**< RX_ER counter */
140 CSCR = 0x74, /**< CS configuration register */
141
142 // 0x76 - 0x77 reserved
143
144 PHY1_PARM = 0x78, /**< PHY parameter 1 */
145 TW_PARM = 0x7c, /**< Twister parameter */
146 PHY2_PARM = 0x80, /**< PHY parameter 2 */
147
148 // 0x81 reserved
149
150 TDOKLA = 0x82, /**< Low Address of a Tx Descriptor with Tx DMA Ok */
151 CRC0 = 0x84, /**< Power Management CRC register0 for wakeup frame 0 */
152 WAKEUP0 = 0x8c, /**< Power Management wakeup frame 0 */
153 LSBCRC0 = 0xcc, /**< Least significant masked byte of WF0 */
154 FLASH = 0xd4, /**< Flash memory read/write register */
155
156 CONFIG5 = 0xd8, /**< Configuration register 5 */
157
158 TPPOL = 0xd9, /**< Transmit priority polling register */
159
160 // 0xda - 0xdf reserved
161
162 CPCR = 0xe0, /**< C+ mode command register */
163
164 // 0xe2 - 0xe3 reserved
165
166 RDSAR = 0xe4, /**< Receive Descriptor Start Address Register */
167 ETTHR = 0xec, /**< Early transmit threshold register */
168
169 // 0xed - 0xef reserved
170
171 FER = 0xf0, /**< Function event register */
172 FEMR = 0xf4, /**< Function event mask register */
173 FPSR = 0xf8, /**< Function present state register */
174 FFER = 0xfc, /**< Function force event register */
175 MIIR = 0xfc /**< MII register */
176};
177
178/** Mask of valid bits in MPC value */
179#define MPC_VMASK UINT32_C(0xFFFFFF);
180
181/** Command register bits */
182enum rtl8139_cr {
183 CR_BUFE = (1 << 0), /**< Buffer empty bit - read only */
184 CR_TE = (1 << 2), /**< Transmitter enable bit */
185 CR_RE = (1 << 3), /**< Receiver enable bit */
186 CR_RST = (1 << 4) /**< Reset - set to 1 to force software reset */
187};
188
189/** Config1 register bits */
190enum rtl8139_config1 {
191 CONFIG1_LEDS_SHIFT = 6, /**< Shift of CONFIG1_LEDS bits */
192 CONFIG1_LEDS_SIZE = 2, /**< Size of CONFIG1_LEDS bits */
193
194 CONFIG1_DVRLOAD = (1 << 5), /**< Driver load */
195 CONFIG1_LWACT = (1 << 4), /**< LWAKE active mode */
196 CONFIG1_MEMMAP = (1 << 3), /**< Memory mapping */
197 CONFIG1_IOMAP = (1 << 2), /**< I/O space mapping */
198 CONFIG1_VPD = (1 << 1), /**< Set to enable Vital Product Data */
199 CONFIG1_PMEn = (1 << 0) /**< Power management enabled */
200};
201
202/** Mask of 9346CR register for lock configuration registers */
203#define RTL8139_REGS_LOCKED 0
204/** Mask of 9346CR register for unlock configuration registers */
205#define RTL8139_REGS_UNLOCKED 0xC0
206
207/** Put rtl8139 to normal mode.
208 *
209 * Writing to Config0-4 and part of BMCR registers is not allowed
210 */
211static inline void rtl8139_regs_lock(void *io_base)
212{
213 pio_write_8(io_base + CR9346, RTL8139_REGS_LOCKED);
214}
215/** Allow to change Config0-4 and BMCR register */
216static inline void rtl8139_regs_unlock(void *io_base)
217{
218 pio_write_8((io_base) + CR9346, RTL8139_REGS_UNLOCKED);
219}
220
221/** Force soft reset of the chip. After it:
222 * receiver and transmitter are disabled
223 * transmitter FIFO is cleared
224 * transmitter buffer is set to TSDA0
225 * receiver buffer is empty
226 *
227 * The reset bit in command register must be set to 1, the value of the
228 * the register is 1 during reset operation
229 *
230 * @param base_port The base address of the port mappings
231 */
232#define rtl8139_hw_reset(base_port)\
233 {\
234 pio_write_8(base_port + CR, CR_RST);\
235 while((pio_read_8(base_port + CR) & CR_RST) != 0);\
236 }
237
238/** Interrupt_masks
239 *
240 * The masks are the same for both IMR and ISR
241 */
242enum rtl8139_interrupts {
243 INT_SERR = (1 << 15), /**< System error interrupt */
244 INT_TIME_OUT = (1 << 14), /**< Time out interrupt */
245 INT_LENGTH_CHANGE = (1 << 13), /**< Cable length change interrupt */
246
247 /* bits 7 - 12 reserved */
248
249 INT_FIFOOVW = (1 << 6), /**< Receiver FIFO overflow interrupt */
250 INT_PUN = (1 << 5), /**< Packet Underrun/Link Change Interrupt */
251 INT_RXOVW = (1 << 4), /**< Receiver buffer overflow */
252 INT_TER = (1 << 3), /**< Transmit error interrupt */
253 INT_TOK = (1 << 2), /**< Transmit OK interrupt */
254 INT_RER = (1 << 1), /**< Receive error interrupt */
255 INT_ROK = (1 << 0) /**< Receive OK interrupt */
256};
257
258/** Transmit status descriptor registers bits */
259enum rtl8139_tsd {
260 TSD_CRS = (1 << 31), /**< Carrier Sense Lost */
261 TSD_TABT = (1 << 30), /**< Transmit Abort */
262 TSD_OWC = (1 << 29), /**< Out of Window Collision */
263 TSD_CDH = (1 << 28), /**< CD Heart Beat */
264 TSD_NCC_SHIFT = 24, /**< Collision Count - bit shift */
265 TSD_NCC_SIZE = 4, /**< Collision Count - bit size */
266 TSD_NCC_MASK = (1 << 4)-1, /**< Collision Count - bit size */
267 TSD_ERTXTH_SHIFT = 16, /**< Early Tx Threshold - bit shift */
268 TSD_ERTXTH_SIZE = 6, /**< Early Tx Treshold - bit size */
269 TSD_TOK = (1 << 15), /**< Transmit OK */
270 TSD_TUN = (1 << 14), /**< Transmit FIFO Underrun */
271 TSD_OWN = (1 << 13), /**< OWN */
272 TSD_SIZE_SHIFT = 0, /**< Size - bit shift */
273 TSD_SIZE_SIZE = 13, /**< Size - bit size */
274 TSD_SIZE_MASK = 0x1fff /**< Size - bit mask */
275};
276
277/** Receiver control register values */
278enum rtl8139_rcr {
279 RCR_ERTH_SHIFT = 24, /**< Early Rx treshold part shift */
280 RCR_ERTH_SIZE = 4, /**< Early Rx treshold part size */
281
282 RCR_MulERINT = 1 << 17, /**< Multiple early interrupt select */
283
[1bc35b5]284 /** Minimal error frame length (1 = 8B, 0 = 64B). If AER/AR is set, RER8
[bf84871]285 * is "Don't care"
286 */
287 RCR_RER8 = 1 << 16,
288
289 RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */
290 RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */
291
292 RCR_RBLEN_SHIFT = 11, /**< Rx buffer length part shift */
293 RCR_RBLEN_SIZE = 2, /**< Rx buffer length part size */
294
295 RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, /**< 8K + 16 byte rx buffer */
296 RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, /**< 16K + 16 byte rx buffer */
297 RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, /**< 32K + 16 byte rx buffer */
298 RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, /**< 64K + 16 byte rx buffer */
299
300 RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */
301 RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */
302
303 RCR_WRAP = 1 << 7, /**< Rx buffer wrapped */
[1bc35b5]304 RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error frame */
305 RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) frames */
[bf84871]306 RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */
307 RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */
308 RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */
[1bc35b5]309 RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all frames with
[bf84871]310 * phys. desticnation
311 */
312 RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */
313};
314
315
316/** CSCR register bits */
317enum rtl8139_cscr {
318 CS_Testfun = (1 << 15),
319 CS_LD = (1 << 9), /**< Low TPI link disable signal */
320 CS_HEART_BEAT = (1 << 8), /**< Heart beat enable; 10Mbit mode only */
321 CS_JABBER_ENABLE = (1 << 7), /**< Enable jabber function */
322 CS_F_LINK100 = (1 << 6),
323 CS_F_CONNECT = (1 << 5),
324 CS_CON_STATUS = (1 << 3), /**< connection status:
325 * 1 = valid, 0 = disconnected
326 */
327 CS_CON_STATUS_EN = (1 << 2), /**< LED1 pin connection status indication */
328 CS_PASS_SCR = (1 << 0) /**< Bypass Scramble */
329};
330
331/** MSR register bits */
332enum rtl8139_msr {
333 MSR_TXFCE = (1 << 7), /**< Transmitter flow control enable */
334 MSR_RXFCE = (1 << 6), /**< Receiver flow control enable */
335
336 MSR_AUX_PRESENT = (1 << 4), /**< Aux. Power present Status */
337 MSR_SPEED10 = (1 << 3), /**< 10MBit mode sign (1 = 10Mb, 0 = 100Mb) */
338 MSR_LINKB = (1 << 2), /**< Link Bad (fail) */
339 MSR_TXPF = (1 << 1), /**< Transmitter pause flag */
340 MSR_RXPF = (1 << 0) /**< Receiver pause flag */
341};
342
343/** BMCR register bits (basic mode control register) */
344enum rtl8139_bmcr {
345 BMCR_Reset = (1 << 15), /**< Software reset */
346 BMCR_Spd_100 = (1 << 13), /**< 100 MBit mode set, 10 MBit otherwise */
347 BMCR_AN_ENABLE = (1 << 12), /**< Autonegotion enable */
348
349 /* 10,11 reserved*/
350
351 BMCR_AN_RESTART = (1 << 9), /**< Restart autonegotion */
352 BMCR_DUPLEX = (1 << 8) /**< Duplex mode: 1=full duplex */
353
354 /* 0-7 reserved */
355};
356
357/** Auto-negotiation advertisement register */
358enum rtl8139_anar {
359 ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability
360 * 1 - protocol specific
361 */
362 ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */
363 ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */
[1bc35b5]364 ANAR_PAUSE = (1 << 10), /**< Symetric pause frame capability */
[bf84871]365 ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */
366 ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */
367 ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */
368 ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */
369 ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */
370 ANAR_SELECTOR = 0x1 /**< Selector,
371 * CSMA/CD (0x1) supported only
372 */
373};
374
375/** Autonegotiation expansion register bits */
376enum rtl8139_aner {
377 ANER_MFL = (1 << 4), /**< Multiple link fault occured */
378 ANER_LP_NP_ABLE = (1 << 3), /**< Link parent supports next page */
379 ANER_NP_ABLE = (1 << 2), /**< Local node is able to send next pages */
380 ANER_PAGE_RX = (1 << 1), /** New page received, cleared on LPAR read */
381 ANER_LP_NW_ABLE = (1 << 0) /**< Link partner autonegotiation support */
382};
383
384enum rtl8139_config5 {
385 CONFIG5_BROADCAST_WAKEUP = (1 << 6), /**< Broadcast wakeup frame enable */
386 CONFIG5_MULTICAST_WAKEUP = (1 << 5), /**< Multicast wakeup frame enable */
387 CONFIG5_UNICAST_WAKEUP = (1 << 4), /**< Unicast wakeup frame enable */
388
389 /** Descending/ascending grow of Rx/Tx FIFO (to test FIFO SRAM only) */
390 CONFIG5_FIFO_ADDR_PTR = (1 << 3),
391 /** Powersave if cable is disconnected */
392 CONFIG5_LINK_DOWN_POWERSAVE = (1 << 2),
393
394 CONFIG5_LAN_WAKE = (1 << 1), /**< LANWake signal enabled */
395 CONFIG5_PME_STATUS = (1 << 0) /**< PMEn change: 0 = SW, 1 = SW+PCI */
396};
397
398enum rtl8139_config3 {
399 CONFIG3_GNT_SELECT = (1 << 7), /**< Gnt select */
400 CONFIG3_PARM_EN = (1 << 6), /**< Parameter enabled (100MBit mode) */
[1bc35b5]401 CONFIG3_MAGIC = (1 << 5), /**< WoL Magic frame enable */
[bf84871]402 CONFIG3_LINK_UP = (1 << 4), /**< Wakeup if link is reestablished */
403 CONFIG3_CLKRUN_EN = (1 << 2), /**< CLKRUN enabled */ /* TODO: check what does it mean */
404 CONFIG3_FBTBEN = (1 << 0) /**< Fast back to back enabled */
405};
406
407enum rtl8139_config4 {
408 CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */
409 CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */
410 CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame
411 * (2xCRC8 + 3xCRC16)
412 */
413 CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */
414 CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */
415 CONFIG4_PBWakeup = (1 << 0) /**< Preboot wakeup */
416};
417
[1bc35b5]418/** Maximal runt frame size + 1 */
[bf84871]419#define RTL8139_RUNT_MAX_SIZE 64
420
[1bc35b5]421/** Bits in frame header */
422enum rtl8139_frame_header {
[bf84871]423 RSR_MAR = (1 << 15), /**< Multicast received */
424 RSR_PAM = (1 << 14), /**< Physical address match */
425 RSR_BAR = (1 << 13), /**< Broadcast match */
426
427 RSR_ISE = (1 << 5), /**< Invalid symbol error, 100BASE-TX only */
[1bc35b5]428 RSR_RUNT = (1 << 4), /**< Runt frame (< RTL8139_RUNT_MAX_SIZE bytes) */
[bf84871]429
[1bc35b5]430 RSR_LONG = (1 << 3), /**< Long frmae (size > 4k bytes) */
[bf84871]431 RSR_CRC = (1 << 2), /**< CRC error */
432 RSR_FAE = (1 << 1), /**< Frame alignment error */
[1bc35b5]433 RSR_ROK = (1 << 0) /**< Good frame received */
[bf84871]434};
435
436enum rtl8139_tcr_bits {
437 HWVERID_A_SHIFT = 26, /**< HW version id, part A shift */
438 HWVERID_A_SIZE = 5, /**< HW version id, part A bit size */
439 HWVERID_A_MASK = (1 << 5) - 1, /**< HW version id, part A mask */
440
441 IFG_SHIFT = 24, /**< The interframe gap time setting shift */
442 IFG_SIZE = 2, /**< The interframe gap time setting bit size */
443
444 HWVERID_B_SHIFT = 22, /**< HW version id, part B shift */
445 HWVERID_B_SIZE = 2, /**< HW version id, part B bit size */
446 HWVERID_B_MASK = (1 << 2) - 1, /**< HW version id, part B mask */
447
448 LOOPBACK_SHIFT = 17, /**< Loopback mode shift */
449 LOOPBACK_SIZE = 2, /**< Loopback mode size
450 * 00 = normal, 11 = loopback
451 */
452
[1bc35b5]453 APPEND_CRC = 1 << 16, /**< Append CRC at the end of a frame */
[bf84871]454
455 MXTxDMA_SHIFT = 8, /**< Max. DMA Burst per TxDMA shift, burst = 16^value */
456 MXTxDMA_SIZE = 3, /**< Max. DMA Burst per TxDMA bit size */
457
458 TX_RETRY_COUNT_SHIFT = 4, /**< Retries before aborting shift */
459 TX_RETRY_COUNT_SIZE = 4, /**< Retries before aborting size */
460
[1bc35b5]461 CLEAR_ABORT = 1 << 0 /**< Retransmit aborted frame at the last
[bf84871]462 * transmitted descriptor
463 */
464};
465
466#define RTL8139_HWVERID_A(tcr) (((tcr) >> HWVERID_A_SHIFT) & HWVERID_A_MASK)
467#define RTL8139_HWVERID_B(tcr) (((tcr) >> HWVERID_B_SHIFT) & HWVERID_B_MASK)
468#define RTL8139_HWVERID(tcr) ((RTL8139_HWVERID_A(tcr) << HWVERID_B_SIZE) | \
469 RTL8139_HWVERID_B(tcr))
470
471/** Mapping of HW version -> version ID */
472struct rtl8139_hwver_map {
473 uint32_t hwverid; /**< HW version value in the register */
474 enum rtl8139_version_id ver_id; /**< appropriate version id */
475};
476
477/** Mapping of HW version -> version ID */
478extern const struct rtl8139_hwver_map rtl8139_versions[RTL8139_VER_COUNT + 1];
479
[1bc35b5]480/** Size in the frame header while copying from RxFIFO to Rx buffer */
[bf84871]481#define RTL8139_EARLY_SIZE UINT16_C(0xfff0)
[1bc35b5]482/** The only supported pause frame time value */
[bf84871]483#define RTL8139_PAUSE_VAL UINT16_C(0xFFFF)
484
[1bc35b5]485/** Size of the frame header in front of the received frame */
486#define RTL_FRAME_HEADER_SIZE 4
[bf84871]487
488/** 8k buffer */
489#define RTL8139_RXFLAGS_SIZE_8 0
490/** 16k buffer */
491#define RTL8139_RXFLAGS_SIZE_16 1
492/** 32k buffer */
493#define RTL8139_RXFLAGS_SIZE_32 2
494/** 64k buffer */
495#define RTL8139_RXFLAGS_SIZE_64 3
496
497/** Get the buffer initial size without 16B padding
498 * Size is (8 + 2^flags) kB (^ in mean power)
499 *
500 * @param flags The flags for Rx buffer size, 0-3
501 */
502#define RTL8139_RXSIZE(flags) (1 << (13 + (flags)))
503
504/** Padding of the receiver buffer */
505#define RTL8139_RXBUF_PAD 16
506/** Size needed for buffer allocation */
507#define RTL8139_RXBUF_LENGTH(flags) (RTL8139_RXSIZE(flags) + RTL8139_RXBUF_PAD)
508
509#endif
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