source: mainline/uspace/drv/nic/e1k/e1k.c@ e882e3a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e882e3a was e882e3a, checked in by Jiri Svoboda <jiri@…>, 13 years ago

Remove include of devman.h where not needed.
  • Property mode set to 100644
File size: 55.7 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/log.h>
47#include <ddf/interrupt.h>
48#include <device/hw_res_parsed.h>
49#include <device/pci.h>
50#include <nic.h>
51#include <nil_remote.h>
52#include <ops/nic.h>
53#include "e1k.h"
54
55#define NAME "e1k"
56
57#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
58
59/* Must be power of 8 */
60#define E1000_RX_FRAME_COUNT 128
61#define E1000_TX_FRAME_COUNT 128
62
63#define E1000_RECEIVE_ADDRESS 16
64
65/** Maximum sending frame size */
66#define E1000_MAX_SEND_FRAME_SIZE 2048
67/** Maximum receiving frame size */
68#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
69
70/** nic_driver_data_t* -> e1000_t* cast */
71#define DRIVER_DATA_NIC(nic) \
72 ((e1000_t *) nic_get_specific(nic))
73
74/** device_t* -> nic_driver_data_t* cast */
75#define NIC_DATA_DEV(dev) \
76 ((nic_t *) ((dev)->driver_data))
77
78/** device_t* -> e1000_t* cast */
79#define DRIVER_DATA_DEV(dev) \
80 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
81
82/** Cast pointer to uint64_t
83 *
84 * @param ptr Pointer to cast
85 *
86 * @return The uint64_t pointer representation.
87 *
88 */
89#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
90
91/** Cast the memaddr part to the void*
92 *
93 * @param memaddr The memaddr value
94 *
95 */
96#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
97
98#define E1000_REG_BASE(e1000) \
99 ((e1000)->reg_base_virt)
100
101#define E1000_REG_ADDR(e1000, reg) \
102 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
103
104#define E1000_REG_READ(e1000, reg) \
105 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
106
107#define E1000_REG_WRITE(e1000, reg, value) \
108 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
109
110/** E1000 device data */
111typedef struct {
112 /** Device configuration */
113 e1000_info_t info;
114
115 /** Physical registers base address */
116 void *reg_base_phys;
117 /** Virtual registers base address */
118 void *reg_base_virt;
119
120 /** Physical tx ring address */
121 void *tx_ring_phys;
122 /** Virtual tx ring address */
123 void *tx_ring_virt;
124
125 /** Ring of TX frames, physical address */
126 void **tx_frame_phys;
127 /** Ring of TX frames, virtual address */
128 void **tx_frame_virt;
129
130 /** Physical rx ring address */
131 void *rx_ring_phys;
132 /** Virtual rx ring address */
133 void *rx_ring_virt;
134
135 /** Ring of RX frames, physical address */
136 void **rx_frame_phys;
137 /** Ring of RX frames, virtual address */
138 void **rx_frame_virt;
139
140 /** VLAN tag */
141 uint16_t vlan_tag;
142
143 /** Add VLAN tag to frame */
144 bool vlan_tag_add;
145
146 /** Used unicast Receive Address count */
147 unsigned int unicast_ra_count;
148
149 /** Used milticast Receive addrress count */
150 unsigned int multicast_ra_count;
151
152 /** The irq assigned */
153 int irq;
154
155 /** Lock for CTRL register */
156 fibril_mutex_t ctrl_lock;
157
158 /** Lock for receiver */
159 fibril_mutex_t rx_lock;
160
161 /** Lock for transmitter */
162 fibril_mutex_t tx_lock;
163
164 /** Lock for EEPROM access */
165 fibril_mutex_t eeprom_lock;
166} e1000_t;
167
168/** Global mutex for work with shared irq structure */
169FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
170
171static int e1000_get_address(e1000_t *, nic_address_t *);
172static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
173static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
174
175static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
176static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
177
178static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
179static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
180static int e1000_get_operation_mode(ddf_fun_t *, int *,
181 nic_channel_mode_t *, nic_role_t *);
182static int e1000_set_operation_mode(ddf_fun_t *, int,
183 nic_channel_mode_t, nic_role_t);
184static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
185static int e1000_autoneg_disable(ddf_fun_t *);
186static int e1000_autoneg_restart(ddf_fun_t *);
187
188static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
189
190/** Network interface options for E1000 card driver */
191static nic_iface_t e1000_nic_iface;
192
193/** Network interface options for E1000 card driver */
194static nic_iface_t e1000_nic_iface = {
195 .set_address = &e1000_set_addr,
196 .get_device_info = &e1000_get_device_info,
197 .get_cable_state = &e1000_get_cable_state,
198 .get_operation_mode = &e1000_get_operation_mode,
199 .set_operation_mode = &e1000_set_operation_mode,
200 .autoneg_enable = &e1000_autoneg_enable,
201 .autoneg_disable = &e1000_autoneg_disable,
202 .autoneg_restart = &e1000_autoneg_restart,
203 .vlan_set_tag = &e1000_vlan_set_tag,
204 .defective_get_mode = &e1000_defective_get_mode,
205 .defective_set_mode = &e1000_defective_set_mode,
206};
207
208/** Basic device operations for E1000 driver */
209static ddf_dev_ops_t e1000_dev_ops;
210
211static int e1000_dev_add(ddf_dev_t *);
212
213/** Basic driver operations for E1000 driver */
214static driver_ops_t e1000_driver_ops = {
215 .dev_add = e1000_dev_add
216};
217
218/** Driver structure for E1000 driver */
219static driver_t e1000_driver = {
220 .name = NAME,
221 .driver_ops = &e1000_driver_ops
222};
223
224/* The default implementation callbacks */
225static int e1000_on_activating(nic_t *);
226static int e1000_on_stopping(nic_t *);
227static void e1000_send_frame(nic_t *, void *, size_t);
228
229/** PIO ranges used in the IRQ code. */
230irq_pio_range_t e1000_irq_pio_ranges[] = {
231 {
232 .base = 0,
233 .size = PAGE_SIZE, /* XXX */
234 }
235};
236
237/** Commands to deal with interrupt
238 *
239 */
240irq_cmd_t e1000_irq_commands[] = {
241 {
242 /* Get the interrupt status */
243 .cmd = CMD_PIO_READ_32,
244 .addr = NULL,
245 .dstarg = 2
246 },
247 {
248 .cmd = CMD_PREDICATE,
249 .value = 2,
250 .srcarg = 2
251 },
252 {
253 /* Disable interrupts until interrupt routine is finished */
254 .cmd = CMD_PIO_WRITE_32,
255 .addr = NULL,
256 .value = 0xffffffff
257 },
258 {
259 .cmd = CMD_ACCEPT
260 }
261};
262
263/** Interrupt code definition */
264irq_code_t e1000_irq_code = {
265 .rangecount = sizeof(e1000_irq_pio_ranges) /
266 sizeof(irq_pio_range_t),
267 .ranges = e1000_irq_pio_ranges,
268 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
269 .cmds = e1000_irq_commands
270};
271
272/** Get the device information
273 *
274 * @param dev NIC device
275 * @param info Information to fill
276 *
277 * @return EOK
278 *
279 */
280static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
281{
282 assert(dev);
283 assert(info);
284
285 bzero(info, sizeof(nic_device_info_t));
286
287 info->vendor_id = 0x8086;
288 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
289 "Intel Corporation");
290 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
291 "Intel Pro");
292
293 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
294 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
295 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
296
297 return EOK;
298}
299
300/** Check the cable state
301 *
302 * @param[in] dev device
303 * @param[out] state state to fill
304 *
305 * @return EOK
306 *
307 */
308static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
309{
310 assert(dev);
311 assert(DRIVER_DATA_DEV(dev));
312 assert(state);
313
314 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
315 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
316 *state = NIC_CS_PLUGGED;
317 else
318 *state = NIC_CS_UNPLUGGED;
319
320 return EOK;
321}
322
323static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
324{
325 return useconds * 4;
326}
327
328/** Get operation mode of the device
329 *
330 */
331static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
332 nic_channel_mode_t *duplex, nic_role_t *role)
333{
334 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
335 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
336
337 if (status & STATUS_FD)
338 *duplex = NIC_CM_FULL_DUPLEX;
339 else
340 *duplex = NIC_CM_HALF_DUPLEX;
341
342 uint32_t speed_bits =
343 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
344
345 if (speed_bits == STATUS_SPEED_10)
346 *speed = 10;
347 else if (speed_bits == STATUS_SPEED_100)
348 *speed = 100;
349 else if ((speed_bits == STATUS_SPEED_1000A) ||
350 (speed_bits == STATUS_SPEED_1000B))
351 *speed = 1000;
352
353 *role = NIC_ROLE_UNKNOWN;
354 return EOK;
355}
356
357static void e1000_link_restart(e1000_t *e1000)
358{
359 fibril_mutex_lock(&e1000->ctrl_lock);
360
361 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
362
363 if (ctrl & CTRL_SLU) {
364 ctrl &= ~(CTRL_SLU);
365 fibril_mutex_unlock(&e1000->ctrl_lock);
366 usleep(10);
367 fibril_mutex_lock(&e1000->ctrl_lock);
368 ctrl |= CTRL_SLU;
369 }
370
371 fibril_mutex_unlock(&e1000->ctrl_lock);
372
373 e1000_link_restart(e1000);
374}
375
376/** Set operation mode of the device
377 *
378 */
379static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
380 nic_channel_mode_t duplex, nic_role_t role)
381{
382 if ((speed != 10) && (speed != 100) && (speed != 1000))
383 return EINVAL;
384
385 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
386 return EINVAL;
387
388 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
389
390 fibril_mutex_lock(&e1000->ctrl_lock);
391 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
392
393 ctrl |= CTRL_FRCSPD;
394 ctrl |= CTRL_FRCDPLX;
395 ctrl &= ~(CTRL_ASDE);
396
397 if (duplex == NIC_CM_FULL_DUPLEX)
398 ctrl |= CTRL_FD;
399 else
400 ctrl &= ~(CTRL_FD);
401
402 ctrl &= ~(CTRL_SPEED_MASK);
403 if (speed == 1000)
404 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
405 else if (speed == 100)
406 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
407 else
408 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
409
410 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
411
412 fibril_mutex_unlock(&e1000->ctrl_lock);
413
414 e1000_link_restart(e1000);
415
416 return EOK;
417}
418
419/** Enable auto-negotiation
420 *
421 * @param dev Device to update
422 * @param advertisement Ignored on E1000
423 *
424 * @return EOK if advertisement mode set successfully
425 *
426 */
427static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
428{
429 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
430
431 fibril_mutex_lock(&e1000->ctrl_lock);
432
433 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
434
435 ctrl &= ~(CTRL_FRCSPD);
436 ctrl &= ~(CTRL_FRCDPLX);
437 ctrl |= CTRL_ASDE;
438
439 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
440
441 fibril_mutex_unlock(&e1000->ctrl_lock);
442
443 e1000_link_restart(e1000);
444
445 return EOK;
446}
447
448/** Disable auto-negotiation
449 *
450 * @param dev Device to update
451 *
452 * @return EOK
453 *
454 */
455static int e1000_autoneg_disable(ddf_fun_t *dev)
456{
457 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
458
459 fibril_mutex_lock(&e1000->ctrl_lock);
460
461 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
462
463 ctrl |= CTRL_FRCSPD;
464 ctrl |= CTRL_FRCDPLX;
465 ctrl &= ~(CTRL_ASDE);
466
467 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
468
469 fibril_mutex_unlock(&e1000->ctrl_lock);
470
471 e1000_link_restart(e1000);
472
473 return EOK;
474}
475
476/** Restart auto-negotiation
477 *
478 * @param dev Device to update
479 *
480 * @return EOK if advertisement mode set successfully
481 *
482 */
483static int e1000_autoneg_restart(ddf_fun_t *dev)
484{
485 return e1000_autoneg_enable(dev, 0);
486}
487
488/** Get state of acceptance of weird frames
489 *
490 * @param device Device to check
491 * @param[out] mode Current mode
492 *
493 */
494static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
495{
496 e1000_t *e1000 = DRIVER_DATA_DEV(device);
497
498 *mode = 0;
499 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
500 if (rctl & RCTL_SBP)
501 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
502
503 return EOK;
504};
505
506/** Set acceptance of weird frames
507 *
508 * @param device Device to update
509 * @param mode Mode to set
510 *
511 * @return ENOTSUP if the mode is not supported
512 * @return EOK of mode was set
513 *
514 */
515static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
516{
517 e1000_t *e1000 = DRIVER_DATA_DEV(device);
518 int rc = EOK;
519
520 fibril_mutex_lock(&e1000->rx_lock);
521
522 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
523 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
524 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
525
526 if (short_mode && bad_mode)
527 rctl |= RCTL_SBP;
528 else if ((!short_mode) && (!bad_mode))
529 rctl &= ~RCTL_SBP;
530 else
531 rc = ENOTSUP;
532
533 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
534
535 fibril_mutex_unlock(&e1000->rx_lock);
536 return rc;
537};
538
539/** Write receive address to RA registr
540 *
541 * @param e1000 E1000 data structure
542 * @param position RA register position
543 * @param address Ethernet address
544 * @param set_av_bit Set the Addtess Valid bit
545 *
546 */
547static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
548 const nic_address_t * address, bool set_av_bit)
549{
550 uint8_t *mac0 = (uint8_t *) address->address;
551 uint8_t *mac1 = (uint8_t *) address->address + 1;
552 uint8_t *mac2 = (uint8_t *) address->address + 2;
553 uint8_t *mac3 = (uint8_t *) address->address + 3;
554 uint8_t *mac4 = (uint8_t *) address->address + 4;
555 uint8_t *mac5 = (uint8_t *) address->address + 5;
556
557 uint32_t rah;
558 uint32_t ral;
559
560 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
561 rah = ((*mac5) << 8) | ((*mac4));
562
563 if (set_av_bit)
564 rah |= RAH_AV;
565 else
566 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
567
568 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
569 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
570}
571
572/** Disable receive address in RA registr
573 *
574 * Clear Address Valid bit
575 *
576 * @param e1000 E1000 data structure
577 * @param position RA register position
578 *
579 */
580static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
581{
582 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
583 rah = rah & ~RAH_AV;
584 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
585}
586
587/** Clear all unicast addresses from RA registers
588 *
589 * @param e1000 E1000 data structure
590 *
591 */
592static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
593{
594 for (unsigned int ra_num = 1;
595 ra_num <= e1000->unicast_ra_count;
596 ra_num++)
597 e1000_disable_receive_address(e1000, ra_num);
598
599 e1000->unicast_ra_count = 0;
600}
601
602/** Clear all multicast addresses from RA registers
603 *
604 * @param e1000 E1000 data structure
605 *
606 */
607static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
608{
609 unsigned int first_multicast_ra_num =
610 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
611
612 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
613 ra_num >= first_multicast_ra_num;
614 ra_num--)
615 e1000_disable_receive_address(e1000, ra_num);
616
617 e1000->multicast_ra_count = 0;
618}
619
620/** Return receive address filter positions count usable for unicast
621 *
622 * @param e1000 E1000 data structure
623 *
624 * @return receive address filter positions count usable for unicast
625 *
626 */
627static unsigned int get_free_unicast_address_count(e1000_t *e1000)
628{
629 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
630}
631
632/** Return receive address filter positions count usable for multicast
633 *
634 * @param e1000 E1000 data structure
635 *
636 * @return receive address filter positions count usable for multicast
637 *
638 */
639static unsigned int get_free_multicast_address_count(e1000_t *e1000)
640{
641 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
642}
643
644/** Write unicast receive addresses to receive address filter registers
645 *
646 * @param e1000 E1000 data structure
647 * @param addr Pointer to address array
648 * @param addr_cnt Address array count
649 *
650 */
651static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
652 const nic_address_t *addr, size_t addr_cnt)
653{
654 assert(addr_cnt <= get_free_unicast_address_count(e1000));
655
656 nic_address_t *addr_iterator = (nic_address_t *) addr;
657
658 /* ra_num = 0 is primary address */
659 for (unsigned int ra_num = 1;
660 ra_num <= addr_cnt;
661 ra_num++) {
662 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
663 addr_iterator++;
664 }
665}
666
667/** Write multicast receive addresses to receive address filter registers
668 *
669 * @param e1000 E1000 data structure
670 * @param addr Pointer to address array
671 * @param addr_cnt Address array count
672 *
673 */
674static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
675 const nic_address_t *addr, size_t addr_cnt)
676{
677 assert(addr_cnt <= get_free_multicast_address_count(e1000));
678
679 nic_address_t *addr_iterator = (nic_address_t *) addr;
680
681 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
682 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
683 ra_num >= first_multicast_ra_num;
684 ra_num--) {
685 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
686 addr_iterator++;
687 }
688}
689
690/** Disable receiving frames for default address
691 *
692 * @param e1000 E1000 data structure
693 *
694 */
695static void disable_ra0_address_filter(e1000_t *e1000)
696{
697 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
698 rah0 = rah0 & ~RAH_AV;
699 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
700}
701
702/** Enable receiving frames for default address
703 *
704 * @param e1000 E1000 data structure
705 *
706 */
707static void enable_ra0_address_filter(e1000_t *e1000)
708{
709 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
710 rah0 = rah0 | RAH_AV;
711 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
712}
713
714/** Disable unicast promiscuous mode
715 *
716 * @param e1000 E1000 data structure
717 *
718 */
719static void e1000_disable_unicast_promisc(e1000_t *e1000)
720{
721 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
722 rctl = rctl & ~RCTL_UPE;
723 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
724}
725
726/** Enable unicast promiscuous mode
727 *
728 * @param e1000 E1000 data structure
729 *
730 */
731static void e1000_enable_unicast_promisc(e1000_t *e1000)
732{
733 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
734 rctl = rctl | RCTL_UPE;
735 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
736}
737
738/** Disable multicast promiscuous mode
739 *
740 * @param e1000 E1000 data structure
741 *
742 */
743static void e1000_disable_multicast_promisc(e1000_t *e1000)
744{
745 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
746 rctl = rctl & ~RCTL_MPE;
747 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
748}
749
750/** Enable multicast promiscuous mode
751 *
752 * @param e1000 E1000 data structure
753 *
754 */
755static void e1000_enable_multicast_promisc(e1000_t *e1000)
756{
757 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
758 rctl = rctl | RCTL_MPE;
759 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
760}
761
762/** Enable accepting of broadcast frames
763 *
764 * @param e1000 E1000 data structure
765 *
766 */
767static void e1000_enable_broadcast_accept(e1000_t *e1000)
768{
769 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
770 rctl = rctl | RCTL_BAM;
771 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
772}
773
774/** Disable accepting of broadcast frames
775 *
776 * @param e1000 E1000 data structure
777 *
778 */
779static void e1000_disable_broadcast_accept(e1000_t *e1000)
780{
781 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
782 rctl = rctl & ~RCTL_BAM;
783 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
784}
785
786/** Enable VLAN filtering according to VFTA registers
787 *
788 * @param e1000 E1000 data structure
789 *
790 */
791static void e1000_enable_vlan_filter(e1000_t *e1000)
792{
793 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
794 rctl = rctl | RCTL_VFE;
795 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
796}
797
798/** Disable VLAN filtering
799 *
800 * @param e1000 E1000 data structure
801 *
802 */
803static void e1000_disable_vlan_filter(e1000_t *e1000)
804{
805 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
806 rctl = rctl & ~RCTL_VFE;
807 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
808}
809
810/** Set multicast frames acceptance mode
811 *
812 * @param nic NIC device to update
813 * @param mode Mode to set
814 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
815 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
816 *
817 * @return EOK
818 *
819 */
820static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
821 const nic_address_t *addr, size_t addr_cnt)
822{
823 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
824 int rc = EOK;
825
826 fibril_mutex_lock(&e1000->rx_lock);
827
828 switch (mode) {
829 case NIC_MULTICAST_BLOCKED:
830 e1000_clear_multicast_receive_addresses(e1000);
831 e1000_disable_multicast_promisc(e1000);
832 nic_report_hw_filtering(nic, -1, 1, -1);
833 break;
834 case NIC_MULTICAST_LIST:
835 e1000_clear_multicast_receive_addresses(e1000);
836 if (addr_cnt > get_free_multicast_address_count(e1000)) {
837 /*
838 * Future work: fill MTA table
839 * Not strictly neccessary, it only saves some compares
840 * in the NIC library.
841 */
842 e1000_enable_multicast_promisc(e1000);
843 nic_report_hw_filtering(nic, -1, 0, -1);
844 } else {
845 e1000_disable_multicast_promisc(e1000);
846 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
847 nic_report_hw_filtering(nic, -1, 1, -1);
848 }
849 break;
850 case NIC_MULTICAST_PROMISC:
851 e1000_enable_multicast_promisc(e1000);
852 e1000_clear_multicast_receive_addresses(e1000);
853 nic_report_hw_filtering(nic, -1, 1, -1);
854 break;
855 default:
856 rc = ENOTSUP;
857 break;
858 }
859
860 fibril_mutex_unlock(&e1000->rx_lock);
861 return rc;
862}
863
864/** Set unicast frames acceptance mode
865 *
866 * @param nic NIC device to update
867 * @param mode Mode to set
868 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
869 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
870 *
871 * @return EOK
872 *
873 */
874static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
875 const nic_address_t *addr, size_t addr_cnt)
876{
877 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
878 int rc = EOK;
879
880 fibril_mutex_lock(&e1000->rx_lock);
881
882 switch (mode) {
883 case NIC_UNICAST_BLOCKED:
884 disable_ra0_address_filter(e1000);
885 e1000_clear_unicast_receive_addresses(e1000);
886 e1000_disable_unicast_promisc(e1000);
887 nic_report_hw_filtering(nic, 1, -1, -1);
888 break;
889 case NIC_UNICAST_DEFAULT:
890 enable_ra0_address_filter(e1000);
891 e1000_clear_unicast_receive_addresses(e1000);
892 e1000_disable_unicast_promisc(e1000);
893 nic_report_hw_filtering(nic, 1, -1, -1);
894 break;
895 case NIC_UNICAST_LIST:
896 enable_ra0_address_filter(e1000);
897 e1000_clear_unicast_receive_addresses(e1000);
898 if (addr_cnt > get_free_unicast_address_count(e1000)) {
899 e1000_enable_unicast_promisc(e1000);
900 nic_report_hw_filtering(nic, 0, -1, -1);
901 } else {
902 e1000_disable_unicast_promisc(e1000);
903 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
904 nic_report_hw_filtering(nic, 1, -1, -1);
905 }
906 break;
907 case NIC_UNICAST_PROMISC:
908 e1000_enable_unicast_promisc(e1000);
909 enable_ra0_address_filter(e1000);
910 e1000_clear_unicast_receive_addresses(e1000);
911 nic_report_hw_filtering(nic, 1, -1, -1);
912 break;
913 default:
914 rc = ENOTSUP;
915 break;
916 }
917
918 fibril_mutex_unlock(&e1000->rx_lock);
919 return rc;
920}
921
922/** Set broadcast frames acceptance mode
923 *
924 * @param nic NIC device to update
925 * @param mode Mode to set
926 *
927 * @return EOK
928 *
929 */
930static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
931{
932 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
933 int rc = EOK;
934
935 fibril_mutex_lock(&e1000->rx_lock);
936
937 switch (mode) {
938 case NIC_BROADCAST_BLOCKED:
939 e1000_disable_broadcast_accept(e1000);
940 break;
941 case NIC_BROADCAST_ACCEPTED:
942 e1000_enable_broadcast_accept(e1000);
943 break;
944 default:
945 rc = ENOTSUP;
946 break;
947 }
948
949 fibril_mutex_unlock(&e1000->rx_lock);
950 return rc;
951}
952
953/** Check if receiving is enabled
954 *
955 * @param e1000 E1000 data structure
956 *
957 * @return true if receiving is enabled
958 *
959 */
960static bool e1000_is_rx_enabled(e1000_t *e1000)
961{
962 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
963 return true;
964
965 return false;
966}
967
968/** Enable receiving
969 *
970 * @param e1000 E1000 data structure
971 *
972 */
973static void e1000_enable_rx(e1000_t *e1000)
974{
975 /* Set Receive Enable Bit */
976 E1000_REG_WRITE(e1000, E1000_RCTL,
977 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
978}
979
980/** Disable receiving
981 *
982 * @param e1000 E1000 data structure
983 *
984 */
985static void e1000_disable_rx(e1000_t *e1000)
986{
987 /* Clear Receive Enable Bit */
988 E1000_REG_WRITE(e1000, E1000_RCTL,
989 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
990}
991
992/** Set VLAN mask
993 *
994 * @param nic NIC device to update
995 * @param vlan_mask VLAN mask
996 *
997 */
998static void e1000_on_vlan_mask_change(nic_t *nic,
999 const nic_vlan_mask_t *vlan_mask)
1000{
1001 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1002
1003 fibril_mutex_lock(&e1000->rx_lock);
1004
1005 if (vlan_mask) {
1006 /*
1007 * Disable receiving, so that frame matching
1008 * partially written VLAN is not received.
1009 */
1010 bool rx_enabled = e1000_is_rx_enabled(e1000);
1011 if (rx_enabled)
1012 e1000_disable_rx(e1000);
1013
1014 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1015 uint32_t bitmap_part =
1016 ((uint32_t) vlan_mask->bitmap[i]) |
1017 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1018 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1019 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1020 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1021 }
1022
1023 e1000_enable_vlan_filter(e1000);
1024 if (rx_enabled)
1025 e1000_enable_rx(e1000);
1026 } else
1027 e1000_disable_vlan_filter(e1000);
1028
1029 fibril_mutex_unlock(&e1000->rx_lock);
1030}
1031
1032/** Set VLAN mask
1033 *
1034 * @param device E1000 device
1035 * @param tag VLAN tag
1036 *
1037 * @return EOK
1038 * @return ENOTSUP
1039 *
1040 */
1041static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1042 bool strip)
1043{
1044 /* VLAN CFI bit cannot be set */
1045 if (tag & VLANTAG_CFI)
1046 return ENOTSUP;
1047
1048 /*
1049 * CTRL.VME is neccessary for both strip and add
1050 * but CTRL.VME means stripping tags on receive.
1051 */
1052 if (!strip && add)
1053 return ENOTSUP;
1054
1055 e1000_t *e1000 = DRIVER_DATA_DEV(device);
1056
1057 e1000->vlan_tag = tag;
1058 e1000->vlan_tag_add = add;
1059
1060 fibril_mutex_lock(&e1000->ctrl_lock);
1061
1062 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1063 if (strip)
1064 ctrl |= CTRL_VME;
1065 else
1066 ctrl &= ~CTRL_VME;
1067
1068 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1069
1070 fibril_mutex_unlock(&e1000->ctrl_lock);
1071 return EOK;
1072}
1073
1074/** Fill receive descriptor with new empty buffer
1075 *
1076 * Store frame in e1000->rx_frame_phys
1077 *
1078 * @param nic NIC data stricture
1079 * @param offset Receive descriptor offset
1080 *
1081 */
1082static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1083{
1084 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1085
1086 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1087 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1088
1089 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1090 rx_descriptor->length = 0;
1091 rx_descriptor->checksum = 0;
1092 rx_descriptor->status = 0;
1093 rx_descriptor->errors = 0;
1094 rx_descriptor->special = 0;
1095}
1096
1097/** Clear receive descriptor
1098 *
1099 * @param e1000 E1000 data
1100 * @param offset Receive descriptor offset
1101 *
1102 */
1103static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1104{
1105 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1106 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1107
1108 rx_descriptor->length = 0;
1109 rx_descriptor->checksum = 0;
1110 rx_descriptor->status = 0;
1111 rx_descriptor->errors = 0;
1112 rx_descriptor->special = 0;
1113}
1114
1115/** Clear receive descriptor
1116 *
1117 * @param nic NIC data
1118 * @param offset Receive descriptor offset
1119 *
1120 */
1121static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1122{
1123 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1124
1125 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1126 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1127
1128 tx_descriptor->phys_addr = 0;
1129 tx_descriptor->length = 0;
1130 tx_descriptor->checksum_offset = 0;
1131 tx_descriptor->command = 0;
1132 tx_descriptor->status = 0;
1133 tx_descriptor->checksum_start_field = 0;
1134 tx_descriptor->special = 0;
1135}
1136
1137/** Increment tail pointer for receive or transmit ring
1138 *
1139 * @param tail Old Tail
1140 * @param descriptors_count Ring length
1141 *
1142 * @return New tail
1143 *
1144 */
1145static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1146{
1147 if (tail + 1 == descriptors_count)
1148 return 0;
1149 else
1150 return tail + 1;
1151}
1152
1153/** Receive frames
1154 *
1155 * @param nic NIC data
1156 *
1157 */
1158static void e1000_receive_frames(nic_t *nic)
1159{
1160 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1161
1162 fibril_mutex_lock(&e1000->rx_lock);
1163
1164 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1165 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1166
1167 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1168 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1169
1170 while (rx_descriptor->status & 0x01) {
1171 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1172
1173 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1174 if (frame != NULL) {
1175 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1176 nic_received_frame(nic, frame);
1177 } else {
1178 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1179 }
1180
1181 e1000_fill_new_rx_descriptor(nic, next_tail);
1182
1183 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1184 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1185
1186 rx_descriptor = (e1000_rx_descriptor_t *)
1187 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1188 }
1189
1190 fibril_mutex_unlock(&e1000->rx_lock);
1191}
1192
1193/** Enable E1000 interupts
1194 *
1195 * @param e1000 E1000 data structure
1196 *
1197 */
1198static void e1000_enable_interrupts(e1000_t *e1000)
1199{
1200 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1201}
1202
1203/** Disable E1000 interupts
1204 *
1205 * @param e1000 E1000 data structure
1206 *
1207 */
1208static void e1000_disable_interrupts(e1000_t *e1000)
1209{
1210 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1211}
1212
1213/** Interrupt handler implementation
1214 *
1215 * This function is called from e1000_interrupt_handler()
1216 * and e1000_poll()
1217 *
1218 * @param nic NIC data
1219 * @param icr ICR register value
1220 *
1221 */
1222static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1223{
1224 if (icr & ICR_RXT0)
1225 e1000_receive_frames(nic);
1226}
1227
1228/** Handle device interrupt
1229 *
1230 * @param dev E1000 device
1231 * @param iid IPC call id
1232 * @param icall IPC call structure
1233 *
1234 */
1235static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1236 ipc_call_t *icall)
1237{
1238 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1239 nic_t *nic = NIC_DATA_DEV(dev);
1240 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1241
1242 e1000_interrupt_handler_impl(nic, icr);
1243 e1000_enable_interrupts(e1000);
1244}
1245
1246/** Register interrupt handler for the card in the system
1247 *
1248 * Note: The global irq_reg_mutex is locked because of work with global
1249 * structure.
1250 *
1251 * @param nic Driver data
1252 *
1253 * @return EOK if the handler was registered
1254 * @return Negative error code otherwise
1255 *
1256 */
1257inline static int e1000_register_int_handler(nic_t *nic)
1258{
1259 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1260
1261 /* Lock the mutex in whole driver while working with global structure */
1262 fibril_mutex_lock(&irq_reg_mutex);
1263
1264 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1265 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1266 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1267
1268 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1269 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1270
1271 fibril_mutex_unlock(&irq_reg_mutex);
1272 return rc;
1273}
1274
1275/** Force receiving all frames in the receive buffer
1276 *
1277 * @param nic NIC data
1278 *
1279 */
1280static void e1000_poll(nic_t *nic)
1281{
1282 assert(nic);
1283
1284 e1000_t *e1000 = nic_get_specific(nic);
1285 assert(e1000);
1286
1287 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1288 e1000_interrupt_handler_impl(nic, icr);
1289}
1290
1291/** Calculates ITR register interrupt from timeval structure
1292 *
1293 * @param period Period
1294 *
1295 */
1296static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1297{
1298 // TODO: use also tv_sec
1299 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1300}
1301
1302/** Set polling mode
1303 *
1304 * @param device Device to set
1305 * @param mode Mode to set
1306 * @param period Period for NIC_POLL_PERIODIC
1307 *
1308 * @return EOK if succeed
1309 * @return ENOTSUP if the mode is not supported
1310 *
1311 */
1312static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1313 const struct timeval *period)
1314{
1315 assert(nic);
1316
1317 e1000_t *e1000 = nic_get_specific(nic);
1318 assert(e1000);
1319
1320 switch (mode) {
1321 case NIC_POLL_IMMEDIATE:
1322 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1323 e1000_enable_interrupts(e1000);
1324 break;
1325 case NIC_POLL_ON_DEMAND:
1326 e1000_disable_interrupts(e1000);
1327 break;
1328 case NIC_POLL_PERIODIC:
1329 assert(period);
1330 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1331 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1332 e1000_enable_interrupts(e1000);
1333 break;
1334 default:
1335 return ENOTSUP;
1336 }
1337
1338 return EOK;
1339}
1340
1341/** Initialize receive registers
1342 *
1343 * @param e1000 E1000 data structure
1344 *
1345 */
1346static void e1000_initialize_rx_registers(e1000_t *e1000)
1347{
1348 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1349 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1350
1351 /* It is not posible to let HW use all descriptors */
1352 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1353
1354 /* Set Broadcast Enable Bit */
1355 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1356}
1357
1358/** Initialize receive structure
1359 *
1360 * @param nic NIC data
1361 *
1362 * @return EOK if succeed
1363 * @return Negative error code otherwise
1364 *
1365 */
1366static int e1000_initialize_rx_structure(nic_t *nic)
1367{
1368 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1369 fibril_mutex_lock(&e1000->rx_lock);
1370
1371 int rc = dmamem_map_anonymous(
1372 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1373 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
1374 &e1000->rx_ring_virt);
1375 if (rc != EOK)
1376 return rc;
1377
1378 E1000_REG_WRITE(e1000, E1000_RDBAH,
1379 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1380 E1000_REG_WRITE(e1000, E1000_RDBAL,
1381 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1382
1383 e1000->rx_frame_phys =
1384 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1385 e1000->rx_frame_virt =
1386 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1387 if (e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {
1388 rc = ENOMEM;
1389 goto error;
1390 }
1391
1392 size_t i;
1393 void *frame_virt;
1394 void *frame_phys;
1395
1396 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1397 rc = dmamem_map_anonymous(
1398 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1399 0, &frame_phys, &frame_virt);
1400 if (rc != EOK)
1401 goto error;
1402
1403 e1000->rx_frame_virt[i] = frame_virt;
1404 e1000->rx_frame_phys[i] = frame_phys;
1405 }
1406
1407 /* Write descriptor */
1408 for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
1409 e1000_fill_new_rx_descriptor(nic, i);
1410
1411 e1000_initialize_rx_registers(e1000);
1412
1413 fibril_mutex_unlock(&e1000->rx_lock);
1414 return EOK;
1415
1416error:
1417 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1418 if (e1000->rx_frame_virt[i] != NULL) {
1419 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1420 e1000->rx_frame_virt[i] = NULL;
1421 e1000->rx_frame_phys[i] = NULL;
1422 }
1423 }
1424
1425 if (e1000->rx_frame_phys != NULL) {
1426 free(e1000->rx_frame_phys);
1427 e1000->rx_frame_phys = NULL;
1428 }
1429
1430 if (e1000->rx_frame_virt != NULL) {
1431 free(e1000->rx_frame_virt);
1432 e1000->rx_frame_phys = NULL;
1433 }
1434
1435 return rc;
1436}
1437
1438/** Uninitialize receive structure
1439 *
1440 * @param nic NIC data
1441 *
1442 */
1443static void e1000_uninitialize_rx_structure(nic_t *nic)
1444{
1445 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1446
1447 /* Write descriptor */
1448 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1449 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1450 e1000->rx_frame_virt[offset] = NULL;
1451 e1000->rx_frame_phys[offset] = NULL;
1452 }
1453
1454 free(e1000->rx_frame_virt);
1455 free(e1000->rx_frame_phys);
1456 e1000->rx_frame_virt = NULL;
1457 e1000->rx_frame_phys = NULL;
1458 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1459}
1460
1461/** Clear receive descriptor ring
1462 *
1463 * @param e1000 E1000 data
1464 *
1465 */
1466static void e1000_clear_rx_ring(e1000_t *e1000)
1467{
1468 /* Write descriptor */
1469 for (unsigned int offset = 0;
1470 offset < E1000_RX_FRAME_COUNT;
1471 offset++)
1472 e1000_clear_rx_descriptor(e1000, offset);
1473}
1474
1475/** Initialize filters
1476 *
1477 * @param e1000 E1000 data
1478 *
1479 */
1480static void e1000_initialize_filters(e1000_t *e1000)
1481{
1482 /* Initialize address filter */
1483 e1000->unicast_ra_count = 0;
1484 e1000->multicast_ra_count = 0;
1485 e1000_clear_unicast_receive_addresses(e1000);
1486}
1487
1488/** Initialize VLAN
1489 *
1490 * @param e1000 E1000 data
1491 *
1492 */
1493static void e1000_initialize_vlan(e1000_t *e1000)
1494{
1495 e1000->vlan_tag_add = false;
1496}
1497
1498/** Fill MAC address from EEPROM to RA[0] register
1499 *
1500 * @param e1000 E1000 data
1501 *
1502 */
1503static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1504{
1505 /* MAC address from eeprom to RA[0] */
1506 nic_address_t address;
1507 e1000_eeprom_get_address(e1000, &address);
1508 e1000_write_receive_address(e1000, 0, &address, true);
1509}
1510
1511/** Initialize other registers
1512 *
1513 * @param dev E1000 data.
1514 *
1515 * @return EOK if succeed
1516 * @return Negative error code otherwise
1517 *
1518 */
1519static void e1000_initialize_registers(e1000_t *e1000)
1520{
1521 E1000_REG_WRITE(e1000, E1000_ITR,
1522 e1000_calculate_itr_interval_from_usecs(
1523 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1524 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1525 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1526 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1527 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1528 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1529 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1530}
1531
1532/** Initialize transmit registers
1533 *
1534 * @param e1000 E1000 data.
1535 *
1536 */
1537static void e1000_initialize_tx_registers(e1000_t *e1000)
1538{
1539 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1540 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1541 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1542
1543 E1000_REG_WRITE(e1000, E1000_TIPG,
1544 10 << TIPG_IPGT_SHIFT |
1545 8 << TIPG_IPGR1_SHIFT |
1546 6 << TIPG_IPGR2_SHIFT);
1547
1548 E1000_REG_WRITE(e1000, E1000_TCTL,
1549 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1550 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1551 TCTL_PSP /* Pad Short Packets */);
1552}
1553
1554/** Initialize transmit structure
1555 *
1556 * @param e1000 E1000 data.
1557 *
1558 */
1559static int e1000_initialize_tx_structure(e1000_t *e1000)
1560{
1561 size_t i;
1562
1563 fibril_mutex_lock(&e1000->tx_lock);
1564
1565 e1000->tx_ring_phys = NULL;
1566 e1000->tx_ring_virt = NULL;
1567 e1000->tx_frame_phys = NULL;
1568 e1000->tx_frame_virt = NULL;
1569
1570 int rc = dmamem_map_anonymous(
1571 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1572 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
1573 &e1000->tx_ring_virt);
1574 if (rc != EOK)
1575 goto error;
1576
1577 bzero(e1000->tx_ring_virt,
1578 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1579
1580 e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1581 e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1582
1583 if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) {
1584 rc = ENOMEM;
1585 goto error;
1586 }
1587
1588 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1589 rc = dmamem_map_anonymous(
1590 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1591 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1592 if (rc != EOK)
1593 goto error;
1594 }
1595
1596 E1000_REG_WRITE(e1000, E1000_TDBAH,
1597 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1598 E1000_REG_WRITE(e1000, E1000_TDBAL,
1599 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1600
1601 e1000_initialize_tx_registers(e1000);
1602
1603 fibril_mutex_unlock(&e1000->tx_lock);
1604 return EOK;
1605
1606error:
1607 if (e1000->tx_ring_virt != NULL) {
1608 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1609 e1000->tx_ring_virt = NULL;
1610 }
1611
1612 if (e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {
1613 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1614 if (e1000->tx_frame_virt[i] != NULL) {
1615 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1616 e1000->tx_frame_virt[i] = NULL;
1617 e1000->tx_frame_phys[i] = NULL;
1618 }
1619 }
1620 }
1621
1622 if (e1000->tx_frame_phys != NULL) {
1623 free(e1000->tx_frame_phys);
1624 e1000->tx_frame_phys = NULL;
1625 }
1626
1627 if (e1000->tx_frame_virt != NULL) {
1628 free(e1000->tx_frame_virt);
1629 e1000->tx_frame_phys = NULL;
1630 }
1631
1632 return rc;
1633}
1634
1635/** Uninitialize transmit structure
1636 *
1637 * @param nic NIC data
1638 *
1639 */
1640static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1641{
1642 size_t i;
1643
1644 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1645 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1646 e1000->tx_frame_virt[i] = NULL;
1647 e1000->tx_frame_phys[i] = NULL;
1648 }
1649
1650 if (e1000->tx_frame_phys != NULL) {
1651 free(e1000->tx_frame_phys);
1652 e1000->tx_frame_phys = NULL;
1653 }
1654
1655 if (e1000->tx_frame_virt != NULL) {
1656 free(e1000->tx_frame_virt);
1657 e1000->tx_frame_phys = NULL;
1658 }
1659
1660 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1661}
1662
1663/** Clear transmit descriptor ring
1664 *
1665 * @param nic NIC data
1666 *
1667 */
1668static void e1000_clear_tx_ring(nic_t *nic)
1669{
1670 /* Write descriptor */
1671 for (unsigned int offset = 0;
1672 offset < E1000_TX_FRAME_COUNT;
1673 offset++)
1674 e1000_clear_tx_descriptor(nic, offset);
1675}
1676
1677/** Enable transmit
1678 *
1679 * @param e1000 E1000 data
1680 *
1681 */
1682static void e1000_enable_tx(e1000_t *e1000)
1683{
1684 /* Set Transmit Enable Bit */
1685 E1000_REG_WRITE(e1000, E1000_TCTL,
1686 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1687}
1688
1689/** Disable transmit
1690 *
1691 * @param e1000 E1000 data
1692 *
1693 */
1694static void e1000_disable_tx(e1000_t *e1000)
1695{
1696 /* Clear Transmit Enable Bit */
1697 E1000_REG_WRITE(e1000, E1000_TCTL,
1698 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1699}
1700
1701/** Reset E1000 device
1702 *
1703 * @param e1000 The E1000 data
1704 *
1705 */
1706static int e1000_reset(nic_t *nic)
1707{
1708 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1709
1710 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1711
1712 /* Wait for the reset */
1713 usleep(20);
1714
1715 /* check if RST_BIT cleared */
1716 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1717 return EINVAL;
1718
1719 e1000_initialize_registers(e1000);
1720 e1000_initialize_rx_registers(e1000);
1721 e1000_initialize_tx_registers(e1000);
1722 e1000_fill_mac_from_eeprom(e1000);
1723 e1000_initialize_filters(e1000);
1724 e1000_initialize_vlan(e1000);
1725
1726 return EOK;
1727}
1728
1729/** Activate the device to receive and transmit frames
1730 *
1731 * @param nic NIC driver data
1732 *
1733 * @return EOK if activated successfully
1734 * @return Error code otherwise
1735 *
1736 */
1737static int e1000_on_activating(nic_t *nic)
1738{
1739 assert(nic);
1740
1741 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1742
1743 fibril_mutex_lock(&e1000->rx_lock);
1744 fibril_mutex_lock(&e1000->tx_lock);
1745 fibril_mutex_lock(&e1000->ctrl_lock);
1746
1747 e1000_enable_interrupts(e1000);
1748
1749 nic_enable_interrupt(nic, e1000->irq);
1750
1751 e1000_clear_rx_ring(e1000);
1752 e1000_enable_rx(e1000);
1753
1754 e1000_clear_tx_ring(nic);
1755 e1000_enable_tx(e1000);
1756
1757 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1758 ctrl |= CTRL_SLU;
1759 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1760
1761 fibril_mutex_unlock(&e1000->ctrl_lock);
1762 fibril_mutex_unlock(&e1000->tx_lock);
1763 fibril_mutex_unlock(&e1000->rx_lock);
1764
1765 return EOK;
1766}
1767
1768/** Callback for NIC_STATE_DOWN change
1769 *
1770 * @param nic NIC driver data
1771 *
1772 * @return EOK if succeed
1773 * @return Error code otherwise
1774 *
1775 */
1776static int e1000_on_down_unlocked(nic_t *nic)
1777{
1778 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1779
1780 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1781 ctrl &= ~CTRL_SLU;
1782 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1783
1784 e1000_disable_tx(e1000);
1785 e1000_disable_rx(e1000);
1786
1787 nic_disable_interrupt(nic, e1000->irq);
1788 e1000_disable_interrupts(e1000);
1789
1790 /*
1791 * Wait for the for the end of all data
1792 * transfers to descriptors.
1793 */
1794 usleep(100);
1795
1796 return EOK;
1797}
1798
1799/** Callback for NIC_STATE_DOWN change
1800 *
1801 * @param nic NIC driver data
1802 *
1803 * @return EOK if succeed
1804 * @return Error code otherwise
1805 *
1806 */
1807static int e1000_on_down(nic_t *nic)
1808{
1809 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1810
1811 fibril_mutex_lock(&e1000->rx_lock);
1812 fibril_mutex_lock(&e1000->tx_lock);
1813 fibril_mutex_lock(&e1000->ctrl_lock);
1814
1815 int rc = e1000_on_down_unlocked(nic);
1816
1817 fibril_mutex_unlock(&e1000->ctrl_lock);
1818 fibril_mutex_unlock(&e1000->tx_lock);
1819 fibril_mutex_unlock(&e1000->rx_lock);
1820
1821 return rc;
1822}
1823
1824/** Callback for NIC_STATE_STOPPED change
1825 *
1826 * @param nic NIC driver data
1827 *
1828 * @return EOK if succeed
1829 * @return Error code otherwise
1830 *
1831 */
1832static int e1000_on_stopping(nic_t *nic)
1833{
1834 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1835
1836 fibril_mutex_lock(&e1000->rx_lock);
1837 fibril_mutex_lock(&e1000->tx_lock);
1838 fibril_mutex_lock(&e1000->ctrl_lock);
1839
1840 int rc = e1000_on_down_unlocked(nic);
1841 if (rc == EOK)
1842 rc = e1000_reset(nic);
1843
1844 fibril_mutex_unlock(&e1000->ctrl_lock);
1845 fibril_mutex_unlock(&e1000->tx_lock);
1846 fibril_mutex_unlock(&e1000->rx_lock);
1847
1848 return rc;
1849}
1850
1851/** Create driver data structure
1852 *
1853 * @return Intialized device data structure or NULL
1854 *
1855 */
1856static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1857{
1858 assert(dev);
1859 assert(!dev->driver_data);
1860
1861 nic_t *nic = nic_create_and_bind(dev);
1862 if (!nic)
1863 return NULL;
1864
1865 e1000_t *e1000 = malloc(sizeof(e1000_t));
1866 if (!e1000) {
1867 nic_unbind_and_destroy(dev);
1868 return NULL;
1869 }
1870
1871 bzero(e1000, sizeof(e1000_t));
1872
1873 nic_set_specific(nic, e1000);
1874 nic_set_send_frame_handler(nic, e1000_send_frame);
1875 nic_set_state_change_handlers(nic, e1000_on_activating,
1876 e1000_on_down, e1000_on_stopping);
1877 nic_set_filtering_change_handlers(nic,
1878 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1879 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1880 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1881
1882 fibril_mutex_initialize(&e1000->ctrl_lock);
1883 fibril_mutex_initialize(&e1000->rx_lock);
1884 fibril_mutex_initialize(&e1000->tx_lock);
1885 fibril_mutex_initialize(&e1000->eeprom_lock);
1886
1887 return e1000;
1888}
1889
1890/** Delete driver data structure
1891 *
1892 * @param data E1000 device data structure
1893 *
1894 */
1895inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1896{
1897 assert(dev);
1898
1899 if (dev->driver_data != NULL)
1900 nic_unbind_and_destroy(dev);
1901}
1902
1903/** Clean up the E1000 device structure.
1904 *
1905 * @param dev Device structure.
1906 *
1907 */
1908static void e1000_dev_cleanup(ddf_dev_t *dev)
1909{
1910 assert(dev);
1911
1912 e1000_delete_dev_data(dev);
1913
1914 if (dev->parent_sess != NULL) {
1915 async_hangup(dev->parent_sess);
1916 dev->parent_sess = NULL;
1917 }
1918}
1919
1920/** Fill the irq and io_addr part of device data structure
1921 *
1922 * The hw_resources must be obtained before calling this function
1923 *
1924 * @param dev Device structure
1925 * @param hw_resources Hardware resources obtained from the parent device
1926 *
1927 * @return EOK if succeed
1928 * @return Negative error code otherwise
1929 *
1930 */
1931static int e1000_fill_resource_info(ddf_dev_t *dev,
1932 const hw_res_list_parsed_t *hw_resources)
1933{
1934 assert(dev != NULL);
1935 assert(hw_resources != NULL);
1936 assert(dev->driver_data != NULL);
1937
1938 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1939
1940 if (hw_resources->irqs.count != 1)
1941 return EINVAL;
1942
1943 e1000->irq = hw_resources->irqs.irqs[0];
1944 e1000->reg_base_phys =
1945 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1946
1947 return EOK;
1948}
1949
1950/** Obtain information about hardware resources of the device
1951 *
1952 * The device must be connected to the parent
1953 *
1954 * @param dev Device structure
1955 *
1956 * @return EOK if succeed
1957 * @return Negative error code otherwise
1958 *
1959 */
1960static int e1000_get_resource_info(ddf_dev_t *dev)
1961{
1962 assert(dev != NULL);
1963 assert(NIC_DATA_DEV(dev) != NULL);
1964
1965 hw_res_list_parsed_t hw_res_parsed;
1966 hw_res_list_parsed_init(&hw_res_parsed);
1967
1968 /* Get hw resources form parent driver */
1969 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1970 if (rc != EOK)
1971 return rc;
1972
1973 /* Fill resources information to the device */
1974 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1975 hw_res_list_parsed_clean(&hw_res_parsed);
1976
1977 return rc;
1978}
1979
1980/** Initialize the E1000 device structure
1981 *
1982 * @param dev Device information
1983 *
1984 * @return EOK if succeed
1985 * @return Negative error code otherwise
1986 *
1987 */
1988static int e1000_device_initialize(ddf_dev_t *dev)
1989{
1990 /* Allocate driver data for the device. */
1991 e1000_t *e1000 = e1000_create_dev_data(dev);
1992 if (e1000 == NULL) {
1993 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1994 return ENOMEM;
1995 }
1996
1997 /* Obtain and fill hardware resources info */
1998 int rc = e1000_get_resource_info(dev);
1999 if (rc != EOK) {
2000 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2001 e1000_dev_cleanup(dev);
2002 return rc;
2003 }
2004
2005 uint16_t device_id;
2006 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
2007 &device_id);
2008 if (rc != EOK) {
2009 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2010 e1000_dev_cleanup(dev);
2011 return rc;
2012 }
2013
2014 e1000_board_t board;
2015 switch (device_id) {
2016 case 0x100e:
2017 case 0x1015:
2018 case 0x1016:
2019 case 0x1017:
2020 board = E1000_82540;
2021 break;
2022 case 0x1013:
2023 case 0x1018:
2024 case 0x1078:
2025 board = E1000_82541;
2026 break;
2027 case 0x1076:
2028 case 0x1077:
2029 case 0x107c:
2030 board = E1000_82541REV2;
2031 break;
2032 case 0x100f:
2033 case 0x1011:
2034 case 0x1026:
2035 case 0x1027:
2036 case 0x1028:
2037 board = E1000_82545;
2038 break;
2039 case 0x1010:
2040 case 0x1012:
2041 case 0x101d:
2042 case 0x1079:
2043 case 0x107a:
2044 case 0x107b:
2045 board = E1000_82546;
2046 break;
2047 case 0x1019:
2048 case 0x101a:
2049 board = E1000_82547;
2050 break;
2051 case 0x10b9:
2052 board = E1000_82572;
2053 break;
2054 case 0x1096:
2055 board = E1000_80003ES2;
2056 break;
2057 default:
2058 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2059 device_id);
2060 e1000_dev_cleanup(dev);
2061 return ENOTSUP;
2062 }
2063
2064 switch (board) {
2065 case E1000_82540:
2066 case E1000_82541:
2067 case E1000_82541REV2:
2068 case E1000_82545:
2069 case E1000_82546:
2070 e1000->info.eerd_start = 0x01;
2071 e1000->info.eerd_done = 0x10;
2072 e1000->info.eerd_address_offset = 8;
2073 e1000->info.eerd_data_offset = 16;
2074 break;
2075 case E1000_82547:
2076 case E1000_82572:
2077 case E1000_80003ES2:
2078 e1000->info.eerd_start = 0x01;
2079 e1000->info.eerd_done = 0x02;
2080 e1000->info.eerd_address_offset = 2;
2081 e1000->info.eerd_data_offset = 16;
2082 break;
2083 }
2084
2085 return EOK;
2086}
2087
2088/** Enable the I/O ports of the device.
2089 *
2090 * @param dev E1000 device.
2091 *
2092 * @return EOK if successed
2093 * @return Negative error code otherwise
2094 *
2095 */
2096static int e1000_pio_enable(ddf_dev_t *dev)
2097{
2098 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2099
2100 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2101 &e1000->reg_base_virt);
2102 if (rc != EOK)
2103 return EADDRNOTAVAIL;
2104
2105 return EOK;
2106}
2107
2108/** Probe and initialize the newly added device.
2109 *
2110 * @param dev E1000 device.
2111 *
2112 */
2113int e1000_dev_add(ddf_dev_t *dev)
2114{
2115 ddf_fun_t *fun;
2116 assert(dev);
2117
2118 /* Initialize device structure for E1000 */
2119 int rc = e1000_device_initialize(dev);
2120 if (rc != EOK)
2121 return rc;
2122
2123 /* Device initialization */
2124 nic_t *nic = dev->driver_data;
2125 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2126
2127 /* Map registers */
2128 rc = e1000_pio_enable(dev);
2129 if (rc != EOK)
2130 goto err_destroy;
2131
2132 e1000_initialize_registers(e1000);
2133 rc = e1000_initialize_tx_structure(e1000);
2134 if (rc != EOK)
2135 goto err_pio;
2136
2137 fibril_mutex_lock(&e1000->rx_lock);
2138
2139 e1000_fill_mac_from_eeprom(e1000);
2140 e1000_initialize_filters(e1000);
2141
2142 fibril_mutex_unlock(&e1000->rx_lock);
2143
2144 e1000_initialize_vlan(e1000);
2145
2146 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2147 if (fun == NULL)
2148 goto err_tx_structure;
2149 nic_set_ddf_fun(nic, fun);
2150 fun->ops = &e1000_dev_ops;
2151 fun->driver_data = nic;
2152
2153 rc = e1000_register_int_handler(nic);
2154 if (rc != EOK)
2155 goto err_fun_create;
2156
2157 rc = nic_connect_to_services(nic);
2158 if (rc != EOK)
2159 goto err_irq;
2160
2161 rc = e1000_initialize_rx_structure(nic);
2162 if (rc != EOK)
2163 goto err_irq;
2164
2165 nic_address_t e1000_address;
2166 e1000_get_address(e1000, &e1000_address);
2167 rc = nic_report_address(nic, &e1000_address);
2168 if (rc != EOK)
2169 goto err_rx_structure;
2170
2171 struct timeval period;
2172 period.tv_sec = 0;
2173 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2174 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2175 if (rc != EOK)
2176 goto err_rx_structure;
2177
2178 rc = ddf_fun_bind(fun);
2179 if (rc != EOK)
2180 goto err_fun_bind;
2181
2182 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2183 if (rc != EOK)
2184 goto err_add_to_cat;
2185
2186 return EOK;
2187
2188err_add_to_cat:
2189 ddf_fun_unbind(fun);
2190err_fun_bind:
2191err_rx_structure:
2192 e1000_uninitialize_rx_structure(nic);
2193err_irq:
2194 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2195err_fun_create:
2196 ddf_fun_destroy(fun);
2197 nic_set_ddf_fun(nic, NULL);
2198err_tx_structure:
2199 e1000_uninitialize_tx_structure(e1000);
2200err_pio:
2201 // TODO: e1000_pio_disable(dev);
2202err_destroy:
2203 e1000_dev_cleanup(dev);
2204 return rc;
2205}
2206
2207/** Read 16-bit value from EEPROM of E1000 adapter
2208 *
2209 * Read using the EERD register.
2210 *
2211 * @param device E1000 device
2212 * @param eeprom_address 8-bit EEPROM address
2213 *
2214 * @return 16-bit value from EEPROM
2215 *
2216 */
2217static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2218{
2219 fibril_mutex_lock(&e1000->eeprom_lock);
2220
2221 /* Write address and START bit to EERD register */
2222 uint32_t write_data = e1000->info.eerd_start |
2223 (((uint32_t) eeprom_address) <<
2224 e1000->info.eerd_address_offset);
2225 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2226
2227 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2228 while ((eerd & e1000->info.eerd_done) == 0) {
2229 usleep(1);
2230 eerd = E1000_REG_READ(e1000, E1000_EERD);
2231 }
2232
2233 fibril_mutex_unlock(&e1000->eeprom_lock);
2234
2235 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2236}
2237
2238/** Get MAC address of the E1000 adapter
2239 *
2240 * @param device E1000 device
2241 * @param address Place to store the address
2242 * @param max_len Maximal addresss length to store
2243 *
2244 * @return EOK if succeed
2245 * @return Negative error code otherwise
2246 *
2247 */
2248static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2249{
2250 fibril_mutex_lock(&e1000->rx_lock);
2251
2252 uint8_t *mac0_dest = (uint8_t *) address->address;
2253 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2254 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2255 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2256 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2257 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2258
2259 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2260 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2261
2262 *mac0_dest = (uint8_t) ral;
2263 *mac1_dest = (uint8_t) (ral >> 8);
2264 *mac2_dest = (uint8_t) (ral >> 16);
2265 *mac3_dest = (uint8_t) (ral >> 24);
2266 *mac4_dest = (uint8_t) rah;
2267 *mac5_dest = (uint8_t) (rah >> 8);
2268
2269 fibril_mutex_unlock(&e1000->rx_lock);
2270 return EOK;
2271};
2272
2273/** Set card MAC address
2274 *
2275 * @param device E1000 device
2276 * @param address Address
2277 *
2278 * @return EOK if succeed
2279 * @return Negative error code otherwise
2280 */
2281static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2282{
2283 nic_t *nic = NIC_DATA_DEV(dev);
2284 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2285
2286 fibril_mutex_lock(&e1000->rx_lock);
2287 fibril_mutex_lock(&e1000->tx_lock);
2288
2289 int rc = nic_report_address(nic, addr);
2290 if (rc == EOK)
2291 e1000_write_receive_address(e1000, 0, addr, false);
2292
2293 fibril_mutex_unlock(&e1000->tx_lock);
2294 fibril_mutex_unlock(&e1000->rx_lock);
2295
2296 return rc;
2297}
2298
2299static void e1000_eeprom_get_address(e1000_t *e1000,
2300 nic_address_t *address)
2301{
2302 uint16_t *mac0_dest = (uint16_t *) address->address;
2303 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2304 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2305
2306 *mac0_dest = e1000_eeprom_read(e1000, 0);
2307 *mac2_dest = e1000_eeprom_read(e1000, 1);
2308 *mac4_dest = e1000_eeprom_read(e1000, 2);
2309}
2310
2311/** Send frame
2312 *
2313 * @param nic NIC driver data structure
2314 * @param data Frame data
2315 * @param size Frame size in bytes
2316 *
2317 * @return EOK if succeed
2318 * @return Error code in the case of error
2319 *
2320 */
2321static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2322{
2323 assert(nic);
2324
2325 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2326 fibril_mutex_lock(&e1000->tx_lock);
2327
2328 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2329 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2330 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2331
2332 bool descriptor_available = false;
2333
2334 /* Descriptor never used */
2335 if (tx_descriptor_addr->length == 0)
2336 descriptor_available = true;
2337
2338 /* Descriptor done */
2339 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2340 descriptor_available = true;
2341
2342 if (!descriptor_available) {
2343 /* Frame lost */
2344 fibril_mutex_unlock(&e1000->tx_lock);
2345 return;
2346 }
2347
2348 memcpy(e1000->tx_frame_virt[tdt], data, size);
2349
2350 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2351 tx_descriptor_addr->length = size;
2352
2353 /*
2354 * Report status to STATUS.DD (descriptor done),
2355 * add ethernet CRC, end of packet.
2356 */
2357 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2358 TXDESCRIPTOR_COMMAND_IFCS |
2359 TXDESCRIPTOR_COMMAND_EOP;
2360
2361 tx_descriptor_addr->checksum_offset = 0;
2362 tx_descriptor_addr->status = 0;
2363 if (e1000->vlan_tag_add) {
2364 tx_descriptor_addr->special = e1000->vlan_tag;
2365 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2366 } else
2367 tx_descriptor_addr->special = 0;
2368
2369 tx_descriptor_addr->checksum_start_field = 0;
2370
2371 tdt++;
2372 if (tdt == E1000_TX_FRAME_COUNT)
2373 tdt = 0;
2374
2375 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2376
2377 fibril_mutex_unlock(&e1000->tx_lock);
2378}
2379
2380int main(void)
2381{
2382 int rc = nic_driver_init(NAME);
2383 if (rc != EOK)
2384 return rc;
2385
2386 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2387 &e1000_nic_iface);
2388
2389 ddf_log_init(NAME, LVL_ERROR);
2390 ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
2391 return ddf_driver_main(&e1000_driver);
2392}
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