source: mainline/uspace/drv/nic/e1k/e1k.c@ c4be33a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c4be33a was c4be33a, checked in by Martin Decky <martin@…>, 14 years ago

e1k: reflect infrastructure changes, more code cleanup, enable by default
  • Property mode set to 100644
File size: 52.1 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/interrupt.h>
47#include <devman.h>
48#include <device/hw_res_parsed.h>
49#include <device/pci.h>
50#include <nic.h>
51#include <nil_remote.h>
52#include <ops/nic.h>
53#include <packet_client.h>
54#include <packet_remote.h>
55#include <net/packet_header.h>
56#include "e1k.h"
57
58#define NAME "e1k"
59
60#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
61
62/* Must be power of 8 */
63#define E1000_RX_PACKETS_COUNT 128
64#define E1000_TX_PACKETS_COUNT 128
65
66#define E1000_RECEIVE_ADDRESS 16
67
68/** Maximum receiving packet size */
69#define E1000_MAX_RECEIVE_PACKET_SIZE 2048
70
71/** nic_driver_data_t* -> e1000_t* cast */
72#define DRIVER_DATA_NIC(nic) \
73 ((e1000_t *) nic_get_specific(nic))
74
75/** device_t* -> nic_driver_data_t* cast */
76#define NIC_DATA_DEV(dev) \
77 ((nic_t *) ((dev)->driver_data))
78
79/** device_t* -> e1000_t* cast */
80#define DRIVER_DATA_DEV(dev) \
81 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
82
83/** Cast pointer to uint64_t
84 *
85 * @param ptr Pointer to cast
86 *
87 * @return The uint64_t pointer representation.
88 *
89 */
90#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
91
92/** Cast the memaddr part to the void*
93 *
94 * @param memaddr The memaddr value
95 *
96 */
97#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
98
99#define E1000_REG_BASE(e1000) \
100 ((e1000)->reg_base_virt)
101
102#define E1000_REG_ADDR(e1000, reg) \
103 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
104
105#define E1000_REG_READ(e1000, reg) \
106 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
107
108#define E1000_REG_WRITE(e1000, reg, value) \
109 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
110
111/** E1000 device data */
112typedef struct {
113 /** Physical registers base address */
114 void *reg_base_phys;
115 /** Virtual registers base address */
116 void *reg_base_virt;
117
118 /** Physical tx ring address */
119 void *tx_ring_phys;
120 /** Virtual tx ring address */
121 void *tx_ring_virt;
122
123 /** Packets in tx ring */
124 packet_t **tx_ring_packets;
125
126 /** Physical rx ring address */
127 void *rx_ring_phys;
128 /** Virtual rx ring address */
129 void *rx_ring_virt;
130
131 /** Packets in rx ring */
132 packet_t **rx_ring_packets;
133
134 /** VLAN tag */
135 uint16_t vlan_tag;
136
137 /** Add VLAN tag to packet */
138 bool vlan_tag_add;
139
140 /** Used unicast Receive Address count */
141 unsigned int unicast_ra_count;
142
143 /** Used milticast Receive addrress count */
144 unsigned int multicast_ra_count;
145
146 /** PCI device ID */
147 uint16_t device_id;
148
149 /** The irq assigned */
150 int irq;
151
152 /** Lock for CTRL register */
153 fibril_mutex_t ctrl_lock;
154
155 /** Lock for receiver */
156 fibril_mutex_t rx_lock;
157
158 /** Lock for transmitter */
159 fibril_mutex_t tx_lock;
160
161 /** Lock for EEPROM access */
162 fibril_mutex_t eeprom_lock;
163} e1000_t;
164
165/** Global mutex for work with shared irq structure */
166FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
167
168static int e1000_get_address(e1000_t *, nic_address_t *);
169static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
170static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
171
172static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
173static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
174
175static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
176static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
177static int e1000_get_operation_mode(ddf_fun_t *, int *,
178 nic_channel_mode_t *, nic_role_t *);
179static int e1000_set_operation_mode(ddf_fun_t *, int,
180 nic_channel_mode_t, nic_role_t);
181static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
182static int e1000_autoneg_disable(ddf_fun_t *);
183static int e1000_autoneg_restart(ddf_fun_t *);
184
185static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
186
187/** Network interface options for E1000 card driver */
188static nic_iface_t e1000_nic_iface;
189
190/** Network interface options for E1000 card driver */
191static nic_iface_t e1000_nic_iface = {
192 .set_address = &e1000_set_addr,
193 .get_device_info = &e1000_get_device_info,
194 .get_cable_state = &e1000_get_cable_state,
195 .get_operation_mode = &e1000_get_operation_mode,
196 .set_operation_mode = &e1000_set_operation_mode,
197 .autoneg_enable = &e1000_autoneg_enable,
198 .autoneg_disable = &e1000_autoneg_disable,
199 .autoneg_restart = &e1000_autoneg_restart,
200 .vlan_set_tag = &e1000_vlan_set_tag,
201 .defective_get_mode = &e1000_defective_get_mode,
202 .defective_set_mode = &e1000_defective_set_mode,
203};
204
205/** Basic device operations for E1000 driver */
206static ddf_dev_ops_t e1000_dev_ops;
207
208static int e1000_dev_add(ddf_dev_t *);
209
210/** Basic driver operations for E1000 driver */
211static driver_ops_t e1000_driver_ops = {
212 .dev_add = e1000_dev_add
213};
214
215/** Driver structure for E1000 driver */
216static driver_t e1000_driver = {
217 .name = NAME,
218 .driver_ops = &e1000_driver_ops
219};
220
221/* The default implementation callbacks */
222static int e1000_on_activating(nic_t *);
223static int e1000_on_stopping(nic_t *);
224static void e1000_write_packet(nic_t *, packet_t *);
225
226/** Commands to deal with interrupt
227 *
228 */
229irq_cmd_t e1000_irq_commands[] = {
230 {
231 /* Get the interrupt status */
232 .cmd = CMD_PIO_READ_32,
233 .addr = NULL,
234 .dstarg = 2
235 },
236 {
237 .cmd = CMD_PREDICATE,
238 .value = 2,
239 .srcarg = 2
240 },
241 {
242 /* Disable interrupts until interrupt routine is finished */
243 .cmd = CMD_PIO_WRITE_32,
244 .addr = NULL,
245 .value = 0xffffffff
246 },
247 {
248 .cmd = CMD_ACCEPT
249 }
250};
251
252/** Interrupt code definition */
253irq_code_t e1000_irq_code = {
254 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
255 .cmds = e1000_irq_commands
256};
257
258/** Get the device information
259 *
260 * @param dev NIC device
261 * @param info Information to fill
262 *
263 * @return EOK
264 *
265 */
266static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
267{
268 assert(dev);
269 assert(info);
270
271 bzero(info, sizeof(nic_device_info_t));
272
273 info->vendor_id = 0x8086;
274 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
275 "Intel Corporation");
276 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
277 "Intel Pro");
278
279 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
280 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
281 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
282
283 return EOK;
284}
285
286/** Check the cable state
287 *
288 * @param[in] dev device
289 * @param[out] state state to fill
290 *
291 * @return EOK
292 *
293 */
294static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
295{
296 assert(dev);
297 assert(DRIVER_DATA_DEV(dev));
298 assert(state);
299
300 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
301 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
302 *state = NIC_CS_PLUGGED;
303 else
304 *state = NIC_CS_UNPLUGGED;
305
306 return EOK;
307}
308
309static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
310{
311 return useconds * 4;
312}
313
314/** Get operation mode of the device
315 *
316 */
317static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
318 nic_channel_mode_t *duplex, nic_role_t *role)
319{
320 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
321 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
322
323 if (status & STATUS_FD)
324 *duplex = NIC_CM_FULL_DUPLEX;
325 else
326 *duplex = NIC_CM_HALF_DUPLEX;
327
328 uint32_t speed_bits =
329 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
330
331 if (speed_bits == STATUS_SPEED_10)
332 *speed = 10;
333 else if (speed_bits == STATUS_SPEED_100)
334 *speed = 100;
335 else if ((speed_bits == STATUS_SPEED_1000A) ||
336 (speed_bits == STATUS_SPEED_1000B))
337 *speed = 1000;
338
339 *role = NIC_ROLE_UNKNOWN;
340 return EOK;
341}
342
343static void e1000_link_restart(e1000_t *e1000)
344{
345 fibril_mutex_lock(&e1000->ctrl_lock);
346
347 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
348
349 if (ctrl & CTRL_SLU) {
350 ctrl &= ~(CTRL_SLU);
351 fibril_mutex_unlock(&e1000->ctrl_lock);
352 usleep(10);
353 fibril_mutex_lock(&e1000->ctrl_lock);
354 ctrl |= CTRL_SLU;
355 }
356
357 fibril_mutex_unlock(&e1000->ctrl_lock);
358
359 e1000_link_restart(e1000);
360}
361
362/** Set operation mode of the device
363 *
364 */
365static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
366 nic_channel_mode_t duplex, nic_role_t role)
367{
368 if ((speed != 10) && (speed != 100) && (speed != 1000))
369 return EINVAL;
370
371 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
372 return EINVAL;
373
374 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
375
376 fibril_mutex_lock(&e1000->ctrl_lock);
377 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
378
379 ctrl |= CTRL_FRCSPD;
380 ctrl |= CTRL_FRCDPLX;
381 ctrl &= ~(CTRL_ASDE);
382
383 if (duplex == NIC_CM_FULL_DUPLEX)
384 ctrl |= CTRL_FD;
385 else
386 ctrl &= ~(CTRL_FD);
387
388 ctrl &= ~(CTRL_SPEED_MASK);
389 if (speed == 1000)
390 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
391 else if (speed == 100)
392 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
393 else
394 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
395
396 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
397
398 fibril_mutex_unlock(&e1000->ctrl_lock);
399
400 e1000_link_restart(e1000);
401
402 return EOK;
403}
404
405/** Enable auto-negotiation
406 *
407 * @param dev Device to update
408 * @param advertisement Ignored on E1000
409 *
410 * @return EOK if advertisement mode set successfully
411 *
412 */
413static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
414{
415 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
416
417 fibril_mutex_lock(&e1000->ctrl_lock);
418
419 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
420
421 ctrl &= ~(CTRL_FRCSPD);
422 ctrl &= ~(CTRL_FRCDPLX);
423 ctrl |= CTRL_ASDE;
424
425 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
426
427 fibril_mutex_unlock(&e1000->ctrl_lock);
428
429 e1000_link_restart(e1000);
430
431 return EOK;
432}
433
434/** Disable auto-negotiation
435 *
436 * @param dev Device to update
437 *
438 * @return EOK
439 *
440 */
441static int e1000_autoneg_disable(ddf_fun_t *dev)
442{
443 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
444
445 fibril_mutex_lock(&e1000->ctrl_lock);
446
447 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
448
449 ctrl |= CTRL_FRCSPD;
450 ctrl |= CTRL_FRCDPLX;
451 ctrl &= ~(CTRL_ASDE);
452
453 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
454
455 fibril_mutex_unlock(&e1000->ctrl_lock);
456
457 e1000_link_restart(e1000);
458
459 return EOK;
460}
461
462/** Restart auto-negotiation
463 *
464 * @param dev Device to update
465 *
466 * @return EOK if advertisement mode set successfully
467 *
468 */
469static int e1000_autoneg_restart(ddf_fun_t *dev)
470{
471 return e1000_autoneg_enable(dev, 0);
472}
473
474/** Get state of acceptance of weird packets
475 *
476 * @param device Device to check
477 * @param[out] mode Current mode
478 *
479 */
480static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
481{
482 e1000_t *e1000 = DRIVER_DATA_DEV(device);
483
484 *mode = 0;
485 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
486 if (rctl & RCTL_SBP)
487 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
488
489 return EOK;
490};
491
492/** Set acceptance of weird packets
493 *
494 * @param device Device to update
495 * @param mode Mode to set
496 *
497 * @return ENOTSUP if the mode is not supported
498 * @return EOK of mode was set
499 *
500 */
501static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
502{
503 e1000_t *e1000 = DRIVER_DATA_DEV(device);
504 int rc = EOK;
505
506 fibril_mutex_lock(&e1000->rx_lock);
507
508 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
509 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
510 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
511
512 if (short_mode && bad_mode)
513 rctl |= RCTL_SBP;
514 else if ((!short_mode) && (!bad_mode))
515 rctl &= ~RCTL_SBP;
516 else
517 rc = ENOTSUP;
518
519 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
520
521 fibril_mutex_unlock(&e1000->rx_lock);
522 return rc;
523};
524
525/** Write receive address to RA registr
526 *
527 * @param e1000 E1000 data structure
528 * @param position RA register position
529 * @param address Ethernet address
530 * @param set_av_bit Set the Addtess Valid bit
531 *
532 */
533static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
534 const nic_address_t * address, bool set_av_bit)
535{
536 uint8_t *mac0 = (uint8_t *) address->address;
537 uint8_t *mac1 = (uint8_t *) address->address + 1;
538 uint8_t *mac2 = (uint8_t *) address->address + 2;
539 uint8_t *mac3 = (uint8_t *) address->address + 3;
540 uint8_t *mac4 = (uint8_t *) address->address + 4;
541 uint8_t *mac5 = (uint8_t *) address->address + 5;
542
543 uint32_t rah;
544 uint32_t ral;
545
546 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
547 rah = ((*mac5) << 8) | ((*mac4));
548
549 if (set_av_bit)
550 rah |= RAH_AV;
551 else
552 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
553
554 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
555 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
556}
557
558/** Disable receive address in RA registr
559 *
560 * Clear Address Valid bit
561 *
562 * @param e1000 E1000 data structure
563 * @param position RA register position
564 *
565 */
566static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
567{
568 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
569 rah = rah & ~RAH_AV;
570 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
571}
572
573/** Clear all unicast addresses from RA registers
574 *
575 * @param e1000 E1000 data structure
576 *
577 */
578static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
579{
580 for (unsigned int ra_num = 1;
581 ra_num <= e1000->unicast_ra_count;
582 ra_num++)
583 e1000_disable_receive_address(e1000, ra_num);
584
585 e1000->unicast_ra_count = 0;
586}
587
588/** Clear all multicast addresses from RA registers
589 *
590 * @param e1000 E1000 data structure
591 *
592 */
593static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
594{
595 unsigned int first_multicast_ra_num =
596 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
597
598 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
599 ra_num >= first_multicast_ra_num;
600 ra_num--)
601 e1000_disable_receive_address(e1000, ra_num);
602
603 e1000->multicast_ra_count = 0;
604}
605
606/** Return receive address filter positions count usable for unicast
607 *
608 * @param e1000 E1000 data structure
609 *
610 * @return receive address filter positions count usable for unicast
611 *
612 */
613static unsigned int get_free_unicast_address_count(e1000_t *e1000)
614{
615 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
616}
617
618/** Return receive address filter positions count usable for multicast
619 *
620 * @param e1000 E1000 data structure
621 *
622 * @return receive address filter positions count usable for multicast
623 *
624 */
625static unsigned int get_free_multicast_address_count(e1000_t *e1000)
626{
627 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
628}
629
630/** Write unicast receive addresses to receive address filter registers
631 *
632 * @param e1000 E1000 data structure
633 * @param addr Pointer to address array
634 * @param addr_cnt Address array count
635 *
636 */
637static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
638 const nic_address_t *addr, size_t addr_cnt)
639{
640 assert(addr_cnt <= get_free_unicast_address_count(e1000));
641
642 nic_address_t *addr_iterator = (nic_address_t *) addr;
643
644 /* ra_num = 0 is primary address */
645 for (unsigned int ra_num = 1;
646 ra_num <= addr_cnt;
647 ra_num++) {
648 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
649 addr_iterator++;
650 }
651}
652
653/** Write multicast receive addresses to receive address filter registers
654 *
655 * @param e1000 E1000 data structure
656 * @param addr Pointer to address array
657 * @param addr_cnt Address array count
658 *
659 */
660static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
661 const nic_address_t *addr, size_t addr_cnt)
662{
663 assert(addr_cnt <= get_free_multicast_address_count(e1000));
664
665 nic_address_t *addr_iterator = (nic_address_t *) addr;
666
667 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
668 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
669 ra_num >= first_multicast_ra_num;
670 ra_num--) {
671 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
672 addr_iterator++;
673 }
674}
675
676/** Disable receiving packets for default address
677 *
678 * @param e1000 E1000 data structure
679 *
680 */
681static void disable_ra0_address_filter(e1000_t *e1000)
682{
683 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
684 rah0 = rah0 & ~RAH_AV;
685 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
686}
687
688/** Enable receiving packets for default address
689 *
690 * @param e1000 E1000 data structure
691 *
692 */
693static void enable_ra0_address_filter(e1000_t *e1000)
694{
695 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
696 rah0 = rah0 | RAH_AV;
697 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
698}
699
700/** Disable unicast promiscuous mode
701 *
702 * @param e1000 E1000 data structure
703 *
704 */
705static void e1000_disable_unicast_promisc(e1000_t *e1000)
706{
707 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
708 rctl = rctl & ~RCTL_UPE;
709 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
710}
711
712/** Enable unicast promiscuous mode
713 *
714 * @param e1000 E1000 data structure
715 *
716 */
717static void e1000_enable_unicast_promisc(e1000_t *e1000)
718{
719 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
720 rctl = rctl | RCTL_UPE;
721 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
722}
723
724/** Disable multicast promiscuous mode
725 *
726 * @param e1000 E1000 data structure
727 *
728 */
729static void e1000_disable_multicast_promisc(e1000_t *e1000)
730{
731 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
732 rctl = rctl & ~RCTL_MPE;
733 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
734}
735
736/** Enable multicast promiscuous mode
737 *
738 * @param e1000 E1000 data structure
739 *
740 */
741static void e1000_enable_multicast_promisc(e1000_t *e1000)
742{
743 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
744 rctl = rctl | RCTL_MPE;
745 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
746}
747
748/** Enable accepting of broadcast packets
749 *
750 * @param e1000 E1000 data structure
751 *
752 */
753static void e1000_enable_broadcast_accept(e1000_t *e1000)
754{
755 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
756 rctl = rctl | RCTL_BAM;
757 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
758}
759
760/** Disable accepting of broadcast packets
761 *
762 * @param e1000 E1000 data structure
763 *
764 */
765static void e1000_disable_broadcast_accept(e1000_t *e1000)
766{
767 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
768 rctl = rctl & ~RCTL_BAM;
769 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
770}
771
772/** Enable VLAN filtering according to VFTA registers
773 *
774 * @param e1000 E1000 data structure
775 *
776 */
777static void e1000_enable_vlan_filter(e1000_t *e1000)
778{
779 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
780 rctl = rctl | RCTL_VFE;
781 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
782}
783
784/** Disable VLAN filtering
785 *
786 * @param e1000 E1000 data structure
787 *
788 */
789static void e1000_disable_vlan_filter(e1000_t *e1000)
790{
791 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
792 rctl = rctl & ~RCTL_VFE;
793 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
794}
795
796/** Set multicast packets acceptance mode
797 *
798 * @param nic NIC device to update
799 * @param mode Mode to set
800 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
801 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
802 *
803 * @return EOK
804 *
805 */
806static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
807 const nic_address_t *addr, size_t addr_cnt)
808{
809 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
810 int rc = EOK;
811
812 fibril_mutex_lock(&e1000->rx_lock);
813
814 switch (mode) {
815 case NIC_MULTICAST_BLOCKED:
816 e1000_clear_multicast_receive_addresses(e1000);
817 e1000_disable_multicast_promisc(e1000);
818 nic_report_hw_filtering(nic, -1, 1, -1);
819 break;
820 case NIC_MULTICAST_LIST:
821 e1000_clear_multicast_receive_addresses(e1000);
822 if (addr_cnt > get_free_multicast_address_count(e1000)) {
823 /*
824 * Future work: fill MTA table
825 * Not strictly neccessary, it only saves some compares
826 * in the NIC library.
827 */
828 e1000_enable_multicast_promisc(e1000);
829 nic_report_hw_filtering(nic, -1, 0, -1);
830 } else {
831 e1000_disable_multicast_promisc(e1000);
832 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
833 nic_report_hw_filtering(nic, -1, 1, -1);
834 }
835 break;
836 case NIC_MULTICAST_PROMISC:
837 e1000_enable_multicast_promisc(e1000);
838 e1000_clear_multicast_receive_addresses(e1000);
839 nic_report_hw_filtering(nic, -1, 1, -1);
840 break;
841 default:
842 rc = ENOTSUP;
843 break;
844 }
845
846 fibril_mutex_unlock(&e1000->rx_lock);
847 return rc;
848}
849
850/** Set unicast packets acceptance mode
851 *
852 * @param nic NIC device to update
853 * @param mode Mode to set
854 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
855 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
856 *
857 * @return EOK
858 *
859 */
860static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
861 const nic_address_t *addr, size_t addr_cnt)
862{
863 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
864 int rc = EOK;
865
866 fibril_mutex_lock(&e1000->rx_lock);
867
868 switch (mode) {
869 case NIC_UNICAST_BLOCKED:
870 disable_ra0_address_filter(e1000);
871 e1000_clear_unicast_receive_addresses(e1000);
872 e1000_disable_unicast_promisc(e1000);
873 nic_report_hw_filtering(nic, 1, -1, -1);
874 break;
875 case NIC_UNICAST_DEFAULT:
876 enable_ra0_address_filter(e1000);
877 e1000_clear_unicast_receive_addresses(e1000);
878 e1000_disable_unicast_promisc(e1000);
879 nic_report_hw_filtering(nic, 1, -1, -1);
880 break;
881 case NIC_UNICAST_LIST:
882 enable_ra0_address_filter(e1000);
883 e1000_clear_unicast_receive_addresses(e1000);
884 if (addr_cnt > get_free_unicast_address_count(e1000)) {
885 e1000_enable_unicast_promisc(e1000);
886 nic_report_hw_filtering(nic, 0, -1, -1);
887 } else {
888 e1000_disable_unicast_promisc(e1000);
889 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
890 nic_report_hw_filtering(nic, 1, -1, -1);
891 }
892 break;
893 case NIC_UNICAST_PROMISC:
894 e1000_enable_unicast_promisc(e1000);
895 enable_ra0_address_filter(e1000);
896 e1000_clear_unicast_receive_addresses(e1000);
897 nic_report_hw_filtering(nic, 1, -1, -1);
898 break;
899 default:
900 rc = ENOTSUP;
901 break;
902 }
903
904 fibril_mutex_unlock(&e1000->rx_lock);
905 return rc;
906}
907
908/** Set broadcast packets acceptance mode
909 *
910 * @param nic NIC device to update
911 * @param mode Mode to set
912 *
913 * @return EOK
914 *
915 */
916static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
917{
918 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
919 int rc = EOK;
920
921 fibril_mutex_lock(&e1000->rx_lock);
922
923 switch (mode) {
924 case NIC_BROADCAST_BLOCKED:
925 e1000_disable_broadcast_accept(e1000);
926 break;
927 case NIC_BROADCAST_ACCEPTED:
928 e1000_enable_broadcast_accept(e1000);
929 break;
930 default:
931 rc = ENOTSUP;
932 break;
933 }
934
935 fibril_mutex_unlock(&e1000->rx_lock);
936 return rc;
937}
938
939/** Check if receiving is enabled
940 *
941 * @param e1000 E1000 data structure
942 *
943 * @return true if receiving is enabled
944 *
945 */
946static bool e1000_is_rx_enabled(e1000_t *e1000)
947{
948 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
949 return true;
950
951 return false;
952}
953
954/** Enable receiving
955 *
956 * @param e1000 E1000 data structure
957 *
958 */
959static void e1000_enable_rx(e1000_t *e1000)
960{
961 /* Set Receive Enable Bit */
962 E1000_REG_WRITE(e1000, E1000_RCTL,
963 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
964}
965
966/** Disable receiving
967 *
968 * @param e1000 E1000 data structure
969 *
970 */
971static void e1000_disable_rx(e1000_t *e1000)
972{
973 /* Clear Receive Enable Bit */
974 E1000_REG_WRITE(e1000, E1000_RCTL,
975 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
976}
977
978/** Set VLAN mask
979 *
980 * @param nic NIC device to update
981 * @param vlan_mask VLAN mask
982 *
983 */
984static void e1000_on_vlan_mask_change(nic_t *nic,
985 const nic_vlan_mask_t *vlan_mask)
986{
987 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
988
989 fibril_mutex_lock(&e1000->rx_lock);
990
991 if (vlan_mask) {
992 /*
993 * Disable receiving, so that packet matching
994 * partially written VLAN is not received.
995 */
996 bool rx_enabled = e1000_is_rx_enabled(e1000);
997 if (rx_enabled)
998 e1000_disable_rx(e1000);
999
1000 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1001 uint32_t bitmap_part =
1002 ((uint32_t) vlan_mask->bitmap[i]) |
1003 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1004 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1005 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1006 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1007 }
1008
1009 e1000_enable_vlan_filter(e1000);
1010 if (rx_enabled)
1011 e1000_enable_rx(e1000);
1012 } else
1013 e1000_disable_vlan_filter(e1000);
1014
1015 fibril_mutex_unlock(&e1000->rx_lock);
1016}
1017
1018/** Set VLAN mask
1019 *
1020 * @param device E1000 device
1021 * @param tag VLAN tag
1022 *
1023 * @return EOK
1024 * @return ENOTSUP
1025 *
1026 */
1027static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1028 bool strip)
1029{
1030 /* VLAN CFI bit cannot be set */
1031 if (tag & VLANTAG_CFI)
1032 return ENOTSUP;
1033
1034 /*
1035 * CTRL.VME is neccessary for both strip and add
1036 * but CTRL.VME means stripping tags on receive.
1037 */
1038 if (!strip && add)
1039 return ENOTSUP;
1040
1041 e1000_t *e1000 = DRIVER_DATA_DEV(device);
1042
1043 e1000->vlan_tag = tag;
1044 e1000->vlan_tag_add = add;
1045
1046 fibril_mutex_lock(&e1000->ctrl_lock);
1047
1048 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1049 if (strip)
1050 ctrl |= CTRL_VME;
1051 else
1052 ctrl &= ~CTRL_VME;
1053
1054 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1055
1056 fibril_mutex_unlock(&e1000->ctrl_lock);
1057 return EOK;
1058}
1059
1060/** Fill receive descriptor with new empty packet
1061 *
1062 * Store packet in e1000->rx_ring_packets
1063 *
1064 * @param nic NIC data stricture
1065 * @param offset Receive descriptor offset
1066 *
1067 */
1068static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1069{
1070 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1071 packet_t *packet =
1072 nic_alloc_packet(nic, E1000_MAX_RECEIVE_PACKET_SIZE);
1073
1074 assert(packet);
1075
1076 *(e1000->rx_ring_packets + offset) = packet;
1077 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1078 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1079
1080 void *phys;
1081 int rc =
1082 nic_dma_lock_packet(packet, E1000_MAX_RECEIVE_PACKET_SIZE, &phys);
1083
1084 if (rc == EOK)
1085 rx_descriptor->phys_addr = PTR_TO_U64(phys + packet->data_start);
1086 else
1087 rx_descriptor->phys_addr = 0;
1088
1089 rx_descriptor->length = 0;
1090 rx_descriptor->checksum = 0;
1091 rx_descriptor->status = 0;
1092 rx_descriptor->errors = 0;
1093 rx_descriptor->special = 0;
1094}
1095
1096/** Clear receive descriptor
1097 *
1098 * @param e1000 E1000 data
1099 * @param offset Receive descriptor offset
1100 *
1101 */
1102static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1103{
1104 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1105 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1106
1107 rx_descriptor->length = 0;
1108 rx_descriptor->checksum = 0;
1109 rx_descriptor->status = 0;
1110 rx_descriptor->errors = 0;
1111 rx_descriptor->special = 0;
1112}
1113
1114/** Clear receive descriptor
1115 *
1116 * @param nic NIC data
1117 * @param offset Receive descriptor offset
1118 *
1119 */
1120static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1121{
1122 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1123
1124 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1125 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1126
1127 if (tx_descriptor->length) {
1128 packet_t *old_packet = *(e1000->tx_ring_packets + offset);
1129 if (old_packet)
1130 nic_release_packet(nic, old_packet);
1131 }
1132
1133 tx_descriptor->phys_addr = 0;
1134 tx_descriptor->length = 0;
1135 tx_descriptor->checksum_offset = 0;
1136 tx_descriptor->command = 0;
1137 tx_descriptor->status = 0;
1138 tx_descriptor->checksum_start_field = 0;
1139 tx_descriptor->special = 0;
1140}
1141
1142/** Increment tail pointer for receive or transmit ring
1143 *
1144 * @param tail Old Tail
1145 * @param descriptors_count Ring length
1146 *
1147 * @return New tail
1148 *
1149 */
1150static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1151{
1152 if (tail + 1 == descriptors_count)
1153 return 0;
1154 else
1155 return tail + 1;
1156}
1157
1158/** Receive packets
1159 *
1160 * @param nic NIC data
1161 *
1162 */
1163static void e1000_receive_packets(nic_t *nic)
1164{
1165 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1166
1167 fibril_mutex_lock(&e1000->rx_lock);
1168
1169 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1170 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1171
1172 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1173 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1174
1175 while (rx_descriptor->status & 0x01) {
1176 uint32_t packet_size = rx_descriptor->length - E1000_CRC_SIZE;
1177
1178 packet_t *packet = *(e1000->rx_ring_packets + next_tail);
1179 packet_suffix(packet, packet_size);
1180
1181 nic_dma_unlock_packet(packet, E1000_MAX_RECEIVE_PACKET_SIZE);
1182 nic_received_packet(nic, packet);
1183
1184 e1000_fill_new_rx_descriptor(nic, next_tail);
1185
1186 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1187 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_PACKETS_COUNT);
1188
1189 rx_descriptor = (e1000_rx_descriptor_t *)
1190 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1191 }
1192
1193 fibril_mutex_unlock(&e1000->rx_lock);
1194}
1195
1196/** Enable E1000 interupts
1197 *
1198 * @param e1000 E1000 data structure
1199 *
1200 */
1201static void e1000_enable_interrupts(e1000_t *e1000)
1202{
1203 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1204}
1205
1206/** Disable E1000 interupts
1207 *
1208 * @param e1000 E1000 data structure
1209 *
1210 */
1211static void e1000_disable_interrupts(e1000_t *e1000)
1212{
1213 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1214}
1215
1216/** Interrupt handler implementation
1217 *
1218 * This function is called from e1000_interrupt_handler()
1219 * and e1000_poll()
1220 *
1221 * @param nic NIC data
1222 * @param icr ICR register value
1223 *
1224 */
1225static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1226{
1227 if (icr & ICR_RXT0)
1228 e1000_receive_packets(nic);
1229}
1230
1231/** Handle device interrupt
1232 *
1233 * @param dev E1000 device
1234 * @param iid IPC call id
1235 * @param icall IPC call structure
1236 *
1237 */
1238static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1239 ipc_call_t *icall)
1240{
1241 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1242 nic_t *nic = NIC_DATA_DEV(dev);
1243 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1244
1245 e1000_interrupt_handler_impl(nic, icr);
1246 e1000_enable_interrupts(e1000);
1247}
1248
1249/** Register interrupt handler for the card in the system
1250 *
1251 * Note: The global irq_reg_mutex is locked because of work with global
1252 * structure.
1253 *
1254 * @param nic Driver data
1255 *
1256 * @return EOK if the handler was registered
1257 * @return Negative error code otherwise
1258 *
1259 */
1260inline static int e1000_register_int_handler(nic_t *nic)
1261{
1262 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1263
1264 /* Lock the mutex in whole driver while working with global structure */
1265 fibril_mutex_lock(&irq_reg_mutex);
1266
1267 e1000_irq_code.cmds[0].addr = e1000->reg_base_virt + E1000_ICR;
1268 e1000_irq_code.cmds[2].addr = e1000->reg_base_virt + E1000_IMC;
1269
1270 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1271 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1272
1273 fibril_mutex_unlock(&irq_reg_mutex);
1274 return rc;
1275}
1276
1277/** Force receiving all packets in the receive buffer
1278 *
1279 * @param nic NIC data
1280 *
1281 */
1282static void e1000_poll(nic_t *nic)
1283{
1284 assert(nic);
1285
1286 e1000_t *e1000 = nic_get_specific(nic);
1287 assert(e1000);
1288
1289 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1290 e1000_interrupt_handler_impl(nic, icr);
1291}
1292
1293/** Calculates ITR register interrupt from timeval structure
1294 *
1295 * @param period Period
1296 *
1297 */
1298static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1299{
1300 // TODO: use also tv_sec
1301 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1302}
1303
1304/** Set polling mode
1305 *
1306 * @param device Device to set
1307 * @param mode Mode to set
1308 * @param period Period for NIC_POLL_PERIODIC
1309 *
1310 * @return EOK if succeed
1311 * @return ENOTSUP if the mode is not supported
1312 *
1313 */
1314static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1315 const struct timeval *period)
1316{
1317 assert(nic);
1318
1319 e1000_t *e1000 = nic_get_specific(nic);
1320 assert(e1000);
1321
1322 switch (mode) {
1323 case NIC_POLL_IMMEDIATE:
1324 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1325 e1000_enable_interrupts(e1000);
1326 break;
1327 case NIC_POLL_ON_DEMAND:
1328 e1000_disable_interrupts(e1000);
1329 break;
1330 case NIC_POLL_PERIODIC:
1331 assert(period);
1332 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1333 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1334 e1000_enable_interrupts(e1000);
1335 break;
1336 default:
1337 return ENOTSUP;
1338 }
1339
1340 return EOK;
1341}
1342
1343/** Initialize receive registers
1344 *
1345 * @param e1000 E1000 data structure
1346 *
1347 */
1348static void e1000_initialize_rx_registers(e1000_t *e1000)
1349{
1350 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_PACKETS_COUNT * 16);
1351 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1352
1353 /* It is not posible to let HW use all descriptors */
1354 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_PACKETS_COUNT - 1);
1355
1356 /* Set Broadcast Enable Bit */
1357 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1358}
1359
1360/** Initialize receive structure
1361 *
1362 * @param nic NIC data
1363 *
1364 * @return EOK if succeed
1365 * @return Negative error code otherwise
1366 *
1367 */
1368static int e1000_initialize_rx_structure(nic_t *nic)
1369{
1370 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1371 fibril_mutex_lock(&e1000->rx_lock);
1372
1373 int rc = dmamem_map_anonymous(
1374 E1000_RX_PACKETS_COUNT * sizeof(e1000_rx_descriptor_t),
1375 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
1376 &e1000->rx_ring_virt);
1377 if (rc != EOK)
1378 return rc;
1379
1380 E1000_REG_WRITE(e1000, E1000_RDBAH,
1381 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1382 E1000_REG_WRITE(e1000, E1000_RDBAL,
1383 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1384
1385 e1000->rx_ring_packets =
1386 malloc(E1000_RX_PACKETS_COUNT * sizeof(packet_t *));
1387 // FIXME: Check return value
1388
1389 /* Write descriptor */
1390 for (unsigned int offset = 0;
1391 offset < E1000_RX_PACKETS_COUNT;
1392 offset++)
1393 e1000_fill_new_rx_descriptor(nic, offset);
1394
1395 e1000_initialize_rx_registers(e1000);
1396
1397 fibril_mutex_unlock(&e1000->rx_lock);
1398 return EOK;
1399}
1400
1401/** Uninitialize receive structure
1402 *
1403 * @param nic NIC data
1404 *
1405 */
1406static void e1000_uninitialize_rx_structure(nic_t *nic)
1407{
1408 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1409
1410 /* Write descriptor */
1411 for (unsigned int offset = 0;
1412 offset < E1000_RX_PACKETS_COUNT;
1413 offset++) {
1414 packet_t *packet = *(e1000->rx_ring_packets + offset);
1415 nic_dma_unlock_packet(packet, E1000_MAX_RECEIVE_PACKET_SIZE);
1416 nic_release_packet(nic, packet);
1417 }
1418
1419 free(e1000->rx_ring_packets);
1420 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1421}
1422
1423/** Clear receive descriptor ring
1424 *
1425 * @param e1000 E1000 data
1426 *
1427 */
1428static void e1000_clear_rx_ring(e1000_t *e1000)
1429{
1430 /* Write descriptor */
1431 for (unsigned int offset = 0;
1432 offset < E1000_RX_PACKETS_COUNT;
1433 offset++)
1434 e1000_clear_rx_descriptor(e1000, offset);
1435}
1436
1437/** Initialize filters
1438 *
1439 * @param e1000 E1000 data
1440 *
1441 */
1442static void e1000_initialize_filters(e1000_t *e1000)
1443{
1444 /* Initialize address filter */
1445 e1000->unicast_ra_count = 0;
1446 e1000->multicast_ra_count = 0;
1447 e1000_clear_unicast_receive_addresses(e1000);
1448}
1449
1450/** Initialize VLAN
1451 *
1452 * @param e1000 E1000 data
1453 *
1454 */
1455static void e1000_initialize_vlan(e1000_t *e1000)
1456{
1457 e1000->vlan_tag_add = false;
1458}
1459
1460/** Fill MAC address from EEPROM to RA[0] register
1461 *
1462 * @param e1000 E1000 data
1463 *
1464 */
1465static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1466{
1467 /* MAC address from eeprom to RA[0] */
1468 nic_address_t address;
1469 e1000_eeprom_get_address(e1000, &address);
1470 e1000_write_receive_address(e1000, 0, &address, true);
1471}
1472
1473/** Initialize other registers
1474 *
1475 * @param dev E1000 data.
1476 *
1477 * @return EOK if succeed
1478 * @return Negative error code otherwise
1479 *
1480 */
1481static void e1000_initialize_registers(e1000_t *e1000)
1482{
1483 E1000_REG_WRITE(e1000, E1000_ITR,
1484 e1000_calculate_itr_interval_from_usecs(
1485 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1486 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1487 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1488 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1489 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1490 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1491 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1492}
1493
1494/** Initialize transmit registers
1495 *
1496 * @param e1000 E1000 data.
1497 *
1498 */
1499static void e1000_initialize_tx_registers(e1000_t *e1000)
1500{
1501 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_PACKETS_COUNT * 16);
1502 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1503 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1504
1505 E1000_REG_WRITE(e1000, E1000_TIPG,
1506 10 << TIPG_IPGT_SHIFT |
1507 8 << TIPG_IPGR1_SHIFT |
1508 6 << TIPG_IPGR2_SHIFT);
1509
1510 E1000_REG_WRITE(e1000, E1000_TCTL,
1511 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1512 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1513 TCTL_PSP /* Pad Short Packets */);
1514}
1515
1516/** Initialize transmit structure
1517 *
1518 * @param e1000 E1000 data.
1519 *
1520 */
1521static int e1000_initialize_tx_structure(e1000_t *e1000)
1522{
1523 fibril_mutex_lock(&e1000->tx_lock);
1524
1525 int rc = dmamem_map_anonymous(
1526 E1000_TX_PACKETS_COUNT * sizeof(e1000_tx_descriptor_t),
1527 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
1528 &e1000->tx_ring_virt);
1529 if (rc != EOK)
1530 return rc;
1531
1532 bzero(e1000->tx_ring_virt,
1533 E1000_TX_PACKETS_COUNT * sizeof(e1000_tx_descriptor_t));
1534
1535 E1000_REG_WRITE(e1000, E1000_TDBAH,
1536 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1537 E1000_REG_WRITE(e1000, E1000_TDBAL,
1538 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1539
1540 e1000->tx_ring_packets =
1541 malloc(E1000_TX_PACKETS_COUNT * sizeof(packet_t *));
1542 // FIXME: Check return value
1543
1544 e1000_initialize_tx_registers(e1000);
1545
1546 fibril_mutex_unlock(&e1000->tx_lock);
1547 return EOK;
1548}
1549
1550/** Uninitialize transmit structure
1551 *
1552 * @param nic NIC data
1553 *
1554 */
1555static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1556{
1557 free(e1000->tx_ring_packets);
1558 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1559}
1560
1561/** Clear transmit descriptor ring
1562 *
1563 * @param nic NIC data
1564 *
1565 */
1566static void e1000_clear_tx_ring(nic_t *nic)
1567{
1568 /* Write descriptor */
1569 for (unsigned int offset = 0;
1570 offset < E1000_TX_PACKETS_COUNT;
1571 offset++)
1572 e1000_clear_tx_descriptor(nic, offset);
1573}
1574
1575/** Enable transmit
1576 *
1577 * @param e1000 E1000 data
1578 *
1579 */
1580static void e1000_enable_tx(e1000_t *e1000)
1581{
1582 /* Set Transmit Enable Bit */
1583 E1000_REG_WRITE(e1000, E1000_TCTL,
1584 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1585}
1586
1587/** Disable transmit
1588 *
1589 * @param e1000 E1000 data
1590 *
1591 */
1592static void e1000_disable_tx(e1000_t *e1000)
1593{
1594 /* Clear Transmit Enable Bit */
1595 E1000_REG_WRITE(e1000, E1000_TCTL,
1596 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1597}
1598
1599/** Reset E1000 device
1600 *
1601 * @param e1000 The E1000 data
1602 *
1603 */
1604static int e1000_reset(nic_t *nic)
1605{
1606 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1607
1608 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1609
1610 /* Wait for the reset */
1611 usleep(20);
1612
1613 /* check if RST_BIT cleared */
1614 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1615 return EINVAL;
1616
1617 e1000_initialize_registers(e1000);
1618 e1000_initialize_rx_registers(e1000);
1619 e1000_initialize_tx_registers(e1000);
1620 e1000_fill_mac_from_eeprom(e1000);
1621 e1000_initialize_filters(e1000);
1622 e1000_initialize_vlan(e1000);
1623
1624 return EOK;
1625}
1626
1627/** Activate the device to receive and transmit packets
1628 *
1629 * @param nic NIC driver data
1630 *
1631 * @return EOK if activated successfully
1632 * @return Error code otherwise
1633 *
1634 */
1635static int e1000_on_activating(nic_t *nic)
1636{
1637 assert(nic);
1638
1639 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1640
1641 fibril_mutex_lock(&e1000->rx_lock);
1642 fibril_mutex_lock(&e1000->tx_lock);
1643 fibril_mutex_lock(&e1000->ctrl_lock);
1644
1645 e1000_enable_interrupts(e1000);
1646
1647 nic_enable_interrupt(nic, e1000->irq);
1648
1649 e1000_clear_rx_ring(e1000);
1650 e1000_enable_rx(e1000);
1651
1652 e1000_clear_tx_ring(nic);
1653 e1000_enable_tx(e1000);
1654
1655 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1656 ctrl |= CTRL_SLU;
1657 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1658
1659 fibril_mutex_unlock(&e1000->ctrl_lock);
1660 fibril_mutex_unlock(&e1000->tx_lock);
1661 fibril_mutex_unlock(&e1000->rx_lock);
1662
1663 return EOK;
1664}
1665
1666/** Callback for NIC_STATE_DOWN change
1667 *
1668 * @param nic NIC driver data
1669 *
1670 * @return EOK if succeed
1671 * @return Error code otherwise
1672 *
1673 */
1674static int e1000_on_down_unlocked(nic_t *nic)
1675{
1676 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1677
1678 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1679 ctrl &= ~CTRL_SLU;
1680 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1681
1682 e1000_disable_tx(e1000);
1683 e1000_disable_rx(e1000);
1684
1685 nic_disable_interrupt(nic, e1000->irq);
1686 e1000_disable_interrupts(e1000);
1687
1688 /*
1689 * Wait for the for the end of all data
1690 * transfers to descriptors.
1691 */
1692 usleep(100);
1693
1694 return EOK;
1695}
1696
1697/** Callback for NIC_STATE_DOWN change
1698 *
1699 * @param nic NIC driver data
1700 *
1701 * @return EOK if succeed
1702 * @return Error code otherwise
1703 *
1704 */
1705static int e1000_on_down(nic_t *nic)
1706{
1707 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1708
1709 fibril_mutex_lock(&e1000->rx_lock);
1710 fibril_mutex_lock(&e1000->tx_lock);
1711 fibril_mutex_lock(&e1000->ctrl_lock);
1712
1713 int rc = e1000_on_down_unlocked(nic);
1714
1715 fibril_mutex_unlock(&e1000->ctrl_lock);
1716 fibril_mutex_unlock(&e1000->tx_lock);
1717 fibril_mutex_unlock(&e1000->rx_lock);
1718
1719 return rc;
1720}
1721
1722/** Callback for NIC_STATE_STOPPED change
1723 *
1724 * @param nic NIC driver data
1725 *
1726 * @return EOK if succeed
1727 * @return Error code otherwise
1728 *
1729 */
1730static int e1000_on_stopping(nic_t *nic)
1731{
1732 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1733
1734 fibril_mutex_lock(&e1000->rx_lock);
1735 fibril_mutex_lock(&e1000->tx_lock);
1736 fibril_mutex_lock(&e1000->ctrl_lock);
1737
1738 int rc = e1000_on_down_unlocked(nic);
1739 if (rc == EOK)
1740 rc = e1000_reset(nic);
1741
1742 fibril_mutex_unlock(&e1000->ctrl_lock);
1743 fibril_mutex_unlock(&e1000->tx_lock);
1744 fibril_mutex_unlock(&e1000->rx_lock);
1745
1746 return rc;
1747}
1748
1749/** Create driver data structure
1750 *
1751 * @return Intialized device data structure or NULL
1752 *
1753 */
1754static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1755{
1756 assert(dev);
1757 assert(!dev->driver_data);
1758
1759 nic_t *nic = nic_create_and_bind(dev);
1760 if (!nic)
1761 return NULL;
1762
1763 e1000_t *e1000 = malloc(sizeof(e1000_t));
1764 if (!e1000) {
1765 nic_unbind_and_destroy(dev);
1766 return NULL;
1767 }
1768
1769 bzero(e1000, sizeof(e1000_t));
1770
1771 nic_set_specific(nic, e1000);
1772 nic_set_write_packet_handler(nic, e1000_write_packet);
1773 nic_set_state_change_handlers(nic, e1000_on_activating,
1774 e1000_on_down, e1000_on_stopping);
1775 nic_set_filtering_change_handlers(nic,
1776 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1777 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1778 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1779
1780 fibril_mutex_initialize(&e1000->ctrl_lock);
1781 fibril_mutex_initialize(&e1000->rx_lock);
1782 fibril_mutex_initialize(&e1000->tx_lock);
1783 fibril_mutex_initialize(&e1000->eeprom_lock);
1784
1785 return e1000;
1786}
1787
1788/** Delete driver data structure
1789 *
1790 * @param data E1000 device data structure
1791 *
1792 */
1793inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1794{
1795 assert(dev);
1796
1797 if (dev->driver_data != NULL)
1798 nic_unbind_and_destroy(dev);
1799}
1800
1801/** Clean up the E1000 device structure.
1802 *
1803 * @param dev Device structure.
1804 *
1805 */
1806static void e1000_dev_cleanup(ddf_dev_t *dev)
1807{
1808 assert(dev);
1809
1810 e1000_delete_dev_data(dev);
1811
1812 if (dev->parent_sess != NULL) {
1813 async_hangup(dev->parent_sess);
1814 dev->parent_sess = NULL;
1815 }
1816}
1817
1818/** Fill the irq and io_addr part of device data structure
1819 *
1820 * The hw_resources must be obtained before calling this function
1821 *
1822 * @param dev Device structure
1823 * @param hw_resources Hardware resources obtained from the parent device
1824 *
1825 * @return EOK if succeed
1826 * @return Negative error code otherwise
1827 *
1828 */
1829static int e1000_fill_resource_info(ddf_dev_t *dev,
1830 const hw_res_list_parsed_t *hw_resources)
1831{
1832 assert(dev != NULL);
1833 assert(hw_resources != NULL);
1834 assert(dev->driver_data != NULL);
1835
1836 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1837
1838 if (hw_resources->irqs.count != 1)
1839 return EINVAL;
1840
1841 e1000->irq = hw_resources->irqs.irqs[0];
1842 e1000->reg_base_phys =
1843 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1844
1845 return EOK;
1846}
1847
1848/** Obtain information about hardware resources of the device
1849 *
1850 * The device must be connected to the parent
1851 *
1852 * @param dev Device structure
1853 *
1854 * @return EOK if succeed
1855 * @return Negative error code otherwise
1856 *
1857 */
1858static int e1000_get_resource_info(ddf_dev_t *dev)
1859{
1860 assert(dev != NULL);
1861 assert(NIC_DATA_DEV(dev) != NULL);
1862
1863 hw_res_list_parsed_t hw_res_parsed;
1864 hw_res_list_parsed_init(&hw_res_parsed);
1865
1866 /* Get hw resources form parent driver */
1867 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1868 if (rc != EOK)
1869 return rc;
1870
1871 /* Fill resources information to the device */
1872 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1873 hw_res_list_parsed_clean(&hw_res_parsed);
1874
1875 return rc;
1876}
1877
1878/** Initialize the E1000 device structure
1879 *
1880 * @param dev Device information
1881 *
1882 * @return EOK if succeed
1883 * @return Negative error code otherwise
1884 *
1885 */
1886static int e1000_device_initialize(ddf_dev_t *dev)
1887{
1888 /* Allocate driver data for the device. */
1889 e1000_t *e1000 = e1000_create_dev_data(dev);
1890 if (e1000 == NULL)
1891 return ENOMEM;
1892
1893 /* Obtain and fill hardware resources info */
1894 int rc = e1000_get_resource_info(dev);
1895 if (rc != EOK) {
1896 e1000_dev_cleanup(dev);
1897 return rc;
1898 }
1899
1900 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
1901 &e1000->device_id);
1902 if (rc != EOK) {
1903 e1000_dev_cleanup(dev);
1904 return rc;
1905 }
1906
1907 return EOK;
1908}
1909
1910/** Enable the I/O ports of the device.
1911 *
1912 * @param dev E1000 device.
1913 *
1914 * @return EOK if successed
1915 * @return Negative error code otherwise
1916 *
1917 */
1918static int e1000_pio_enable(ddf_dev_t *dev)
1919{
1920 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1921
1922 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
1923 &e1000->reg_base_virt);
1924 if (rc != EOK)
1925 return EADDRNOTAVAIL;
1926
1927 return EOK;
1928}
1929
1930/** Probe and initialize the newly added device.
1931 *
1932 * @param dev E1000 device.
1933 *
1934 */
1935int e1000_dev_add(ddf_dev_t *dev)
1936{
1937 assert(dev);
1938
1939 /* Initialize device structure for E1000 */
1940 int rc = e1000_device_initialize(dev);
1941 if (rc != EOK)
1942 return rc;
1943
1944 /* Device initialization */
1945 nic_t *nic = dev->driver_data;
1946 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1947
1948 /* Map registers */
1949 rc = e1000_pio_enable(dev);
1950 if (rc != EOK)
1951 goto err_destroy;
1952
1953 e1000_initialize_registers(e1000);
1954 rc = e1000_initialize_tx_structure(e1000);
1955 if (rc != EOK)
1956 goto err_pio;
1957
1958 fibril_mutex_lock(&e1000->rx_lock);
1959
1960 e1000_fill_mac_from_eeprom(e1000);
1961 e1000_initialize_filters(e1000);
1962
1963 fibril_mutex_unlock(&e1000->rx_lock);
1964
1965 e1000_initialize_vlan(e1000);
1966
1967 rc = nic_register_as_ddf_fun(nic, &e1000_dev_ops);
1968 if (rc != EOK)
1969 goto err_tx_structure;
1970
1971 rc = e1000_register_int_handler(nic);
1972 if (rc != EOK)
1973 goto err_tx_structure;
1974
1975 rc = nic_connect_to_services(nic);
1976 if (rc != EOK)
1977 goto err_irq;
1978
1979 rc = e1000_initialize_rx_structure(nic);
1980 if (rc != EOK)
1981 goto err_irq;
1982
1983 nic_address_t e1000_address;
1984 e1000_get_address(e1000, &e1000_address);
1985 rc = nic_report_address(nic, &e1000_address);
1986 if (rc != EOK)
1987 goto err_rx_structure;
1988
1989 struct timeval period;
1990 period.tv_sec = 0;
1991 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
1992 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
1993 if (rc != EOK)
1994 goto err_rx_structure;
1995
1996 return EOK;
1997
1998err_rx_structure:
1999 e1000_uninitialize_rx_structure(nic);
2000err_irq:
2001 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2002err_tx_structure:
2003 e1000_uninitialize_tx_structure(e1000);
2004err_pio:
2005 // TODO: e1000_pio_disable(dev);
2006err_destroy:
2007 e1000_dev_cleanup(dev);
2008 return rc;
2009}
2010
2011/** Read 16-bit value from EEPROM of E1000 adapter
2012 *
2013 * Read using the EERD register.
2014 *
2015 * @param device E1000 device
2016 * @param eeprom_address 8-bit EEPROM address
2017 *
2018 * @return 16-bit value from EEPROM
2019 *
2020 */
2021static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2022{
2023 fibril_mutex_lock(&e1000->eeprom_lock);
2024
2025 uint32_t eerd_done;
2026 uint32_t eerd_address_offset;
2027
2028 switch (e1000->device_id) {
2029 case 0x107c:
2030 case 0x1013:
2031 case 0x1018:
2032 case 0x1019:
2033 case 0x101A:
2034 case 0x1076:
2035 case 0x1077:
2036 case 0x1078:
2037 case 0x10b9:
2038 /* 82541xx and 82547GI/EI */
2039 eerd_done = EERD_DONE_82541XX_82547GI_EI;
2040 eerd_address_offset = EERD_ADDRESS_OFFSET_82541XX_82547GI_EI;
2041 break;
2042 default:
2043 eerd_done = EERD_DONE;
2044 eerd_address_offset = EERD_ADDRESS_OFFSET;
2045 break;
2046 }
2047
2048 /* Write address and START bit to EERD register */
2049 uint32_t write_data = EERD_START |
2050 (((uint32_t) eeprom_address) << eerd_address_offset);
2051 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2052
2053 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2054 while ((eerd & eerd_done) == 0) {
2055 usleep(1);
2056 eerd = E1000_REG_READ(e1000, E1000_EERD);
2057 }
2058
2059 fibril_mutex_unlock(&e1000->eeprom_lock);
2060
2061 return (uint16_t) (eerd >> EERD_DATA_OFFSET);
2062}
2063
2064/** Get MAC address of the E1000 adapter
2065 *
2066 * @param device E1000 device
2067 * @param address Place to store the address
2068 * @param max_len Maximal addresss length to store
2069 *
2070 * @return EOK if succeed
2071 * @return Negative error code otherwise
2072 *
2073 */
2074static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2075{
2076 fibril_mutex_lock(&e1000->rx_lock);
2077
2078 uint8_t *mac0_dest = (uint8_t *) address->address;
2079 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2080 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2081 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2082 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2083 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2084
2085 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2086 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2087
2088 *mac0_dest = (uint8_t) ral;
2089 *mac1_dest = (uint8_t) (ral >> 8);
2090 *mac2_dest = (uint8_t) (ral >> 16);
2091 *mac3_dest = (uint8_t) (ral >> 24);
2092 *mac4_dest = (uint8_t) rah;
2093 *mac5_dest = (uint8_t) (rah >> 8);
2094
2095 fibril_mutex_unlock(&e1000->rx_lock);
2096 return EOK;
2097};
2098
2099/** Set card MAC address
2100 *
2101 * @param device E1000 device
2102 * @param address Address
2103 *
2104 * @return EOK if succeed
2105 * @return Negative error code otherwise
2106 */
2107static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2108{
2109 nic_t *nic = NIC_DATA_DEV(dev);
2110 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2111
2112 fibril_mutex_lock(&e1000->rx_lock);
2113 fibril_mutex_lock(&e1000->tx_lock);
2114
2115 int rc = nic_report_address(nic, addr);
2116 if (rc == EOK)
2117 e1000_write_receive_address(e1000, 0, addr, false);
2118
2119 fibril_mutex_unlock(&e1000->tx_lock);
2120 fibril_mutex_unlock(&e1000->rx_lock);
2121
2122 return rc;
2123}
2124
2125static void e1000_eeprom_get_address(e1000_t *e1000,
2126 nic_address_t *address)
2127{
2128 uint16_t *mac0_dest = (uint16_t *) address->address;
2129 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2130 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2131
2132 *mac0_dest = e1000_eeprom_read(e1000, 0);
2133 *mac2_dest = e1000_eeprom_read(e1000, 1);
2134 *mac4_dest = e1000_eeprom_read(e1000, 2);
2135}
2136
2137/** Send packet
2138 *
2139 * @param nic NIC driver data structure
2140 * @param packet Packet to send
2141 *
2142 * @return EOK if succeed
2143 * @return Error code in the case of error
2144 *
2145 */
2146static void e1000_write_packet(nic_t *nic, packet_t *packet)
2147{
2148 assert(nic);
2149
2150 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2151 fibril_mutex_lock(&e1000->tx_lock);
2152
2153 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2154 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2155 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2156
2157 bool descriptor_available = false;
2158
2159 /* Descriptor never used */
2160 if (tx_descriptor_addr->length == 0)
2161 descriptor_available = true;
2162
2163 /* Descriptor done */
2164 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD) {
2165 descriptor_available = true;
2166 packet_t *old_packet = *(e1000->tx_ring_packets + tdt);
2167 if (old_packet) {
2168 size_t old_packet_size = packet_get_data_length(old_packet);
2169 nic_dma_unlock_packet(old_packet, old_packet_size);
2170 nic_release_packet(nic, old_packet);
2171 }
2172 }
2173
2174 if (!descriptor_available) {
2175 /* Packet lost */
2176 fibril_mutex_unlock(&e1000->tx_lock);
2177 return;
2178 }
2179
2180 size_t packet_size = packet_get_data_length(packet);
2181
2182 void *phys;
2183 int rc = nic_dma_lock_packet(packet, packet_size, &phys);
2184 if (rc != EOK) {
2185 fibril_mutex_unlock(&e1000->tx_lock);
2186 return;
2187 }
2188
2189 *(e1000->tx_ring_packets + tdt) = packet;
2190
2191 tx_descriptor_addr->phys_addr =
2192 PTR_TO_U64(phys + packet->data_start);
2193 tx_descriptor_addr->length = packet_size;
2194
2195 /*
2196 * Report status to STATUS.DD (descriptor done),
2197 * add ethernet CRC, end of packet.
2198 */
2199 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2200 TXDESCRIPTOR_COMMAND_IFCS |
2201 TXDESCRIPTOR_COMMAND_EOP;
2202
2203 tx_descriptor_addr->checksum_offset = 0;
2204 tx_descriptor_addr->status = 0;
2205 if (e1000->vlan_tag_add) {
2206 tx_descriptor_addr->special = e1000->vlan_tag;
2207 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2208 } else
2209 tx_descriptor_addr->special = 0;
2210
2211 tx_descriptor_addr->checksum_start_field = 0;
2212
2213 tdt++;
2214 if (tdt == E1000_TX_PACKETS_COUNT)
2215 tdt = 0;
2216
2217 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2218
2219 fibril_mutex_unlock(&e1000->tx_lock);
2220}
2221
2222int main(void)
2223{
2224 int rc = nic_driver_init(NAME);
2225 if (rc != EOK)
2226 return rc;
2227
2228 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2229 &e1000_nic_iface);
2230 return ddf_driver_main(&e1000_driver);
2231}
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