source: mainline/uspace/drv/nic/e1k/e1k.c@ 033ebc25

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 033ebc25 was 3bacee1, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Make ccheck-fix again and commit more good files.
  • Property mode set to 100644
File size: 56.3 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <async.h>
36#include <assert.h>
37#include <stdio.h>
38#include <errno.h>
39#include <adt/list.h>
40#include <align.h>
41#include <byteorder.h>
42#include <as.h>
43#include <ddi.h>
44#include <ddf/log.h>
45#include <ddf/interrupt.h>
46#include <device/hw_res.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#define NAME "e1k"
54
55#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
56
57/* Must be power of 8 */
58#define E1000_RX_FRAME_COUNT 128
59#define E1000_TX_FRAME_COUNT 128
60
61#define E1000_RECEIVE_ADDRESS 16
62
63/** Maximum sending frame size */
64#define E1000_MAX_SEND_FRAME_SIZE 2048
65/** Maximum receiving frame size */
66#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
67
68/** nic_driver_data_t* -> e1000_t* cast */
69#define DRIVER_DATA_NIC(nic) \
70 ((e1000_t *) nic_get_specific(nic))
71
72/** ddf_fun_t * -> nic_driver_data_t* cast */
73#define NIC_DATA_FUN(fun) \
74 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
75
76/** ddf_dev_t * -> nic_driver_data_t* cast */
77#define NIC_DATA_DEV(dev) \
78 ((nic_t *) ddf_dev_data_get(dev))
79
80/** ddf_dev_t * -> e1000_t* cast */
81#define DRIVER_DATA_DEV(dev) \
82 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
83
84/** ddf_fun_t * -> e1000_t* cast */
85#define DRIVER_DATA_FUN(fun) \
86 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
87
88/** Cast pointer to uint64_t
89 *
90 * @param ptr Pointer to cast
91 *
92 * @return The uint64_t pointer representation.
93 *
94 */
95#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
96
97/** Cast the memaddr part to the void*
98 *
99 * @param memaddr The memaddr value
100 *
101 */
102#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
103
104#define E1000_REG_BASE(e1000) \
105 ((e1000)->reg_base_virt)
106
107#define E1000_REG_ADDR(e1000, reg) \
108 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
109
110#define E1000_REG_READ(e1000, reg) \
111 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
112
113#define E1000_REG_WRITE(e1000, reg, value) \
114 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
115
116/** E1000 device data */
117typedef struct {
118 /** DDF device */
119 ddf_dev_t *dev;
120 /** Parent session */
121 async_sess_t *parent_sess;
122 /** Device configuration */
123 e1000_info_t info;
124
125 /** Physical registers base address */
126 void *reg_base_phys;
127 /** Virtual registers base address */
128 void *reg_base_virt;
129
130 /** Physical tx ring address */
131 uintptr_t tx_ring_phys;
132 /** Virtual tx ring address */
133 void *tx_ring_virt;
134
135 /** Ring of TX frames, physical address */
136 uintptr_t *tx_frame_phys;
137 /** Ring of TX frames, virtual address */
138 void **tx_frame_virt;
139
140 /** Physical rx ring address */
141 uintptr_t rx_ring_phys;
142 /** Virtual rx ring address */
143 void *rx_ring_virt;
144
145 /** Ring of RX frames, physical address */
146 uintptr_t *rx_frame_phys;
147 /** Ring of RX frames, virtual address */
148 void **rx_frame_virt;
149
150 /** VLAN tag */
151 uint16_t vlan_tag;
152
153 /** Add VLAN tag to frame */
154 bool vlan_tag_add;
155
156 /** Used unicast Receive Address count */
157 unsigned int unicast_ra_count;
158
159 /** Used milticast Receive addrress count */
160 unsigned int multicast_ra_count;
161
162 /** The irq assigned */
163 int irq;
164
165 /** Lock for CTRL register */
166 fibril_mutex_t ctrl_lock;
167
168 /** Lock for receiver */
169 fibril_mutex_t rx_lock;
170
171 /** Lock for transmitter */
172 fibril_mutex_t tx_lock;
173
174 /** Lock for EEPROM access */
175 fibril_mutex_t eeprom_lock;
176} e1000_t;
177
178/** Global mutex for work with shared irq structure */
179FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
180
181static errno_t e1000_get_address(e1000_t *, nic_address_t *);
182static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
183static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
184
185static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
186static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
187
188static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
189static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
190static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
191 nic_channel_mode_t *, nic_role_t *);
192static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
193 nic_channel_mode_t, nic_role_t);
194static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
195static errno_t e1000_autoneg_disable(ddf_fun_t *);
196static errno_t e1000_autoneg_restart(ddf_fun_t *);
197
198static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
199
200/** Network interface options for E1000 card driver */
201static nic_iface_t e1000_nic_iface;
202
203/** Network interface options for E1000 card driver */
204static nic_iface_t e1000_nic_iface = {
205 .set_address = &e1000_set_addr,
206 .get_device_info = &e1000_get_device_info,
207 .get_cable_state = &e1000_get_cable_state,
208 .get_operation_mode = &e1000_get_operation_mode,
209 .set_operation_mode = &e1000_set_operation_mode,
210 .autoneg_enable = &e1000_autoneg_enable,
211 .autoneg_disable = &e1000_autoneg_disable,
212 .autoneg_restart = &e1000_autoneg_restart,
213 .vlan_set_tag = &e1000_vlan_set_tag,
214 .defective_get_mode = &e1000_defective_get_mode,
215 .defective_set_mode = &e1000_defective_set_mode,
216};
217
218/** Basic device operations for E1000 driver */
219static ddf_dev_ops_t e1000_dev_ops;
220
221static errno_t e1000_dev_add(ddf_dev_t *);
222
223/** Basic driver operations for E1000 driver */
224static driver_ops_t e1000_driver_ops = {
225 .dev_add = e1000_dev_add
226};
227
228/** Driver structure for E1000 driver */
229static driver_t e1000_driver = {
230 .name = NAME,
231 .driver_ops = &e1000_driver_ops
232};
233
234/* The default implementation callbacks */
235static errno_t e1000_on_activating(nic_t *);
236static errno_t e1000_on_stopping(nic_t *);
237static void e1000_send_frame(nic_t *, void *, size_t);
238
239/** PIO ranges used in the IRQ code. */
240irq_pio_range_t e1000_irq_pio_ranges[] = {
241 {
242 .base = 0,
243 .size = PAGE_SIZE, /* XXX */
244 }
245};
246
247/** Commands to deal with interrupt
248 *
249 */
250irq_cmd_t e1000_irq_commands[] = {
251 {
252 /* Get the interrupt status */
253 .cmd = CMD_PIO_READ_32,
254 .addr = NULL,
255 .dstarg = 2
256 },
257 {
258 .cmd = CMD_PREDICATE,
259 .value = 2,
260 .srcarg = 2
261 },
262 {
263 /* Disable interrupts until interrupt routine is finished */
264 .cmd = CMD_PIO_WRITE_32,
265 .addr = NULL,
266 .value = 0xffffffff
267 },
268 {
269 .cmd = CMD_ACCEPT
270 }
271};
272
273/** Interrupt code definition */
274irq_code_t e1000_irq_code = {
275 .rangecount = sizeof(e1000_irq_pio_ranges) /
276 sizeof(irq_pio_range_t),
277 .ranges = e1000_irq_pio_ranges,
278 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
279 .cmds = e1000_irq_commands
280};
281
282/** Get the device information
283 *
284 * @param dev NIC device
285 * @param info Information to fill
286 *
287 * @return EOK
288 *
289 */
290static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
291{
292 assert(dev);
293 assert(info);
294
295 memset(info, 0, sizeof(nic_device_info_t));
296
297 info->vendor_id = 0x8086;
298 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
299 "Intel Corporation");
300 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
301 "Intel Pro");
302
303 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
304 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
305 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
306
307 return EOK;
308}
309
310/** Check the cable state
311 *
312 * @param[in] dev device
313 * @param[out] state state to fill
314 *
315 * @return EOK
316 *
317 */
318static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
319{
320 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
321 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
322 *state = NIC_CS_PLUGGED;
323 else
324 *state = NIC_CS_UNPLUGGED;
325
326 return EOK;
327}
328
329static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
330{
331 return useconds * 4;
332}
333
334/** Get operation mode of the device
335 *
336 */
337static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
338 nic_channel_mode_t *duplex, nic_role_t *role)
339{
340 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
341 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
342
343 if (status & STATUS_FD)
344 *duplex = NIC_CM_FULL_DUPLEX;
345 else
346 *duplex = NIC_CM_HALF_DUPLEX;
347
348 uint32_t speed_bits =
349 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
350
351 if (speed_bits == STATUS_SPEED_10)
352 *speed = 10;
353 else if (speed_bits == STATUS_SPEED_100)
354 *speed = 100;
355 else if ((speed_bits == STATUS_SPEED_1000A) ||
356 (speed_bits == STATUS_SPEED_1000B))
357 *speed = 1000;
358
359 *role = NIC_ROLE_UNKNOWN;
360 return EOK;
361}
362
363static void e1000_link_restart(e1000_t *e1000)
364{
365 fibril_mutex_lock(&e1000->ctrl_lock);
366
367 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
368
369 if (ctrl & CTRL_SLU) {
370 ctrl &= ~(CTRL_SLU);
371 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
372 fibril_mutex_unlock(&e1000->ctrl_lock);
373
374 async_usleep(10);
375
376 fibril_mutex_lock(&e1000->ctrl_lock);
377 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
378 ctrl |= CTRL_SLU;
379 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
380 }
381
382 fibril_mutex_unlock(&e1000->ctrl_lock);
383}
384
385/** Set operation mode of the device
386 *
387 */
388static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
389 nic_channel_mode_t duplex, nic_role_t role)
390{
391 if ((speed != 10) && (speed != 100) && (speed != 1000))
392 return EINVAL;
393
394 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
395 return EINVAL;
396
397 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
398
399 fibril_mutex_lock(&e1000->ctrl_lock);
400 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
401
402 ctrl |= CTRL_FRCSPD;
403 ctrl |= CTRL_FRCDPLX;
404 ctrl &= ~(CTRL_ASDE);
405
406 if (duplex == NIC_CM_FULL_DUPLEX)
407 ctrl |= CTRL_FD;
408 else
409 ctrl &= ~(CTRL_FD);
410
411 ctrl &= ~(CTRL_SPEED_MASK);
412 if (speed == 1000)
413 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
414 else if (speed == 100)
415 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
416 else
417 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
418
419 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
420
421 fibril_mutex_unlock(&e1000->ctrl_lock);
422
423 e1000_link_restart(e1000);
424
425 return EOK;
426}
427
428/** Enable auto-negotiation
429 *
430 * @param dev Device to update
431 * @param advertisement Ignored on E1000
432 *
433 * @return EOK if advertisement mode set successfully
434 *
435 */
436static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
437{
438 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
439
440 fibril_mutex_lock(&e1000->ctrl_lock);
441
442 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
443
444 ctrl &= ~(CTRL_FRCSPD);
445 ctrl &= ~(CTRL_FRCDPLX);
446 ctrl |= CTRL_ASDE;
447
448 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
449
450 fibril_mutex_unlock(&e1000->ctrl_lock);
451
452 e1000_link_restart(e1000);
453
454 return EOK;
455}
456
457/** Disable auto-negotiation
458 *
459 * @param dev Device to update
460 *
461 * @return EOK
462 *
463 */
464static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
465{
466 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
467
468 fibril_mutex_lock(&e1000->ctrl_lock);
469
470 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
471
472 ctrl |= CTRL_FRCSPD;
473 ctrl |= CTRL_FRCDPLX;
474 ctrl &= ~(CTRL_ASDE);
475
476 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
477
478 fibril_mutex_unlock(&e1000->ctrl_lock);
479
480 e1000_link_restart(e1000);
481
482 return EOK;
483}
484
485/** Restart auto-negotiation
486 *
487 * @param dev Device to update
488 *
489 * @return EOK if advertisement mode set successfully
490 *
491 */
492static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
493{
494 return e1000_autoneg_enable(dev, 0);
495}
496
497/** Get state of acceptance of weird frames
498 *
499 * @param device Device to check
500 * @param[out] mode Current mode
501 *
502 */
503static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
504{
505 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
506
507 *mode = 0;
508 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
509 if (rctl & RCTL_SBP)
510 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
511
512 return EOK;
513}
514
515/** Set acceptance of weird frames
516 *
517 * @param device Device to update
518 * @param mode Mode to set
519 *
520 * @return ENOTSUP if the mode is not supported
521 * @return EOK of mode was set
522 *
523 */
524static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
525{
526 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
527 errno_t rc = EOK;
528
529 fibril_mutex_lock(&e1000->rx_lock);
530
531 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
532 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
533 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
534
535 if (short_mode && bad_mode)
536 rctl |= RCTL_SBP;
537 else if ((!short_mode) && (!bad_mode))
538 rctl &= ~RCTL_SBP;
539 else
540 rc = ENOTSUP;
541
542 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
543
544 fibril_mutex_unlock(&e1000->rx_lock);
545 return rc;
546}
547
548/** Write receive address to RA registr
549 *
550 * @param e1000 E1000 data structure
551 * @param position RA register position
552 * @param address Ethernet address
553 * @param set_av_bit Set the Addtess Valid bit
554 *
555 */
556static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
557 const nic_address_t *address, bool set_av_bit)
558{
559 uint8_t *mac0 = (uint8_t *) address->address;
560 uint8_t *mac1 = (uint8_t *) address->address + 1;
561 uint8_t *mac2 = (uint8_t *) address->address + 2;
562 uint8_t *mac3 = (uint8_t *) address->address + 3;
563 uint8_t *mac4 = (uint8_t *) address->address + 4;
564 uint8_t *mac5 = (uint8_t *) address->address + 5;
565
566 uint32_t rah;
567 uint32_t ral;
568
569 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
570 rah = ((*mac5) << 8) | ((*mac4));
571
572 if (set_av_bit)
573 rah |= RAH_AV;
574 else
575 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
576
577 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
578 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
579}
580
581/** Disable receive address in RA registr
582 *
583 * Clear Address Valid bit
584 *
585 * @param e1000 E1000 data structure
586 * @param position RA register position
587 *
588 */
589static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
590{
591 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
592 rah = rah & ~RAH_AV;
593 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
594}
595
596/** Clear all unicast addresses from RA registers
597 *
598 * @param e1000 E1000 data structure
599 *
600 */
601static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
602{
603 for (unsigned int ra_num = 1;
604 ra_num <= e1000->unicast_ra_count;
605 ra_num++)
606 e1000_disable_receive_address(e1000, ra_num);
607
608 e1000->unicast_ra_count = 0;
609}
610
611/** Clear all multicast addresses from RA registers
612 *
613 * @param e1000 E1000 data structure
614 *
615 */
616static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
617{
618 unsigned int first_multicast_ra_num =
619 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
620
621 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
622 ra_num >= first_multicast_ra_num;
623 ra_num--)
624 e1000_disable_receive_address(e1000, ra_num);
625
626 e1000->multicast_ra_count = 0;
627}
628
629/** Return receive address filter positions count usable for unicast
630 *
631 * @param e1000 E1000 data structure
632 *
633 * @return receive address filter positions count usable for unicast
634 *
635 */
636static unsigned int get_free_unicast_address_count(e1000_t *e1000)
637{
638 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
639}
640
641/** Return receive address filter positions count usable for multicast
642 *
643 * @param e1000 E1000 data structure
644 *
645 * @return receive address filter positions count usable for multicast
646 *
647 */
648static unsigned int get_free_multicast_address_count(e1000_t *e1000)
649{
650 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
651}
652
653/** Write unicast receive addresses to receive address filter registers
654 *
655 * @param e1000 E1000 data structure
656 * @param addr Pointer to address array
657 * @param addr_cnt Address array count
658 *
659 */
660static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
661 const nic_address_t *addr, size_t addr_cnt)
662{
663 assert(addr_cnt <= get_free_unicast_address_count(e1000));
664
665 nic_address_t *addr_iterator = (nic_address_t *) addr;
666
667 /* ra_num = 0 is primary address */
668 for (unsigned int ra_num = 1;
669 ra_num <= addr_cnt;
670 ra_num++) {
671 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
672 addr_iterator++;
673 }
674}
675
676/** Write multicast receive addresses to receive address filter registers
677 *
678 * @param e1000 E1000 data structure
679 * @param addr Pointer to address array
680 * @param addr_cnt Address array count
681 *
682 */
683static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
684 const nic_address_t *addr, size_t addr_cnt)
685{
686 assert(addr_cnt <= get_free_multicast_address_count(e1000));
687
688 nic_address_t *addr_iterator = (nic_address_t *) addr;
689
690 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
691 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
692 ra_num >= first_multicast_ra_num;
693 ra_num--) {
694 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
695 addr_iterator++;
696 }
697}
698
699/** Disable receiving frames for default address
700 *
701 * @param e1000 E1000 data structure
702 *
703 */
704static void disable_ra0_address_filter(e1000_t *e1000)
705{
706 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
707 rah0 = rah0 & ~RAH_AV;
708 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
709}
710
711/** Enable receiving frames for default address
712 *
713 * @param e1000 E1000 data structure
714 *
715 */
716static void enable_ra0_address_filter(e1000_t *e1000)
717{
718 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
719 rah0 = rah0 | RAH_AV;
720 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
721}
722
723/** Disable unicast promiscuous mode
724 *
725 * @param e1000 E1000 data structure
726 *
727 */
728static void e1000_disable_unicast_promisc(e1000_t *e1000)
729{
730 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
731 rctl = rctl & ~RCTL_UPE;
732 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
733}
734
735/** Enable unicast promiscuous mode
736 *
737 * @param e1000 E1000 data structure
738 *
739 */
740static void e1000_enable_unicast_promisc(e1000_t *e1000)
741{
742 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
743 rctl = rctl | RCTL_UPE;
744 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
745}
746
747/** Disable multicast promiscuous mode
748 *
749 * @param e1000 E1000 data structure
750 *
751 */
752static void e1000_disable_multicast_promisc(e1000_t *e1000)
753{
754 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
755 rctl = rctl & ~RCTL_MPE;
756 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
757}
758
759/** Enable multicast promiscuous mode
760 *
761 * @param e1000 E1000 data structure
762 *
763 */
764static void e1000_enable_multicast_promisc(e1000_t *e1000)
765{
766 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
767 rctl = rctl | RCTL_MPE;
768 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
769}
770
771/** Enable accepting of broadcast frames
772 *
773 * @param e1000 E1000 data structure
774 *
775 */
776static void e1000_enable_broadcast_accept(e1000_t *e1000)
777{
778 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
779 rctl = rctl | RCTL_BAM;
780 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
781}
782
783/** Disable accepting of broadcast frames
784 *
785 * @param e1000 E1000 data structure
786 *
787 */
788static void e1000_disable_broadcast_accept(e1000_t *e1000)
789{
790 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
791 rctl = rctl & ~RCTL_BAM;
792 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
793}
794
795/** Enable VLAN filtering according to VFTA registers
796 *
797 * @param e1000 E1000 data structure
798 *
799 */
800static void e1000_enable_vlan_filter(e1000_t *e1000)
801{
802 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
803 rctl = rctl | RCTL_VFE;
804 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
805}
806
807/** Disable VLAN filtering
808 *
809 * @param e1000 E1000 data structure
810 *
811 */
812static void e1000_disable_vlan_filter(e1000_t *e1000)
813{
814 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
815 rctl = rctl & ~RCTL_VFE;
816 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
817}
818
819/** Set multicast frames acceptance mode
820 *
821 * @param nic NIC device to update
822 * @param mode Mode to set
823 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
824 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
825 *
826 * @return EOK
827 *
828 */
829static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
830 const nic_address_t *addr, size_t addr_cnt)
831{
832 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
833 errno_t rc = EOK;
834
835 fibril_mutex_lock(&e1000->rx_lock);
836
837 switch (mode) {
838 case NIC_MULTICAST_BLOCKED:
839 e1000_clear_multicast_receive_addresses(e1000);
840 e1000_disable_multicast_promisc(e1000);
841 nic_report_hw_filtering(nic, -1, 1, -1);
842 break;
843 case NIC_MULTICAST_LIST:
844 e1000_clear_multicast_receive_addresses(e1000);
845 if (addr_cnt > get_free_multicast_address_count(e1000)) {
846 /*
847 * Future work: fill MTA table
848 * Not strictly neccessary, it only saves some compares
849 * in the NIC library.
850 */
851 e1000_enable_multicast_promisc(e1000);
852 nic_report_hw_filtering(nic, -1, 0, -1);
853 } else {
854 e1000_disable_multicast_promisc(e1000);
855 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
856 nic_report_hw_filtering(nic, -1, 1, -1);
857 }
858 break;
859 case NIC_MULTICAST_PROMISC:
860 e1000_enable_multicast_promisc(e1000);
861 e1000_clear_multicast_receive_addresses(e1000);
862 nic_report_hw_filtering(nic, -1, 1, -1);
863 break;
864 default:
865 rc = ENOTSUP;
866 break;
867 }
868
869 fibril_mutex_unlock(&e1000->rx_lock);
870 return rc;
871}
872
873/** Set unicast frames acceptance mode
874 *
875 * @param nic NIC device to update
876 * @param mode Mode to set
877 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
878 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
879 *
880 * @return EOK
881 *
882 */
883static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
884 const nic_address_t *addr, size_t addr_cnt)
885{
886 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
887 errno_t rc = EOK;
888
889 fibril_mutex_lock(&e1000->rx_lock);
890
891 switch (mode) {
892 case NIC_UNICAST_BLOCKED:
893 disable_ra0_address_filter(e1000);
894 e1000_clear_unicast_receive_addresses(e1000);
895 e1000_disable_unicast_promisc(e1000);
896 nic_report_hw_filtering(nic, 1, -1, -1);
897 break;
898 case NIC_UNICAST_DEFAULT:
899 enable_ra0_address_filter(e1000);
900 e1000_clear_unicast_receive_addresses(e1000);
901 e1000_disable_unicast_promisc(e1000);
902 nic_report_hw_filtering(nic, 1, -1, -1);
903 break;
904 case NIC_UNICAST_LIST:
905 enable_ra0_address_filter(e1000);
906 e1000_clear_unicast_receive_addresses(e1000);
907 if (addr_cnt > get_free_unicast_address_count(e1000)) {
908 e1000_enable_unicast_promisc(e1000);
909 nic_report_hw_filtering(nic, 0, -1, -1);
910 } else {
911 e1000_disable_unicast_promisc(e1000);
912 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
913 nic_report_hw_filtering(nic, 1, -1, -1);
914 }
915 break;
916 case NIC_UNICAST_PROMISC:
917 e1000_enable_unicast_promisc(e1000);
918 enable_ra0_address_filter(e1000);
919 e1000_clear_unicast_receive_addresses(e1000);
920 nic_report_hw_filtering(nic, 1, -1, -1);
921 break;
922 default:
923 rc = ENOTSUP;
924 break;
925 }
926
927 fibril_mutex_unlock(&e1000->rx_lock);
928 return rc;
929}
930
931/** Set broadcast frames acceptance mode
932 *
933 * @param nic NIC device to update
934 * @param mode Mode to set
935 *
936 * @return EOK
937 *
938 */
939static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
940{
941 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
942 errno_t rc = EOK;
943
944 fibril_mutex_lock(&e1000->rx_lock);
945
946 switch (mode) {
947 case NIC_BROADCAST_BLOCKED:
948 e1000_disable_broadcast_accept(e1000);
949 break;
950 case NIC_BROADCAST_ACCEPTED:
951 e1000_enable_broadcast_accept(e1000);
952 break;
953 default:
954 rc = ENOTSUP;
955 break;
956 }
957
958 fibril_mutex_unlock(&e1000->rx_lock);
959 return rc;
960}
961
962/** Check if receiving is enabled
963 *
964 * @param e1000 E1000 data structure
965 *
966 * @return true if receiving is enabled
967 *
968 */
969static bool e1000_is_rx_enabled(e1000_t *e1000)
970{
971 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
972 return true;
973
974 return false;
975}
976
977/** Enable receiving
978 *
979 * @param e1000 E1000 data structure
980 *
981 */
982static void e1000_enable_rx(e1000_t *e1000)
983{
984 /* Set Receive Enable Bit */
985 E1000_REG_WRITE(e1000, E1000_RCTL,
986 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
987}
988
989/** Disable receiving
990 *
991 * @param e1000 E1000 data structure
992 *
993 */
994static void e1000_disable_rx(e1000_t *e1000)
995{
996 /* Clear Receive Enable Bit */
997 E1000_REG_WRITE(e1000, E1000_RCTL,
998 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
999}
1000
1001/** Set VLAN mask
1002 *
1003 * @param nic NIC device to update
1004 * @param vlan_mask VLAN mask
1005 *
1006 */
1007static void e1000_on_vlan_mask_change(nic_t *nic,
1008 const nic_vlan_mask_t *vlan_mask)
1009{
1010 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1011
1012 fibril_mutex_lock(&e1000->rx_lock);
1013
1014 if (vlan_mask) {
1015 /*
1016 * Disable receiving, so that frame matching
1017 * partially written VLAN is not received.
1018 */
1019 bool rx_enabled = e1000_is_rx_enabled(e1000);
1020 if (rx_enabled)
1021 e1000_disable_rx(e1000);
1022
1023 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1024 uint32_t bitmap_part =
1025 ((uint32_t) vlan_mask->bitmap[i]) |
1026 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1027 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1028 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1029 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1030 }
1031
1032 e1000_enable_vlan_filter(e1000);
1033 if (rx_enabled)
1034 e1000_enable_rx(e1000);
1035 } else
1036 e1000_disable_vlan_filter(e1000);
1037
1038 fibril_mutex_unlock(&e1000->rx_lock);
1039}
1040
1041/** Set VLAN mask
1042 *
1043 * @param device E1000 device
1044 * @param tag VLAN tag
1045 *
1046 * @return EOK
1047 * @return ENOTSUP
1048 *
1049 */
1050static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1051 bool strip)
1052{
1053 /* VLAN CFI bit cannot be set */
1054 if (tag & VLANTAG_CFI)
1055 return ENOTSUP;
1056
1057 /*
1058 * CTRL.VME is neccessary for both strip and add
1059 * but CTRL.VME means stripping tags on receive.
1060 */
1061 if (!strip && add)
1062 return ENOTSUP;
1063
1064 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1065
1066 e1000->vlan_tag = tag;
1067 e1000->vlan_tag_add = add;
1068
1069 fibril_mutex_lock(&e1000->ctrl_lock);
1070
1071 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1072 if (strip)
1073 ctrl |= CTRL_VME;
1074 else
1075 ctrl &= ~CTRL_VME;
1076
1077 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1078
1079 fibril_mutex_unlock(&e1000->ctrl_lock);
1080 return EOK;
1081}
1082
1083/** Fill receive descriptor with new empty buffer
1084 *
1085 * Store frame in e1000->rx_frame_phys
1086 *
1087 * @param nic NIC data stricture
1088 * @param offset Receive descriptor offset
1089 *
1090 */
1091static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1092{
1093 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1094
1095 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1096 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1097
1098 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1099 rx_descriptor->length = 0;
1100 rx_descriptor->checksum = 0;
1101 rx_descriptor->status = 0;
1102 rx_descriptor->errors = 0;
1103 rx_descriptor->special = 0;
1104}
1105
1106/** Clear receive descriptor
1107 *
1108 * @param e1000 E1000 data
1109 * @param offset Receive descriptor offset
1110 *
1111 */
1112static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1113{
1114 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1115 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1116
1117 rx_descriptor->length = 0;
1118 rx_descriptor->checksum = 0;
1119 rx_descriptor->status = 0;
1120 rx_descriptor->errors = 0;
1121 rx_descriptor->special = 0;
1122}
1123
1124/** Clear receive descriptor
1125 *
1126 * @param nic NIC data
1127 * @param offset Receive descriptor offset
1128 *
1129 */
1130static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1131{
1132 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1133
1134 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1135 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1136
1137 tx_descriptor->phys_addr = 0;
1138 tx_descriptor->length = 0;
1139 tx_descriptor->checksum_offset = 0;
1140 tx_descriptor->command = 0;
1141 tx_descriptor->status = 0;
1142 tx_descriptor->checksum_start_field = 0;
1143 tx_descriptor->special = 0;
1144}
1145
1146/** Increment tail pointer for receive or transmit ring
1147 *
1148 * @param tail Old Tail
1149 * @param descriptors_count Ring length
1150 *
1151 * @return New tail
1152 *
1153 */
1154static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1155{
1156 if (tail + 1 == descriptors_count)
1157 return 0;
1158 else
1159 return tail + 1;
1160}
1161
1162/** Receive frames
1163 *
1164 * @param nic NIC data
1165 *
1166 */
1167static void e1000_receive_frames(nic_t *nic)
1168{
1169 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1170
1171 fibril_mutex_lock(&e1000->rx_lock);
1172
1173 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1174 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1175
1176 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1177 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1178
1179 while (rx_descriptor->status & 0x01) {
1180 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1181
1182 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1183 if (frame != NULL) {
1184 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1185 nic_received_frame(nic, frame);
1186 } else {
1187 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1188 }
1189
1190 e1000_fill_new_rx_descriptor(nic, next_tail);
1191
1192 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1193 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1194
1195 rx_descriptor = (e1000_rx_descriptor_t *)
1196 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1197 }
1198
1199 fibril_mutex_unlock(&e1000->rx_lock);
1200}
1201
1202/** Enable E1000 interupts
1203 *
1204 * @param e1000 E1000 data structure
1205 *
1206 */
1207static void e1000_enable_interrupts(e1000_t *e1000)
1208{
1209 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1210}
1211
1212/** Disable E1000 interupts
1213 *
1214 * @param e1000 E1000 data structure
1215 *
1216 */
1217static void e1000_disable_interrupts(e1000_t *e1000)
1218{
1219 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1220}
1221
1222/** Interrupt handler implementation
1223 *
1224 * This function is called from e1000_interrupt_handler()
1225 * and e1000_poll()
1226 *
1227 * @param nic NIC data
1228 * @param icr ICR register value
1229 *
1230 */
1231static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1232{
1233 if (icr & ICR_RXT0)
1234 e1000_receive_frames(nic);
1235}
1236
1237/** Handle device interrupt
1238 *
1239 * @param icall IPC call structure
1240 * @param dev E1000 device
1241 *
1242 */
1243static void e1000_interrupt_handler(ipc_call_t *icall,
1244 ddf_dev_t *dev)
1245{
1246 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1247 nic_t *nic = NIC_DATA_DEV(dev);
1248 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1249
1250 e1000_interrupt_handler_impl(nic, icr);
1251 e1000_enable_interrupts(e1000);
1252}
1253
1254/** Register interrupt handler for the card in the system
1255 *
1256 * Note: The global irq_reg_mutex is locked because of work with global
1257 * structure.
1258 *
1259 * @param nic Driver data
1260 *
1261 * @param[out] handle IRQ capability handle if the handler was registered
1262 *
1263 * @return An error code otherwise
1264 *
1265 */
1266inline static errno_t e1000_register_int_handler(nic_t *nic,
1267 cap_irq_handle_t *handle)
1268{
1269 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1270
1271 /* Lock the mutex in whole driver while working with global structure */
1272 fibril_mutex_lock(&irq_reg_mutex);
1273
1274 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1275 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1276 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1277
1278 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1279 e1000_interrupt_handler, &e1000_irq_code, handle);
1280
1281 fibril_mutex_unlock(&irq_reg_mutex);
1282 return rc;
1283}
1284
1285/** Force receiving all frames in the receive buffer
1286 *
1287 * @param nic NIC data
1288 *
1289 */
1290static void e1000_poll(nic_t *nic)
1291{
1292 assert(nic);
1293
1294 e1000_t *e1000 = nic_get_specific(nic);
1295 assert(e1000);
1296
1297 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1298 e1000_interrupt_handler_impl(nic, icr);
1299}
1300
1301/** Calculates ITR register interrupt from timeval structure
1302 *
1303 * @param period Period
1304 *
1305 */
1306static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1307{
1308 // TODO: use also tv_sec
1309 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1310}
1311
1312/** Set polling mode
1313 *
1314 * @param device Device to set
1315 * @param mode Mode to set
1316 * @param period Period for NIC_POLL_PERIODIC
1317 *
1318 * @return EOK if succeed
1319 * @return ENOTSUP if the mode is not supported
1320 *
1321 */
1322static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1323 const struct timeval *period)
1324{
1325 assert(nic);
1326
1327 e1000_t *e1000 = nic_get_specific(nic);
1328 assert(e1000);
1329
1330 switch (mode) {
1331 case NIC_POLL_IMMEDIATE:
1332 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1333 e1000_enable_interrupts(e1000);
1334 break;
1335 case NIC_POLL_ON_DEMAND:
1336 e1000_disable_interrupts(e1000);
1337 break;
1338 case NIC_POLL_PERIODIC:
1339 assert(period);
1340 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1341 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1342 e1000_enable_interrupts(e1000);
1343 break;
1344 default:
1345 return ENOTSUP;
1346 }
1347
1348 return EOK;
1349}
1350
1351/** Initialize receive registers
1352 *
1353 * @param e1000 E1000 data structure
1354 *
1355 */
1356static void e1000_initialize_rx_registers(e1000_t *e1000)
1357{
1358 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1359 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1360
1361 /* It is not posible to let HW use all descriptors */
1362 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1363
1364 /* Set Broadcast Enable Bit */
1365 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1366}
1367
1368/** Initialize receive structure
1369 *
1370 * @param nic NIC data
1371 *
1372 * @return EOK if succeed
1373 * @return An error code otherwise
1374 *
1375 */
1376static errno_t e1000_initialize_rx_structure(nic_t *nic)
1377{
1378 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1379 fibril_mutex_lock(&e1000->rx_lock);
1380
1381 e1000->rx_ring_virt = AS_AREA_ANY;
1382 errno_t rc = dmamem_map_anonymous(
1383 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1384 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1385 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1386 if (rc != EOK)
1387 return rc;
1388
1389 E1000_REG_WRITE(e1000, E1000_RDBAH,
1390 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1391 E1000_REG_WRITE(e1000, E1000_RDBAL,
1392 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1393
1394 e1000->rx_frame_phys = (uintptr_t *)
1395 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1396 e1000->rx_frame_virt =
1397 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1398 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1399 rc = ENOMEM;
1400 goto error;
1401 }
1402
1403 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1404 uintptr_t frame_phys;
1405 void *frame_virt = AS_AREA_ANY;
1406
1407 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1408 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1409 &frame_phys, &frame_virt);
1410 if (rc != EOK)
1411 goto error;
1412
1413 e1000->rx_frame_phys[i] = frame_phys;
1414 e1000->rx_frame_virt[i] = frame_virt;
1415 }
1416
1417 /* Write descriptor */
1418 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1419 e1000_fill_new_rx_descriptor(nic, i);
1420
1421 e1000_initialize_rx_registers(e1000);
1422
1423 fibril_mutex_unlock(&e1000->rx_lock);
1424 return EOK;
1425
1426error:
1427 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1428 if (e1000->rx_frame_virt[i] != NULL) {
1429 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1430 e1000->rx_frame_phys[i] = 0;
1431 e1000->rx_frame_virt[i] = NULL;
1432 }
1433 }
1434
1435 if (e1000->rx_frame_phys != NULL) {
1436 free(e1000->rx_frame_phys);
1437 e1000->rx_frame_phys = NULL;
1438 }
1439
1440 if (e1000->rx_frame_virt != NULL) {
1441 free(e1000->rx_frame_virt);
1442 e1000->rx_frame_virt = NULL;
1443 }
1444
1445 return rc;
1446}
1447
1448/** Uninitialize receive structure
1449 *
1450 * @param nic NIC data
1451 *
1452 */
1453static void e1000_uninitialize_rx_structure(nic_t *nic)
1454{
1455 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1456
1457 /* Write descriptor */
1458 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1459 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1460 e1000->rx_frame_phys[offset] = 0;
1461 e1000->rx_frame_virt[offset] = NULL;
1462 }
1463
1464 free(e1000->rx_frame_virt);
1465
1466 e1000->rx_frame_phys = NULL;
1467 e1000->rx_frame_virt = NULL;
1468
1469 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1470}
1471
1472/** Clear receive descriptor ring
1473 *
1474 * @param e1000 E1000 data
1475 *
1476 */
1477static void e1000_clear_rx_ring(e1000_t *e1000)
1478{
1479 /* Write descriptor */
1480 for (unsigned int offset = 0;
1481 offset < E1000_RX_FRAME_COUNT;
1482 offset++)
1483 e1000_clear_rx_descriptor(e1000, offset);
1484}
1485
1486/** Initialize filters
1487 *
1488 * @param e1000 E1000 data
1489 *
1490 */
1491static void e1000_initialize_filters(e1000_t *e1000)
1492{
1493 /* Initialize address filter */
1494 e1000->unicast_ra_count = 0;
1495 e1000->multicast_ra_count = 0;
1496 e1000_clear_unicast_receive_addresses(e1000);
1497}
1498
1499/** Initialize VLAN
1500 *
1501 * @param e1000 E1000 data
1502 *
1503 */
1504static void e1000_initialize_vlan(e1000_t *e1000)
1505{
1506 e1000->vlan_tag_add = false;
1507}
1508
1509/** Fill MAC address from EEPROM to RA[0] register
1510 *
1511 * @param e1000 E1000 data
1512 *
1513 */
1514static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1515{
1516 /* MAC address from eeprom to RA[0] */
1517 nic_address_t address;
1518 e1000_eeprom_get_address(e1000, &address);
1519 e1000_write_receive_address(e1000, 0, &address, true);
1520}
1521
1522/** Initialize other registers
1523 *
1524 * @param dev E1000 data.
1525 *
1526 * @return EOK if succeed
1527 * @return An error code otherwise
1528 *
1529 */
1530static void e1000_initialize_registers(e1000_t *e1000)
1531{
1532 E1000_REG_WRITE(e1000, E1000_ITR,
1533 e1000_calculate_itr_interval_from_usecs(
1534 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1535 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1536 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1537 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1538 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1539 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1540 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1541}
1542
1543/** Initialize transmit registers
1544 *
1545 * @param e1000 E1000 data.
1546 *
1547 */
1548static void e1000_initialize_tx_registers(e1000_t *e1000)
1549{
1550 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1551 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1552 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1553
1554 E1000_REG_WRITE(e1000, E1000_TIPG,
1555 10 << TIPG_IPGT_SHIFT |
1556 8 << TIPG_IPGR1_SHIFT |
1557 6 << TIPG_IPGR2_SHIFT);
1558
1559 E1000_REG_WRITE(e1000, E1000_TCTL,
1560 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1561 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1562 TCTL_PSP /* Pad Short Packets */);
1563}
1564
1565/** Initialize transmit structure
1566 *
1567 * @param e1000 E1000 data.
1568 *
1569 */
1570static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1571{
1572 size_t i;
1573
1574 fibril_mutex_lock(&e1000->tx_lock);
1575
1576 e1000->tx_ring_phys = 0;
1577 e1000->tx_ring_virt = AS_AREA_ANY;
1578
1579 e1000->tx_frame_phys = NULL;
1580 e1000->tx_frame_virt = NULL;
1581
1582 errno_t rc = dmamem_map_anonymous(
1583 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1584 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1585 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1586 if (rc != EOK)
1587 goto error;
1588
1589 memset(e1000->tx_ring_virt, 0,
1590 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1591
1592 e1000->tx_frame_phys = (uintptr_t *)
1593 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1594 e1000->tx_frame_virt =
1595 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1596
1597 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1598 rc = ENOMEM;
1599 goto error;
1600 }
1601
1602 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1603 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1604 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1605 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1606 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1607 if (rc != EOK)
1608 goto error;
1609 }
1610
1611 E1000_REG_WRITE(e1000, E1000_TDBAH,
1612 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1613 E1000_REG_WRITE(e1000, E1000_TDBAL,
1614 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1615
1616 e1000_initialize_tx_registers(e1000);
1617
1618 fibril_mutex_unlock(&e1000->tx_lock);
1619 return EOK;
1620
1621error:
1622 if (e1000->tx_ring_virt != NULL) {
1623 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1624 e1000->tx_ring_virt = NULL;
1625 }
1626
1627 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1628 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1629 if (e1000->tx_frame_virt[i] != NULL) {
1630 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1631 e1000->tx_frame_phys[i] = 0;
1632 e1000->tx_frame_virt[i] = NULL;
1633 }
1634 }
1635 }
1636
1637 if (e1000->tx_frame_phys != NULL) {
1638 free(e1000->tx_frame_phys);
1639 e1000->tx_frame_phys = NULL;
1640 }
1641
1642 if (e1000->tx_frame_virt != NULL) {
1643 free(e1000->tx_frame_virt);
1644 e1000->tx_frame_virt = NULL;
1645 }
1646
1647 return rc;
1648}
1649
1650/** Uninitialize transmit structure
1651 *
1652 * @param nic NIC data
1653 *
1654 */
1655static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1656{
1657 size_t i;
1658
1659 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1660 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1661 e1000->tx_frame_phys[i] = 0;
1662 e1000->tx_frame_virt[i] = NULL;
1663 }
1664
1665 if (e1000->tx_frame_phys != NULL) {
1666 free(e1000->tx_frame_phys);
1667 e1000->tx_frame_phys = NULL;
1668 }
1669
1670 if (e1000->tx_frame_virt != NULL) {
1671 free(e1000->tx_frame_virt);
1672 e1000->tx_frame_virt = NULL;
1673 }
1674
1675 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1676}
1677
1678/** Clear transmit descriptor ring
1679 *
1680 * @param nic NIC data
1681 *
1682 */
1683static void e1000_clear_tx_ring(nic_t *nic)
1684{
1685 /* Write descriptor */
1686 for (unsigned int offset = 0;
1687 offset < E1000_TX_FRAME_COUNT;
1688 offset++)
1689 e1000_clear_tx_descriptor(nic, offset);
1690}
1691
1692/** Enable transmit
1693 *
1694 * @param e1000 E1000 data
1695 *
1696 */
1697static void e1000_enable_tx(e1000_t *e1000)
1698{
1699 /* Set Transmit Enable Bit */
1700 E1000_REG_WRITE(e1000, E1000_TCTL,
1701 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1702}
1703
1704/** Disable transmit
1705 *
1706 * @param e1000 E1000 data
1707 *
1708 */
1709static void e1000_disable_tx(e1000_t *e1000)
1710{
1711 /* Clear Transmit Enable Bit */
1712 E1000_REG_WRITE(e1000, E1000_TCTL,
1713 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1714}
1715
1716/** Reset E1000 device
1717 *
1718 * @param e1000 The E1000 data
1719 *
1720 */
1721static errno_t e1000_reset(nic_t *nic)
1722{
1723 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1724
1725 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1726
1727 /* Wait for the reset */
1728 async_usleep(20);
1729
1730 /* check if RST_BIT cleared */
1731 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1732 return EINVAL;
1733
1734 e1000_initialize_registers(e1000);
1735 e1000_initialize_rx_registers(e1000);
1736 e1000_initialize_tx_registers(e1000);
1737 e1000_fill_mac_from_eeprom(e1000);
1738 e1000_initialize_filters(e1000);
1739 e1000_initialize_vlan(e1000);
1740
1741 return EOK;
1742}
1743
1744/** Activate the device to receive and transmit frames
1745 *
1746 * @param nic NIC driver data
1747 *
1748 * @return EOK if activated successfully
1749 * @return Error code otherwise
1750 *
1751 */
1752static errno_t e1000_on_activating(nic_t *nic)
1753{
1754 assert(nic);
1755
1756 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1757
1758 fibril_mutex_lock(&e1000->rx_lock);
1759 fibril_mutex_lock(&e1000->tx_lock);
1760 fibril_mutex_lock(&e1000->ctrl_lock);
1761
1762 e1000_enable_interrupts(e1000);
1763
1764 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1765 if (rc != EOK) {
1766 e1000_disable_interrupts(e1000);
1767 fibril_mutex_unlock(&e1000->ctrl_lock);
1768 fibril_mutex_unlock(&e1000->tx_lock);
1769 fibril_mutex_unlock(&e1000->rx_lock);
1770 return rc;
1771 }
1772
1773 e1000_clear_rx_ring(e1000);
1774 e1000_enable_rx(e1000);
1775
1776 e1000_clear_tx_ring(nic);
1777 e1000_enable_tx(e1000);
1778
1779 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1780 ctrl |= CTRL_SLU;
1781 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1782
1783 fibril_mutex_unlock(&e1000->ctrl_lock);
1784 fibril_mutex_unlock(&e1000->tx_lock);
1785 fibril_mutex_unlock(&e1000->rx_lock);
1786
1787 return EOK;
1788}
1789
1790/** Callback for NIC_STATE_DOWN change
1791 *
1792 * @param nic NIC driver data
1793 *
1794 * @return EOK if succeed
1795 * @return Error code otherwise
1796 *
1797 */
1798static errno_t e1000_on_down_unlocked(nic_t *nic)
1799{
1800 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1801
1802 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1803 ctrl &= ~CTRL_SLU;
1804 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1805
1806 e1000_disable_tx(e1000);
1807 e1000_disable_rx(e1000);
1808
1809 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1810 e1000_disable_interrupts(e1000);
1811
1812 /*
1813 * Wait for the for the end of all data
1814 * transfers to descriptors.
1815 */
1816 async_usleep(100);
1817
1818 return EOK;
1819}
1820
1821/** Callback for NIC_STATE_DOWN change
1822 *
1823 * @param nic NIC driver data
1824 *
1825 * @return EOK if succeed
1826 * @return Error code otherwise
1827 *
1828 */
1829static errno_t e1000_on_down(nic_t *nic)
1830{
1831 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1832
1833 fibril_mutex_lock(&e1000->rx_lock);
1834 fibril_mutex_lock(&e1000->tx_lock);
1835 fibril_mutex_lock(&e1000->ctrl_lock);
1836
1837 errno_t rc = e1000_on_down_unlocked(nic);
1838
1839 fibril_mutex_unlock(&e1000->ctrl_lock);
1840 fibril_mutex_unlock(&e1000->tx_lock);
1841 fibril_mutex_unlock(&e1000->rx_lock);
1842
1843 return rc;
1844}
1845
1846/** Callback for NIC_STATE_STOPPED change
1847 *
1848 * @param nic NIC driver data
1849 *
1850 * @return EOK if succeed
1851 * @return Error code otherwise
1852 *
1853 */
1854static errno_t e1000_on_stopping(nic_t *nic)
1855{
1856 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1857
1858 fibril_mutex_lock(&e1000->rx_lock);
1859 fibril_mutex_lock(&e1000->tx_lock);
1860 fibril_mutex_lock(&e1000->ctrl_lock);
1861
1862 errno_t rc = e1000_on_down_unlocked(nic);
1863 if (rc == EOK)
1864 rc = e1000_reset(nic);
1865
1866 fibril_mutex_unlock(&e1000->ctrl_lock);
1867 fibril_mutex_unlock(&e1000->tx_lock);
1868 fibril_mutex_unlock(&e1000->rx_lock);
1869
1870 return rc;
1871}
1872
1873/** Create driver data structure
1874 *
1875 * @return Intialized device data structure or NULL
1876 *
1877 */
1878static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1879{
1880 nic_t *nic = nic_create_and_bind(dev);
1881 if (!nic)
1882 return NULL;
1883
1884 e1000_t *e1000 = malloc(sizeof(e1000_t));
1885 if (!e1000) {
1886 nic_unbind_and_destroy(dev);
1887 return NULL;
1888 }
1889
1890 memset(e1000, 0, sizeof(e1000_t));
1891 e1000->dev = dev;
1892
1893 nic_set_specific(nic, e1000);
1894 nic_set_send_frame_handler(nic, e1000_send_frame);
1895 nic_set_state_change_handlers(nic, e1000_on_activating,
1896 e1000_on_down, e1000_on_stopping);
1897 nic_set_filtering_change_handlers(nic,
1898 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1899 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1900 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1901
1902 fibril_mutex_initialize(&e1000->ctrl_lock);
1903 fibril_mutex_initialize(&e1000->rx_lock);
1904 fibril_mutex_initialize(&e1000->tx_lock);
1905 fibril_mutex_initialize(&e1000->eeprom_lock);
1906
1907 return e1000;
1908}
1909
1910/** Delete driver data structure
1911 *
1912 * @param data E1000 device data structure
1913 *
1914 */
1915inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1916{
1917 assert(dev);
1918
1919 if (ddf_dev_data_get(dev) != NULL)
1920 nic_unbind_and_destroy(dev);
1921}
1922
1923/** Clean up the E1000 device structure.
1924 *
1925 * @param dev Device structure.
1926 *
1927 */
1928static void e1000_dev_cleanup(ddf_dev_t *dev)
1929{
1930 assert(dev);
1931
1932 e1000_delete_dev_data(dev);
1933}
1934
1935/** Fill the irq and io_addr part of device data structure
1936 *
1937 * The hw_resources must be obtained before calling this function
1938 *
1939 * @param dev Device structure
1940 * @param hw_resources Hardware resources obtained from the parent device
1941 *
1942 * @return EOK if succeed
1943 * @return An error code otherwise
1944 *
1945 */
1946static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1947 const hw_res_list_parsed_t *hw_resources)
1948{
1949 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1950
1951 if (hw_resources->irqs.count != 1)
1952 return EINVAL;
1953
1954 e1000->irq = hw_resources->irqs.irqs[0];
1955 e1000->reg_base_phys =
1956 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1957
1958 return EOK;
1959}
1960
1961/** Obtain information about hardware resources of the device
1962 *
1963 * The device must be connected to the parent
1964 *
1965 * @param dev Device structure
1966 *
1967 * @return EOK if succeed
1968 * @return An error code otherwise
1969 *
1970 */
1971static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1972{
1973 assert(dev != NULL);
1974 assert(NIC_DATA_DEV(dev) != NULL);
1975
1976 hw_res_list_parsed_t hw_res_parsed;
1977 hw_res_list_parsed_init(&hw_res_parsed);
1978
1979 /* Get hw resources form parent driver */
1980 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1981 if (rc != EOK)
1982 return rc;
1983
1984 /* Fill resources information to the device */
1985 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1986 hw_res_list_parsed_clean(&hw_res_parsed);
1987
1988 return rc;
1989}
1990
1991/** Initialize the E1000 device structure
1992 *
1993 * @param dev Device information
1994 *
1995 * @return EOK if succeed
1996 * @return An error code otherwise
1997 *
1998 */
1999static errno_t e1000_device_initialize(ddf_dev_t *dev)
2000{
2001 /* Allocate driver data for the device. */
2002 e1000_t *e1000 = e1000_create_dev_data(dev);
2003 if (e1000 == NULL) {
2004 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2005 return ENOMEM;
2006 }
2007
2008 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2009 if (e1000->parent_sess == NULL) {
2010 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2011 return EIO;
2012 }
2013
2014 /* Obtain and fill hardware resources info */
2015 errno_t rc = e1000_get_resource_info(dev);
2016 if (rc != EOK) {
2017 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2018 e1000_dev_cleanup(dev);
2019 return rc;
2020 }
2021
2022 uint16_t device_id;
2023 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2024 &device_id);
2025 if (rc != EOK) {
2026 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2027 e1000_dev_cleanup(dev);
2028 return rc;
2029 }
2030
2031 e1000_board_t board;
2032 switch (device_id) {
2033 case 0x100e:
2034 case 0x1015:
2035 case 0x1016:
2036 case 0x1017:
2037 board = E1000_82540;
2038 break;
2039 case 0x1013:
2040 case 0x1018:
2041 case 0x1078:
2042 board = E1000_82541;
2043 break;
2044 case 0x1076:
2045 case 0x1077:
2046 case 0x107c:
2047 board = E1000_82541REV2;
2048 break;
2049 case 0x100f:
2050 case 0x1011:
2051 case 0x1026:
2052 case 0x1027:
2053 case 0x1028:
2054 board = E1000_82545;
2055 break;
2056 case 0x1010:
2057 case 0x1012:
2058 case 0x101d:
2059 case 0x1079:
2060 case 0x107a:
2061 case 0x107b:
2062 board = E1000_82546;
2063 break;
2064 case 0x1019:
2065 case 0x101a:
2066 board = E1000_82547;
2067 break;
2068 case 0x10b9:
2069 board = E1000_82572;
2070 break;
2071 case 0x1096:
2072 board = E1000_80003ES2;
2073 break;
2074 default:
2075 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2076 device_id);
2077 e1000_dev_cleanup(dev);
2078 return ENOTSUP;
2079 }
2080
2081 switch (board) {
2082 case E1000_82540:
2083 case E1000_82541:
2084 case E1000_82541REV2:
2085 case E1000_82545:
2086 case E1000_82546:
2087 e1000->info.eerd_start = 0x01;
2088 e1000->info.eerd_done = 0x10;
2089 e1000->info.eerd_address_offset = 8;
2090 e1000->info.eerd_data_offset = 16;
2091 break;
2092 case E1000_82547:
2093 case E1000_82572:
2094 case E1000_80003ES2:
2095 e1000->info.eerd_start = 0x01;
2096 e1000->info.eerd_done = 0x02;
2097 e1000->info.eerd_address_offset = 2;
2098 e1000->info.eerd_data_offset = 16;
2099 break;
2100 }
2101
2102 return EOK;
2103}
2104
2105/** Enable the I/O ports of the device.
2106 *
2107 * @param dev E1000 device.
2108 *
2109 * @return EOK if successed
2110 * @return An error code otherwise
2111 *
2112 */
2113static errno_t e1000_pio_enable(ddf_dev_t *dev)
2114{
2115 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2116
2117 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2118 &e1000->reg_base_virt);
2119 if (rc != EOK)
2120 return EADDRNOTAVAIL;
2121
2122 return EOK;
2123}
2124
2125/** Probe and initialize the newly added device.
2126 *
2127 * @param dev E1000 device.
2128 *
2129 */
2130errno_t e1000_dev_add(ddf_dev_t *dev)
2131{
2132 ddf_fun_t *fun;
2133
2134 /* Initialize device structure for E1000 */
2135 errno_t rc = e1000_device_initialize(dev);
2136 if (rc != EOK)
2137 return rc;
2138
2139 /* Device initialization */
2140 nic_t *nic = ddf_dev_data_get(dev);
2141 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2142
2143 /* Map registers */
2144 rc = e1000_pio_enable(dev);
2145 if (rc != EOK)
2146 goto err_destroy;
2147
2148 e1000_initialize_registers(e1000);
2149 rc = e1000_initialize_tx_structure(e1000);
2150 if (rc != EOK)
2151 goto err_pio;
2152
2153 fibril_mutex_lock(&e1000->rx_lock);
2154
2155 e1000_fill_mac_from_eeprom(e1000);
2156 e1000_initialize_filters(e1000);
2157
2158 fibril_mutex_unlock(&e1000->rx_lock);
2159
2160 e1000_initialize_vlan(e1000);
2161
2162 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2163 if (fun == NULL)
2164 goto err_tx_structure;
2165 nic_set_ddf_fun(nic, fun);
2166 ddf_fun_set_ops(fun, &e1000_dev_ops);
2167
2168 cap_irq_handle_t irq_handle;
2169 rc = e1000_register_int_handler(nic, &irq_handle);
2170 if (rc != EOK) {
2171 goto err_fun_create;
2172 }
2173
2174 rc = e1000_initialize_rx_structure(nic);
2175 if (rc != EOK)
2176 goto err_irq;
2177
2178 nic_address_t e1000_address;
2179 e1000_get_address(e1000, &e1000_address);
2180 rc = nic_report_address(nic, &e1000_address);
2181 if (rc != EOK)
2182 goto err_rx_structure;
2183
2184 struct timeval period;
2185 period.tv_sec = 0;
2186 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2187 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2188 if (rc != EOK)
2189 goto err_rx_structure;
2190
2191 rc = ddf_fun_bind(fun);
2192 if (rc != EOK)
2193 goto err_fun_bind;
2194
2195 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2196 if (rc != EOK)
2197 goto err_add_to_cat;
2198
2199 return EOK;
2200
2201err_add_to_cat:
2202 ddf_fun_unbind(fun);
2203err_fun_bind:
2204err_rx_structure:
2205 e1000_uninitialize_rx_structure(nic);
2206err_irq:
2207 unregister_interrupt_handler(dev, irq_handle);
2208err_fun_create:
2209 ddf_fun_destroy(fun);
2210 nic_set_ddf_fun(nic, NULL);
2211err_tx_structure:
2212 e1000_uninitialize_tx_structure(e1000);
2213err_pio:
2214 // TODO: e1000_pio_disable(dev);
2215err_destroy:
2216 e1000_dev_cleanup(dev);
2217 return rc;
2218}
2219
2220/** Read 16-bit value from EEPROM of E1000 adapter
2221 *
2222 * Read using the EERD register.
2223 *
2224 * @param device E1000 device
2225 * @param eeprom_address 8-bit EEPROM address
2226 *
2227 * @return 16-bit value from EEPROM
2228 *
2229 */
2230static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2231{
2232 fibril_mutex_lock(&e1000->eeprom_lock);
2233
2234 /* Write address and START bit to EERD register */
2235 uint32_t write_data = e1000->info.eerd_start |
2236 (((uint32_t) eeprom_address) <<
2237 e1000->info.eerd_address_offset);
2238 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2239
2240 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2241 while ((eerd & e1000->info.eerd_done) == 0) {
2242 async_usleep(1);
2243 eerd = E1000_REG_READ(e1000, E1000_EERD);
2244 }
2245
2246 fibril_mutex_unlock(&e1000->eeprom_lock);
2247
2248 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2249}
2250
2251/** Get MAC address of the E1000 adapter
2252 *
2253 * @param device E1000 device
2254 * @param address Place to store the address
2255 * @param max_len Maximal addresss length to store
2256 *
2257 * @return EOK if succeed
2258 * @return An error code otherwise
2259 *
2260 */
2261static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2262{
2263 fibril_mutex_lock(&e1000->rx_lock);
2264
2265 uint8_t *mac0_dest = (uint8_t *) address->address;
2266 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2267 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2268 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2269 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2270 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2271
2272 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2273 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2274
2275 *mac0_dest = (uint8_t) ral;
2276 *mac1_dest = (uint8_t) (ral >> 8);
2277 *mac2_dest = (uint8_t) (ral >> 16);
2278 *mac3_dest = (uint8_t) (ral >> 24);
2279 *mac4_dest = (uint8_t) rah;
2280 *mac5_dest = (uint8_t) (rah >> 8);
2281
2282 fibril_mutex_unlock(&e1000->rx_lock);
2283 return EOK;
2284}
2285
2286/** Set card MAC address
2287 *
2288 * @param device E1000 device
2289 * @param address Address
2290 *
2291 * @return EOK if succeed
2292 * @return An error code otherwise
2293 */
2294static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2295{
2296 nic_t *nic = NIC_DATA_FUN(fun);
2297 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2298
2299 fibril_mutex_lock(&e1000->rx_lock);
2300 fibril_mutex_lock(&e1000->tx_lock);
2301
2302 errno_t rc = nic_report_address(nic, addr);
2303 if (rc == EOK)
2304 e1000_write_receive_address(e1000, 0, addr, false);
2305
2306 fibril_mutex_unlock(&e1000->tx_lock);
2307 fibril_mutex_unlock(&e1000->rx_lock);
2308
2309 return rc;
2310}
2311
2312static void e1000_eeprom_get_address(e1000_t *e1000,
2313 nic_address_t *address)
2314{
2315 uint16_t *mac0_dest = (uint16_t *) address->address;
2316 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2317 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2318
2319 *mac0_dest = e1000_eeprom_read(e1000, 0);
2320 *mac2_dest = e1000_eeprom_read(e1000, 1);
2321 *mac4_dest = e1000_eeprom_read(e1000, 2);
2322}
2323
2324/** Send frame
2325 *
2326 * @param nic NIC driver data structure
2327 * @param data Frame data
2328 * @param size Frame size in bytes
2329 *
2330 * @return EOK if succeed
2331 * @return Error code in the case of error
2332 *
2333 */
2334static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2335{
2336 assert(nic);
2337
2338 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2339 fibril_mutex_lock(&e1000->tx_lock);
2340
2341 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2342 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2343 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2344
2345 bool descriptor_available = false;
2346
2347 /* Descriptor never used */
2348 if (tx_descriptor_addr->length == 0)
2349 descriptor_available = true;
2350
2351 /* Descriptor done */
2352 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2353 descriptor_available = true;
2354
2355 if (!descriptor_available) {
2356 /* Frame lost */
2357 fibril_mutex_unlock(&e1000->tx_lock);
2358 return;
2359 }
2360
2361 memcpy(e1000->tx_frame_virt[tdt], data, size);
2362
2363 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2364 tx_descriptor_addr->length = size;
2365
2366 /*
2367 * Report status to STATUS.DD (descriptor done),
2368 * add ethernet CRC, end of packet.
2369 */
2370 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2371 TXDESCRIPTOR_COMMAND_IFCS |
2372 TXDESCRIPTOR_COMMAND_EOP;
2373
2374 tx_descriptor_addr->checksum_offset = 0;
2375 tx_descriptor_addr->status = 0;
2376 if (e1000->vlan_tag_add) {
2377 tx_descriptor_addr->special = e1000->vlan_tag;
2378 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2379 } else
2380 tx_descriptor_addr->special = 0;
2381
2382 tx_descriptor_addr->checksum_start_field = 0;
2383
2384 tdt++;
2385 if (tdt == E1000_TX_FRAME_COUNT)
2386 tdt = 0;
2387
2388 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2389
2390 fibril_mutex_unlock(&e1000->tx_lock);
2391}
2392
2393int main(void)
2394{
2395 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2396
2397 if (nic_driver_init(NAME) != EOK)
2398 return 1;
2399
2400 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2401 &e1000_nic_iface);
2402
2403 ddf_log_init(NAME);
2404 return ddf_driver_main(&e1000_driver);
2405}
Note: See TracBrowser for help on using the repository browser.