source: mainline/uspace/drv/nic/e1k/e1k.c

Last change on this file was 870841cf, checked in by Jiri Svoboda <jiri@…>, 5 months ago

Style issues related to improper use of 'inline' keyword.
  • Property mode set to 100644
File size: 56.8 KB
Line 
1/*
2 * Copyright (c) 2025 Jiri Svoboda
3 * Copyright (c) 2011 Zdenek Bouska
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @file e1k.c
31 *
32 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
33 *
34 */
35
36#include <async.h>
37#include <assert.h>
38#include <stdio.h>
39#include <errno.h>
40#include <adt/list.h>
41#include <align.h>
42#include <byteorder.h>
43#include <as.h>
44#include <ddi.h>
45#include <ddf/log.h>
46#include <ddf/interrupt.h>
47#include <device/hw_res.h>
48#include <device/hw_res_parsed.h>
49#include <pci_dev_iface.h>
50#include <nic.h>
51#include <ops/nic.h>
52#include "e1k.h"
53
54#define NAME "e1k"
55
56#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
57
58/* Must be power of 8 */
59#define E1000_RX_FRAME_COUNT 128
60#define E1000_TX_FRAME_COUNT 128
61
62#define E1000_RECEIVE_ADDRESS 16
63
64/** Maximum sending frame size */
65#define E1000_MAX_SEND_FRAME_SIZE 2048
66/** Maximum receiving frame size */
67#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
68
69/** nic_driver_data_t* -> e1000_t* cast */
70#define DRIVER_DATA_NIC(nic) \
71 ((e1000_t *) nic_get_specific(nic))
72
73/** ddf_fun_t * -> nic_driver_data_t* cast */
74#define NIC_DATA_FUN(fun) \
75 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
76
77/** ddf_dev_t * -> nic_driver_data_t* cast */
78#define NIC_DATA_DEV(dev) \
79 ((nic_t *) ddf_dev_data_get(dev))
80
81/** ddf_dev_t * -> e1000_t* cast */
82#define DRIVER_DATA_DEV(dev) \
83 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
84
85/** ddf_fun_t * -> e1000_t* cast */
86#define DRIVER_DATA_FUN(fun) \
87 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
88
89/** Cast pointer to uint64_t
90 *
91 * @param ptr Pointer to cast
92 *
93 * @return The uint64_t pointer representation.
94 *
95 */
96#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
97
98/** Cast the memaddr part to the void*
99 *
100 * @param memaddr The memaddr value
101 *
102 */
103#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
104
105#define E1000_REG_BASE(e1000) \
106 ((e1000)->reg_base_virt)
107
108#define E1000_REG_ADDR(e1000, reg) \
109 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
110
111#define E1000_REG_READ(e1000, reg) \
112 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
113
114#define E1000_REG_WRITE(e1000, reg, value) \
115 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
116
117/** E1000 device data */
118typedef struct {
119 /** DDF device */
120 ddf_dev_t *dev;
121 /** Parent session */
122 async_sess_t *parent_sess;
123 /** Device configuration */
124 e1000_info_t info;
125
126 /** Physical registers base address */
127 void *reg_base_phys;
128 /** Virtual registers base address */
129 void *reg_base_virt;
130
131 /** Physical tx ring address */
132 uintptr_t tx_ring_phys;
133 /** Virtual tx ring address */
134 void *tx_ring_virt;
135
136 /** Ring of TX frames, physical address */
137 uintptr_t *tx_frame_phys;
138 /** Ring of TX frames, virtual address */
139 void **tx_frame_virt;
140
141 /** Physical rx ring address */
142 uintptr_t rx_ring_phys;
143 /** Virtual rx ring address */
144 void *rx_ring_virt;
145
146 /** Ring of RX frames, physical address */
147 uintptr_t *rx_frame_phys;
148 /** Ring of RX frames, virtual address */
149 void **rx_frame_virt;
150
151 /** VLAN tag */
152 uint16_t vlan_tag;
153
154 /** Add VLAN tag to frame */
155 bool vlan_tag_add;
156
157 /** Used unicast Receive Address count */
158 unsigned int unicast_ra_count;
159
160 /** Used milticast Receive addrress count */
161 unsigned int multicast_ra_count;
162
163 /** The irq assigned */
164 int irq;
165
166 /** Lock for CTRL register */
167 fibril_mutex_t ctrl_lock;
168
169 /** Lock for receiver */
170 fibril_mutex_t rx_lock;
171
172 /** Lock for transmitter */
173 fibril_mutex_t tx_lock;
174
175 /** Lock for EEPROM access */
176 fibril_mutex_t eeprom_lock;
177} e1000_t;
178
179/** Global mutex for work with shared irq structure */
180FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
181
182static errno_t e1000_get_address(e1000_t *, nic_address_t *);
183static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
184static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
185
186static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
187static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
188
189static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
190static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
191static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
192 nic_channel_mode_t *, nic_role_t *);
193static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
194 nic_channel_mode_t, nic_role_t);
195static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
196static errno_t e1000_autoneg_disable(ddf_fun_t *);
197static errno_t e1000_autoneg_restart(ddf_fun_t *);
198
199static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
200
201/** Network interface options for E1000 card driver */
202static nic_iface_t e1000_nic_iface;
203
204/** Network interface options for E1000 card driver */
205static nic_iface_t e1000_nic_iface = {
206 .set_address = &e1000_set_addr,
207 .get_device_info = &e1000_get_device_info,
208 .get_cable_state = &e1000_get_cable_state,
209 .get_operation_mode = &e1000_get_operation_mode,
210 .set_operation_mode = &e1000_set_operation_mode,
211 .autoneg_enable = &e1000_autoneg_enable,
212 .autoneg_disable = &e1000_autoneg_disable,
213 .autoneg_restart = &e1000_autoneg_restart,
214 .vlan_set_tag = &e1000_vlan_set_tag,
215 .defective_get_mode = &e1000_defective_get_mode,
216 .defective_set_mode = &e1000_defective_set_mode,
217};
218
219/** Basic device operations for E1000 driver */
220static ddf_dev_ops_t e1000_dev_ops;
221
222static errno_t e1000_dev_add(ddf_dev_t *);
223static errno_t e1000_dev_quiesce(ddf_dev_t *);
224
225/** Basic driver operations for E1000 driver */
226static driver_ops_t e1000_driver_ops = {
227 .dev_add = e1000_dev_add,
228 .dev_quiesce = e1000_dev_quiesce
229};
230
231/** Driver structure for E1000 driver */
232static driver_t e1000_driver = {
233 .name = NAME,
234 .driver_ops = &e1000_driver_ops
235};
236
237/* The default implementation callbacks */
238static errno_t e1000_on_activating(nic_t *);
239static errno_t e1000_on_stopping(nic_t *);
240static void e1000_send_frame(nic_t *, void *, size_t);
241
242/** PIO ranges used in the IRQ code. */
243irq_pio_range_t e1000_irq_pio_ranges[] = {
244 {
245 .base = 0,
246 .size = PAGE_SIZE, /* XXX */
247 }
248};
249
250/** Commands to deal with interrupt
251 *
252 */
253irq_cmd_t e1000_irq_commands[] = {
254 {
255 /* Get the interrupt status */
256 .cmd = CMD_PIO_READ_32,
257 .addr = NULL,
258 .dstarg = 2
259 },
260 {
261 .cmd = CMD_AND,
262 .value = ICR_RXT0,
263 .srcarg = 2,
264 .dstarg = 1
265 },
266 {
267 .cmd = CMD_PREDICATE,
268 .value = 2,
269 .srcarg = 1
270 },
271 {
272 /* Disable interrupts until interrupt routine is finished */
273 .cmd = CMD_PIO_WRITE_32,
274 .addr = NULL,
275 .value = 0xffffffff
276 },
277 {
278 .cmd = CMD_ACCEPT
279 }
280};
281
282/** Interrupt code definition */
283irq_code_t e1000_irq_code = {
284 .rangecount = sizeof(e1000_irq_pio_ranges) /
285 sizeof(irq_pio_range_t),
286 .ranges = e1000_irq_pio_ranges,
287 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
288 .cmds = e1000_irq_commands
289};
290
291/** Get the device information
292 *
293 * @param dev NIC device
294 * @param info Information to fill
295 *
296 * @return EOK
297 *
298 */
299static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
300{
301 assert(dev);
302 assert(info);
303
304 memset(info, 0, sizeof(nic_device_info_t));
305
306 info->vendor_id = 0x8086;
307 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
308 "Intel Corporation");
309 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
310 "Intel Pro");
311
312 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
313 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
314 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
315
316 return EOK;
317}
318
319/** Check the cable state
320 *
321 * @param[in] dev device
322 * @param[out] state state to fill
323 *
324 * @return EOK
325 *
326 */
327static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
328{
329 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
330 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
331 *state = NIC_CS_PLUGGED;
332 else
333 *state = NIC_CS_UNPLUGGED;
334
335 return EOK;
336}
337
338static uint16_t e1000_calculate_itr_interval_from_usecs(usec_t useconds)
339{
340 return useconds * 4;
341}
342
343/** Get operation mode of the device
344 *
345 */
346static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
347 nic_channel_mode_t *duplex, nic_role_t *role)
348{
349 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
350 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
351
352 if (status & STATUS_FD)
353 *duplex = NIC_CM_FULL_DUPLEX;
354 else
355 *duplex = NIC_CM_HALF_DUPLEX;
356
357 uint32_t speed_bits =
358 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
359
360 if (speed_bits == STATUS_SPEED_10)
361 *speed = 10;
362 else if (speed_bits == STATUS_SPEED_100)
363 *speed = 100;
364 else if ((speed_bits == STATUS_SPEED_1000A) ||
365 (speed_bits == STATUS_SPEED_1000B))
366 *speed = 1000;
367
368 *role = NIC_ROLE_UNKNOWN;
369 return EOK;
370}
371
372static void e1000_link_restart(e1000_t *e1000)
373{
374 fibril_mutex_lock(&e1000->ctrl_lock);
375
376 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
377
378 if (ctrl & CTRL_SLU) {
379 ctrl &= ~(CTRL_SLU);
380 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
381 fibril_mutex_unlock(&e1000->ctrl_lock);
382
383 fibril_usleep(10);
384
385 fibril_mutex_lock(&e1000->ctrl_lock);
386 ctrl = E1000_REG_READ(e1000, E1000_CTRL);
387 ctrl |= CTRL_SLU;
388 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
389 }
390
391 fibril_mutex_unlock(&e1000->ctrl_lock);
392}
393
394/** Set operation mode of the device
395 *
396 */
397static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
398 nic_channel_mode_t duplex, nic_role_t role)
399{
400 if ((speed != 10) && (speed != 100) && (speed != 1000))
401 return EINVAL;
402
403 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
404 return EINVAL;
405
406 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
407
408 fibril_mutex_lock(&e1000->ctrl_lock);
409 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
410
411 ctrl |= CTRL_FRCSPD;
412 ctrl |= CTRL_FRCDPLX;
413 ctrl &= ~(CTRL_ASDE);
414
415 if (duplex == NIC_CM_FULL_DUPLEX)
416 ctrl |= CTRL_FD;
417 else
418 ctrl &= ~(CTRL_FD);
419
420 ctrl &= ~(CTRL_SPEED_MASK);
421 if (speed == 1000)
422 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
423 else if (speed == 100)
424 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
425 else
426 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
427
428 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
429
430 fibril_mutex_unlock(&e1000->ctrl_lock);
431
432 e1000_link_restart(e1000);
433
434 return EOK;
435}
436
437/** Enable auto-negotiation
438 *
439 * @param dev Device to update
440 * @param advertisement Ignored on E1000
441 *
442 * @return EOK if advertisement mode set successfully
443 *
444 */
445static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
446{
447 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
448
449 fibril_mutex_lock(&e1000->ctrl_lock);
450
451 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
452
453 ctrl &= ~(CTRL_FRCSPD);
454 ctrl &= ~(CTRL_FRCDPLX);
455 ctrl |= CTRL_ASDE;
456
457 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
458
459 fibril_mutex_unlock(&e1000->ctrl_lock);
460
461 e1000_link_restart(e1000);
462
463 return EOK;
464}
465
466/** Disable auto-negotiation
467 *
468 * @param dev Device to update
469 *
470 * @return EOK
471 *
472 */
473static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
474{
475 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
476
477 fibril_mutex_lock(&e1000->ctrl_lock);
478
479 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
480
481 ctrl |= CTRL_FRCSPD;
482 ctrl |= CTRL_FRCDPLX;
483 ctrl &= ~(CTRL_ASDE);
484
485 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
486
487 fibril_mutex_unlock(&e1000->ctrl_lock);
488
489 e1000_link_restart(e1000);
490
491 return EOK;
492}
493
494/** Restart auto-negotiation
495 *
496 * @param dev Device to update
497 *
498 * @return EOK if advertisement mode set successfully
499 *
500 */
501static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
502{
503 return e1000_autoneg_enable(dev, 0);
504}
505
506/** Get state of acceptance of weird frames
507 *
508 * @param device Device to check
509 * @param[out] mode Current mode
510 *
511 */
512static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
513{
514 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
515
516 *mode = 0;
517 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
518 if (rctl & RCTL_SBP)
519 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
520
521 return EOK;
522}
523
524/** Set acceptance of weird frames
525 *
526 * @param device Device to update
527 * @param mode Mode to set
528 *
529 * @return ENOTSUP if the mode is not supported
530 * @return EOK of mode was set
531 *
532 */
533static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
534{
535 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
536 errno_t rc = EOK;
537
538 fibril_mutex_lock(&e1000->rx_lock);
539
540 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
541 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
542 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
543
544 if (short_mode && bad_mode)
545 rctl |= RCTL_SBP;
546 else if ((!short_mode) && (!bad_mode))
547 rctl &= ~RCTL_SBP;
548 else
549 rc = ENOTSUP;
550
551 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
552
553 fibril_mutex_unlock(&e1000->rx_lock);
554 return rc;
555}
556
557/** Write receive address to RA registr
558 *
559 * @param e1000 E1000 data structure
560 * @param position RA register position
561 * @param address Ethernet address
562 * @param set_av_bit Set the Addtess Valid bit
563 *
564 */
565static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
566 const nic_address_t *address, bool set_av_bit)
567{
568 uint8_t *mac0 = (uint8_t *) address->address;
569 uint8_t *mac1 = (uint8_t *) address->address + 1;
570 uint8_t *mac2 = (uint8_t *) address->address + 2;
571 uint8_t *mac3 = (uint8_t *) address->address + 3;
572 uint8_t *mac4 = (uint8_t *) address->address + 4;
573 uint8_t *mac5 = (uint8_t *) address->address + 5;
574
575 uint32_t rah;
576 uint32_t ral;
577
578 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
579 rah = ((*mac5) << 8) | ((*mac4));
580
581 if (set_av_bit)
582 rah |= RAH_AV;
583 else
584 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
585
586 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
587 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
588}
589
590/** Disable receive address in RA registr
591 *
592 * Clear Address Valid bit
593 *
594 * @param e1000 E1000 data structure
595 * @param position RA register position
596 *
597 */
598static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
599{
600 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
601 rah = rah & ~RAH_AV;
602 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
603}
604
605/** Clear all unicast addresses from RA registers
606 *
607 * @param e1000 E1000 data structure
608 *
609 */
610static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
611{
612 for (unsigned int ra_num = 1;
613 ra_num <= e1000->unicast_ra_count;
614 ra_num++)
615 e1000_disable_receive_address(e1000, ra_num);
616
617 e1000->unicast_ra_count = 0;
618}
619
620/** Clear all multicast addresses from RA registers
621 *
622 * @param e1000 E1000 data structure
623 *
624 */
625static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
626{
627 unsigned int first_multicast_ra_num =
628 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
629
630 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
631 ra_num >= first_multicast_ra_num;
632 ra_num--)
633 e1000_disable_receive_address(e1000, ra_num);
634
635 e1000->multicast_ra_count = 0;
636}
637
638/** Return receive address filter positions count usable for unicast
639 *
640 * @param e1000 E1000 data structure
641 *
642 * @return receive address filter positions count usable for unicast
643 *
644 */
645static unsigned int get_free_unicast_address_count(e1000_t *e1000)
646{
647 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
648}
649
650/** Return receive address filter positions count usable for multicast
651 *
652 * @param e1000 E1000 data structure
653 *
654 * @return receive address filter positions count usable for multicast
655 *
656 */
657static unsigned int get_free_multicast_address_count(e1000_t *e1000)
658{
659 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
660}
661
662/** Write unicast receive addresses to receive address filter registers
663 *
664 * @param e1000 E1000 data structure
665 * @param addr Pointer to address array
666 * @param addr_cnt Address array count
667 *
668 */
669static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
670 const nic_address_t *addr, size_t addr_cnt)
671{
672 assert(addr_cnt <= get_free_unicast_address_count(e1000));
673
674 nic_address_t *addr_iterator = (nic_address_t *) addr;
675
676 /* ra_num = 0 is primary address */
677 for (unsigned int ra_num = 1;
678 ra_num <= addr_cnt;
679 ra_num++) {
680 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
681 addr_iterator++;
682 }
683}
684
685/** Write multicast receive addresses to receive address filter registers
686 *
687 * @param e1000 E1000 data structure
688 * @param addr Pointer to address array
689 * @param addr_cnt Address array count
690 *
691 */
692static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
693 const nic_address_t *addr, size_t addr_cnt)
694{
695 assert(addr_cnt <= get_free_multicast_address_count(e1000));
696
697 nic_address_t *addr_iterator = (nic_address_t *) addr;
698
699 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
700 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
701 ra_num >= first_multicast_ra_num;
702 ra_num--) {
703 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
704 addr_iterator++;
705 }
706}
707
708/** Disable receiving frames for default address
709 *
710 * @param e1000 E1000 data structure
711 *
712 */
713static void disable_ra0_address_filter(e1000_t *e1000)
714{
715 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
716 rah0 = rah0 & ~RAH_AV;
717 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
718}
719
720/** Enable receiving frames for default address
721 *
722 * @param e1000 E1000 data structure
723 *
724 */
725static void enable_ra0_address_filter(e1000_t *e1000)
726{
727 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
728 rah0 = rah0 | RAH_AV;
729 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
730}
731
732/** Disable unicast promiscuous mode
733 *
734 * @param e1000 E1000 data structure
735 *
736 */
737static void e1000_disable_unicast_promisc(e1000_t *e1000)
738{
739 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
740 rctl = rctl & ~RCTL_UPE;
741 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
742}
743
744/** Enable unicast promiscuous mode
745 *
746 * @param e1000 E1000 data structure
747 *
748 */
749static void e1000_enable_unicast_promisc(e1000_t *e1000)
750{
751 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
752 rctl = rctl | RCTL_UPE;
753 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
754}
755
756/** Disable multicast promiscuous mode
757 *
758 * @param e1000 E1000 data structure
759 *
760 */
761static void e1000_disable_multicast_promisc(e1000_t *e1000)
762{
763 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
764 rctl = rctl & ~RCTL_MPE;
765 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
766}
767
768/** Enable multicast promiscuous mode
769 *
770 * @param e1000 E1000 data structure
771 *
772 */
773static void e1000_enable_multicast_promisc(e1000_t *e1000)
774{
775 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
776 rctl = rctl | RCTL_MPE;
777 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
778}
779
780/** Enable accepting of broadcast frames
781 *
782 * @param e1000 E1000 data structure
783 *
784 */
785static void e1000_enable_broadcast_accept(e1000_t *e1000)
786{
787 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
788 rctl = rctl | RCTL_BAM;
789 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
790}
791
792/** Disable accepting of broadcast frames
793 *
794 * @param e1000 E1000 data structure
795 *
796 */
797static void e1000_disable_broadcast_accept(e1000_t *e1000)
798{
799 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
800 rctl = rctl & ~RCTL_BAM;
801 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
802}
803
804/** Enable VLAN filtering according to VFTA registers
805 *
806 * @param e1000 E1000 data structure
807 *
808 */
809static void e1000_enable_vlan_filter(e1000_t *e1000)
810{
811 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
812 rctl = rctl | RCTL_VFE;
813 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
814}
815
816/** Disable VLAN filtering
817 *
818 * @param e1000 E1000 data structure
819 *
820 */
821static void e1000_disable_vlan_filter(e1000_t *e1000)
822{
823 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
824 rctl = rctl & ~RCTL_VFE;
825 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
826}
827
828/** Set multicast frames acceptance mode
829 *
830 * @param nic NIC device to update
831 * @param mode Mode to set
832 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
833 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
834 *
835 * @return EOK
836 *
837 */
838static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
839 const nic_address_t *addr, size_t addr_cnt)
840{
841 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
842 errno_t rc = EOK;
843
844 fibril_mutex_lock(&e1000->rx_lock);
845
846 switch (mode) {
847 case NIC_MULTICAST_BLOCKED:
848 e1000_clear_multicast_receive_addresses(e1000);
849 e1000_disable_multicast_promisc(e1000);
850 nic_report_hw_filtering(nic, -1, 1, -1);
851 break;
852 case NIC_MULTICAST_LIST:
853 e1000_clear_multicast_receive_addresses(e1000);
854 if (addr_cnt > get_free_multicast_address_count(e1000)) {
855 /*
856 * Future work: fill MTA table
857 * Not strictly neccessary, it only saves some compares
858 * in the NIC library.
859 */
860 e1000_enable_multicast_promisc(e1000);
861 nic_report_hw_filtering(nic, -1, 0, -1);
862 } else {
863 e1000_disable_multicast_promisc(e1000);
864 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
865 nic_report_hw_filtering(nic, -1, 1, -1);
866 }
867 break;
868 case NIC_MULTICAST_PROMISC:
869 e1000_enable_multicast_promisc(e1000);
870 e1000_clear_multicast_receive_addresses(e1000);
871 nic_report_hw_filtering(nic, -1, 1, -1);
872 break;
873 default:
874 rc = ENOTSUP;
875 break;
876 }
877
878 fibril_mutex_unlock(&e1000->rx_lock);
879 return rc;
880}
881
882/** Set unicast frames acceptance mode
883 *
884 * @param nic NIC device to update
885 * @param mode Mode to set
886 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
887 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
888 *
889 * @return EOK
890 *
891 */
892static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
893 const nic_address_t *addr, size_t addr_cnt)
894{
895 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
896 errno_t rc = EOK;
897
898 fibril_mutex_lock(&e1000->rx_lock);
899
900 switch (mode) {
901 case NIC_UNICAST_BLOCKED:
902 disable_ra0_address_filter(e1000);
903 e1000_clear_unicast_receive_addresses(e1000);
904 e1000_disable_unicast_promisc(e1000);
905 nic_report_hw_filtering(nic, 1, -1, -1);
906 break;
907 case NIC_UNICAST_DEFAULT:
908 enable_ra0_address_filter(e1000);
909 e1000_clear_unicast_receive_addresses(e1000);
910 e1000_disable_unicast_promisc(e1000);
911 nic_report_hw_filtering(nic, 1, -1, -1);
912 break;
913 case NIC_UNICAST_LIST:
914 enable_ra0_address_filter(e1000);
915 e1000_clear_unicast_receive_addresses(e1000);
916 if (addr_cnt > get_free_unicast_address_count(e1000)) {
917 e1000_enable_unicast_promisc(e1000);
918 nic_report_hw_filtering(nic, 0, -1, -1);
919 } else {
920 e1000_disable_unicast_promisc(e1000);
921 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
922 nic_report_hw_filtering(nic, 1, -1, -1);
923 }
924 break;
925 case NIC_UNICAST_PROMISC:
926 e1000_enable_unicast_promisc(e1000);
927 enable_ra0_address_filter(e1000);
928 e1000_clear_unicast_receive_addresses(e1000);
929 nic_report_hw_filtering(nic, 1, -1, -1);
930 break;
931 default:
932 rc = ENOTSUP;
933 break;
934 }
935
936 fibril_mutex_unlock(&e1000->rx_lock);
937 return rc;
938}
939
940/** Set broadcast frames acceptance mode
941 *
942 * @param nic NIC device to update
943 * @param mode Mode to set
944 *
945 * @return EOK
946 *
947 */
948static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
949{
950 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
951 errno_t rc = EOK;
952
953 fibril_mutex_lock(&e1000->rx_lock);
954
955 switch (mode) {
956 case NIC_BROADCAST_BLOCKED:
957 e1000_disable_broadcast_accept(e1000);
958 break;
959 case NIC_BROADCAST_ACCEPTED:
960 e1000_enable_broadcast_accept(e1000);
961 break;
962 default:
963 rc = ENOTSUP;
964 break;
965 }
966
967 fibril_mutex_unlock(&e1000->rx_lock);
968 return rc;
969}
970
971/** Check if receiving is enabled
972 *
973 * @param e1000 E1000 data structure
974 *
975 * @return true if receiving is enabled
976 *
977 */
978static bool e1000_is_rx_enabled(e1000_t *e1000)
979{
980 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
981 return true;
982
983 return false;
984}
985
986/** Enable receiving
987 *
988 * @param e1000 E1000 data structure
989 *
990 */
991static void e1000_enable_rx(e1000_t *e1000)
992{
993 /* Set Receive Enable Bit */
994 E1000_REG_WRITE(e1000, E1000_RCTL,
995 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
996}
997
998/** Disable receiving
999 *
1000 * @param e1000 E1000 data structure
1001 *
1002 */
1003static void e1000_disable_rx(e1000_t *e1000)
1004{
1005 /* Clear Receive Enable Bit */
1006 E1000_REG_WRITE(e1000, E1000_RCTL,
1007 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
1008}
1009
1010/** Set VLAN mask
1011 *
1012 * @param nic NIC device to update
1013 * @param vlan_mask VLAN mask
1014 *
1015 */
1016static void e1000_on_vlan_mask_change(nic_t *nic,
1017 const nic_vlan_mask_t *vlan_mask)
1018{
1019 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1020
1021 fibril_mutex_lock(&e1000->rx_lock);
1022
1023 if (vlan_mask) {
1024 /*
1025 * Disable receiving, so that frame matching
1026 * partially written VLAN is not received.
1027 */
1028 bool rx_enabled = e1000_is_rx_enabled(e1000);
1029 if (rx_enabled)
1030 e1000_disable_rx(e1000);
1031
1032 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1033 uint32_t bitmap_part =
1034 ((uint32_t) vlan_mask->bitmap[i]) |
1035 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1036 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1037 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1038 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1039 }
1040
1041 e1000_enable_vlan_filter(e1000);
1042 if (rx_enabled)
1043 e1000_enable_rx(e1000);
1044 } else
1045 e1000_disable_vlan_filter(e1000);
1046
1047 fibril_mutex_unlock(&e1000->rx_lock);
1048}
1049
1050/** Set VLAN mask
1051 *
1052 * @param device E1000 device
1053 * @param tag VLAN tag
1054 *
1055 * @return EOK
1056 * @return ENOTSUP
1057 *
1058 */
1059static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1060 bool strip)
1061{
1062 /* VLAN CFI bit cannot be set */
1063 if (tag & VLANTAG_CFI)
1064 return ENOTSUP;
1065
1066 /*
1067 * CTRL.VME is neccessary for both strip and add
1068 * but CTRL.VME means stripping tags on receive.
1069 */
1070 if (!strip && add)
1071 return ENOTSUP;
1072
1073 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1074
1075 e1000->vlan_tag = tag;
1076 e1000->vlan_tag_add = add;
1077
1078 fibril_mutex_lock(&e1000->ctrl_lock);
1079
1080 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1081 if (strip)
1082 ctrl |= CTRL_VME;
1083 else
1084 ctrl &= ~CTRL_VME;
1085
1086 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1087
1088 fibril_mutex_unlock(&e1000->ctrl_lock);
1089 return EOK;
1090}
1091
1092/** Fill receive descriptor with new empty buffer
1093 *
1094 * Store frame in e1000->rx_frame_phys
1095 *
1096 * @param nic NIC data stricture
1097 * @param offset Receive descriptor offset
1098 *
1099 */
1100static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1101{
1102 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1103
1104 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1105 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1106
1107 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1108 rx_descriptor->length = 0;
1109 rx_descriptor->checksum = 0;
1110 rx_descriptor->status = 0;
1111 rx_descriptor->errors = 0;
1112 rx_descriptor->special = 0;
1113}
1114
1115/** Clear receive descriptor
1116 *
1117 * @param e1000 E1000 data
1118 * @param offset Receive descriptor offset
1119 *
1120 */
1121static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1122{
1123 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1124 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1125
1126 rx_descriptor->length = 0;
1127 rx_descriptor->checksum = 0;
1128 rx_descriptor->status = 0;
1129 rx_descriptor->errors = 0;
1130 rx_descriptor->special = 0;
1131}
1132
1133/** Clear receive descriptor
1134 *
1135 * @param nic NIC data
1136 * @param offset Receive descriptor offset
1137 *
1138 */
1139static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1140{
1141 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1142
1143 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1144 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1145
1146 tx_descriptor->phys_addr = 0;
1147 tx_descriptor->length = 0;
1148 tx_descriptor->checksum_offset = 0;
1149 tx_descriptor->command = 0;
1150 tx_descriptor->status = 0;
1151 tx_descriptor->checksum_start_field = 0;
1152 tx_descriptor->special = 0;
1153}
1154
1155/** Increment tail pointer for receive or transmit ring
1156 *
1157 * @param tail Old Tail
1158 * @param descriptors_count Ring length
1159 *
1160 * @return New tail
1161 *
1162 */
1163static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1164{
1165 if (tail + 1 == descriptors_count)
1166 return 0;
1167 else
1168 return tail + 1;
1169}
1170
1171/** Receive frames
1172 *
1173 * @param nic NIC data
1174 *
1175 */
1176static void e1000_receive_frames(nic_t *nic)
1177{
1178 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1179
1180 fibril_mutex_lock(&e1000->rx_lock);
1181
1182 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1183 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1184
1185 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1186 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1187
1188 while (rx_descriptor->status & 0x01) {
1189 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1190
1191 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1192 if (frame != NULL) {
1193 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1194 nic_received_frame(nic, frame);
1195 } else {
1196 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1197 }
1198
1199 e1000_fill_new_rx_descriptor(nic, next_tail);
1200
1201 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1202 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1203
1204 rx_descriptor = (e1000_rx_descriptor_t *)
1205 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1206 }
1207
1208 fibril_mutex_unlock(&e1000->rx_lock);
1209}
1210
1211/** Enable E1000 interupts
1212 *
1213 * @param e1000 E1000 data structure
1214 *
1215 */
1216static void e1000_enable_interrupts(e1000_t *e1000)
1217{
1218 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1219}
1220
1221/** Disable E1000 interupts
1222 *
1223 * @param e1000 E1000 data structure
1224 *
1225 */
1226static void e1000_disable_interrupts(e1000_t *e1000)
1227{
1228 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1229}
1230
1231/** Interrupt handler implementation
1232 *
1233 * This function is called from e1000_interrupt_handler()
1234 * and e1000_poll()
1235 *
1236 * @param nic NIC data
1237 * @param icr ICR register value
1238 *
1239 */
1240static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1241{
1242 if (icr & ICR_RXT0)
1243 e1000_receive_frames(nic);
1244}
1245
1246/** Handle device interrupt
1247 *
1248 * @param icall IPC call structure
1249 * @param arg Argument (nic_t *)
1250 *
1251 */
1252static void e1000_interrupt_handler(ipc_call_t *icall, void *arg)
1253{
1254 uint32_t icr = (uint32_t) ipc_get_arg2(icall);
1255 nic_t *nic = (nic_t *)arg;
1256 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1257
1258 e1000_interrupt_handler_impl(nic, icr);
1259 e1000_enable_interrupts(e1000);
1260}
1261
1262/** Register interrupt handler for the card in the system
1263 *
1264 * Note: The global irq_reg_mutex is locked because of work with global
1265 * structure.
1266 *
1267 * @param nic Driver data
1268 *
1269 * @param[out] handle IRQ capability handle if the handler was registered
1270 *
1271 * @return An error code otherwise
1272 *
1273 */
1274static errno_t e1000_register_int_handler(nic_t *nic,
1275 cap_irq_handle_t *handle)
1276{
1277 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1278
1279 /* Lock the mutex in whole driver while working with global structure */
1280 fibril_mutex_lock(&irq_reg_mutex);
1281
1282 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1283 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1284 e1000_irq_code.cmds[3].addr = e1000->reg_base_phys + E1000_IMC;
1285
1286 errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1287 e1000_interrupt_handler, (void *)nic, &e1000_irq_code, handle);
1288
1289 fibril_mutex_unlock(&irq_reg_mutex);
1290 return rc;
1291}
1292
1293/** Force receiving all frames in the receive buffer
1294 *
1295 * @param nic NIC data
1296 *
1297 */
1298static void e1000_poll(nic_t *nic)
1299{
1300 assert(nic);
1301
1302 e1000_t *e1000 = nic_get_specific(nic);
1303 assert(e1000);
1304
1305 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1306 e1000_interrupt_handler_impl(nic, icr);
1307}
1308
1309/** Calculates ITR register interrupt from timespec structure
1310 *
1311 * @param period Period
1312 *
1313 */
1314static uint16_t e1000_calculate_itr_interval(const struct timespec *period)
1315{
1316 // TODO: use also tv_sec
1317 return e1000_calculate_itr_interval_from_usecs(NSEC2USEC(period->tv_nsec));
1318}
1319
1320/** Set polling mode
1321 *
1322 * @param device Device to set
1323 * @param mode Mode to set
1324 * @param period Period for NIC_POLL_PERIODIC
1325 *
1326 * @return EOK if succeed
1327 * @return ENOTSUP if the mode is not supported
1328 *
1329 */
1330static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1331 const struct timespec *period)
1332{
1333 assert(nic);
1334
1335 e1000_t *e1000 = nic_get_specific(nic);
1336 assert(e1000);
1337
1338 switch (mode) {
1339 case NIC_POLL_IMMEDIATE:
1340 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1341 e1000_enable_interrupts(e1000);
1342 break;
1343 case NIC_POLL_ON_DEMAND:
1344 e1000_disable_interrupts(e1000);
1345 break;
1346 case NIC_POLL_PERIODIC:
1347 assert(period);
1348 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1349 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1350 e1000_enable_interrupts(e1000);
1351 break;
1352 default:
1353 return ENOTSUP;
1354 }
1355
1356 return EOK;
1357}
1358
1359/** Initialize receive registers
1360 *
1361 * @param e1000 E1000 data structure
1362 *
1363 */
1364static void e1000_initialize_rx_registers(e1000_t *e1000)
1365{
1366 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1367 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1368
1369 /* It is not posible to let HW use all descriptors */
1370 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1371
1372 /* Set Broadcast Enable Bit */
1373 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1374}
1375
1376/** Initialize receive structure
1377 *
1378 * @param nic NIC data
1379 *
1380 * @return EOK if succeed
1381 * @return An error code otherwise
1382 *
1383 */
1384static errno_t e1000_initialize_rx_structure(nic_t *nic)
1385{
1386 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1387 fibril_mutex_lock(&e1000->rx_lock);
1388
1389 e1000->rx_ring_virt = AS_AREA_ANY;
1390 errno_t rc = dmamem_map_anonymous(
1391 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1392 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1393 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1394 if (rc != EOK)
1395 return rc;
1396
1397 E1000_REG_WRITE(e1000, E1000_RDBAH,
1398 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1399 E1000_REG_WRITE(e1000, E1000_RDBAL,
1400 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1401
1402 e1000->rx_frame_phys = (uintptr_t *)
1403 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1404 e1000->rx_frame_virt =
1405 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1406 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1407 rc = ENOMEM;
1408 goto error;
1409 }
1410
1411 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1412 uintptr_t frame_phys;
1413 void *frame_virt = AS_AREA_ANY;
1414
1415 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1416 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1417 &frame_phys, &frame_virt);
1418 if (rc != EOK)
1419 goto error;
1420
1421 e1000->rx_frame_phys[i] = frame_phys;
1422 e1000->rx_frame_virt[i] = frame_virt;
1423 }
1424
1425 /* Write descriptor */
1426 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1427 e1000_fill_new_rx_descriptor(nic, i);
1428
1429 e1000_initialize_rx_registers(e1000);
1430
1431 fibril_mutex_unlock(&e1000->rx_lock);
1432 return EOK;
1433
1434error:
1435 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1436 if (e1000->rx_frame_virt[i] != NULL) {
1437 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1438 e1000->rx_frame_phys[i] = 0;
1439 e1000->rx_frame_virt[i] = NULL;
1440 }
1441 }
1442
1443 if (e1000->rx_frame_phys != NULL) {
1444 free(e1000->rx_frame_phys);
1445 e1000->rx_frame_phys = NULL;
1446 }
1447
1448 if (e1000->rx_frame_virt != NULL) {
1449 free(e1000->rx_frame_virt);
1450 e1000->rx_frame_virt = NULL;
1451 }
1452
1453 return rc;
1454}
1455
1456/** Uninitialize receive structure
1457 *
1458 * @param nic NIC data
1459 *
1460 */
1461static void e1000_uninitialize_rx_structure(nic_t *nic)
1462{
1463 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1464
1465 /* Write descriptor */
1466 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1467 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1468 e1000->rx_frame_phys[offset] = 0;
1469 e1000->rx_frame_virt[offset] = NULL;
1470 }
1471
1472 free(e1000->rx_frame_virt);
1473
1474 e1000->rx_frame_phys = NULL;
1475 e1000->rx_frame_virt = NULL;
1476
1477 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1478}
1479
1480/** Clear receive descriptor ring
1481 *
1482 * @param e1000 E1000 data
1483 *
1484 */
1485static void e1000_clear_rx_ring(e1000_t *e1000)
1486{
1487 /* Write descriptor */
1488 for (unsigned int offset = 0;
1489 offset < E1000_RX_FRAME_COUNT;
1490 offset++)
1491 e1000_clear_rx_descriptor(e1000, offset);
1492}
1493
1494/** Initialize filters
1495 *
1496 * @param e1000 E1000 data
1497 *
1498 */
1499static void e1000_initialize_filters(e1000_t *e1000)
1500{
1501 /* Initialize address filter */
1502 e1000->unicast_ra_count = 0;
1503 e1000->multicast_ra_count = 0;
1504 e1000_clear_unicast_receive_addresses(e1000);
1505}
1506
1507/** Initialize VLAN
1508 *
1509 * @param e1000 E1000 data
1510 *
1511 */
1512static void e1000_initialize_vlan(e1000_t *e1000)
1513{
1514 e1000->vlan_tag_add = false;
1515}
1516
1517/** Fill MAC address from EEPROM to RA[0] register
1518 *
1519 * @param e1000 E1000 data
1520 *
1521 */
1522static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1523{
1524 /* MAC address from eeprom to RA[0] */
1525 nic_address_t address;
1526 e1000_eeprom_get_address(e1000, &address);
1527 e1000_write_receive_address(e1000, 0, &address, true);
1528}
1529
1530/** Initialize other registers
1531 *
1532 * @param dev E1000 data.
1533 *
1534 * @return EOK if succeed
1535 * @return An error code otherwise
1536 *
1537 */
1538static void e1000_initialize_registers(e1000_t *e1000)
1539{
1540 E1000_REG_WRITE(e1000, E1000_ITR,
1541 e1000_calculate_itr_interval_from_usecs(
1542 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1543 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1544 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1545 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1546 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1547 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1548 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1549}
1550
1551/** Initialize transmit registers
1552 *
1553 * @param e1000 E1000 data.
1554 *
1555 */
1556static void e1000_initialize_tx_registers(e1000_t *e1000)
1557{
1558 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1559 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1560 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1561
1562 E1000_REG_WRITE(e1000, E1000_TIPG,
1563 10 << TIPG_IPGT_SHIFT |
1564 8 << TIPG_IPGR1_SHIFT |
1565 6 << TIPG_IPGR2_SHIFT);
1566
1567 E1000_REG_WRITE(e1000, E1000_TCTL,
1568 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1569 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1570 TCTL_PSP /* Pad Short Packets */);
1571}
1572
1573/** Initialize transmit structure
1574 *
1575 * @param e1000 E1000 data.
1576 *
1577 */
1578static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
1579{
1580 size_t i;
1581
1582 fibril_mutex_lock(&e1000->tx_lock);
1583
1584 e1000->tx_ring_phys = 0;
1585 e1000->tx_ring_virt = AS_AREA_ANY;
1586
1587 e1000->tx_frame_phys = NULL;
1588 e1000->tx_frame_virt = NULL;
1589
1590 errno_t rc = dmamem_map_anonymous(
1591 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1592 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1593 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1594 if (rc != EOK)
1595 goto error;
1596
1597 memset(e1000->tx_ring_virt, 0,
1598 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1599
1600 e1000->tx_frame_phys = (uintptr_t *)
1601 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1602 e1000->tx_frame_virt =
1603 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1604
1605 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1606 rc = ENOMEM;
1607 goto error;
1608 }
1609
1610 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1611 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1612 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1613 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1614 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1615 if (rc != EOK)
1616 goto error;
1617 }
1618
1619 E1000_REG_WRITE(e1000, E1000_TDBAH,
1620 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1621 E1000_REG_WRITE(e1000, E1000_TDBAL,
1622 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1623
1624 e1000_initialize_tx_registers(e1000);
1625
1626 fibril_mutex_unlock(&e1000->tx_lock);
1627 return EOK;
1628
1629error:
1630 if (e1000->tx_ring_virt != NULL) {
1631 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1632 e1000->tx_ring_virt = NULL;
1633 }
1634
1635 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1636 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1637 if (e1000->tx_frame_virt[i] != NULL) {
1638 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1639 e1000->tx_frame_phys[i] = 0;
1640 e1000->tx_frame_virt[i] = NULL;
1641 }
1642 }
1643 }
1644
1645 if (e1000->tx_frame_phys != NULL) {
1646 free(e1000->tx_frame_phys);
1647 e1000->tx_frame_phys = NULL;
1648 }
1649
1650 if (e1000->tx_frame_virt != NULL) {
1651 free(e1000->tx_frame_virt);
1652 e1000->tx_frame_virt = NULL;
1653 }
1654
1655 return rc;
1656}
1657
1658/** Uninitialize transmit structure
1659 *
1660 * @param nic NIC data
1661 *
1662 */
1663static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1664{
1665 size_t i;
1666
1667 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1668 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1669 e1000->tx_frame_phys[i] = 0;
1670 e1000->tx_frame_virt[i] = NULL;
1671 }
1672
1673 if (e1000->tx_frame_phys != NULL) {
1674 free(e1000->tx_frame_phys);
1675 e1000->tx_frame_phys = NULL;
1676 }
1677
1678 if (e1000->tx_frame_virt != NULL) {
1679 free(e1000->tx_frame_virt);
1680 e1000->tx_frame_virt = NULL;
1681 }
1682
1683 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1684}
1685
1686/** Clear transmit descriptor ring
1687 *
1688 * @param nic NIC data
1689 *
1690 */
1691static void e1000_clear_tx_ring(nic_t *nic)
1692{
1693 /* Write descriptor */
1694 for (unsigned int offset = 0;
1695 offset < E1000_TX_FRAME_COUNT;
1696 offset++)
1697 e1000_clear_tx_descriptor(nic, offset);
1698}
1699
1700/** Enable transmit
1701 *
1702 * @param e1000 E1000 data
1703 *
1704 */
1705static void e1000_enable_tx(e1000_t *e1000)
1706{
1707 /* Set Transmit Enable Bit */
1708 E1000_REG_WRITE(e1000, E1000_TCTL,
1709 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1710}
1711
1712/** Disable transmit
1713 *
1714 * @param e1000 E1000 data
1715 *
1716 */
1717static void e1000_disable_tx(e1000_t *e1000)
1718{
1719 /* Clear Transmit Enable Bit */
1720 E1000_REG_WRITE(e1000, E1000_TCTL,
1721 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1722}
1723
1724/** Reset E1000 device
1725 *
1726 * @param e1000 The E1000 data
1727 *
1728 */
1729static errno_t e1000_reset(nic_t *nic)
1730{
1731 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1732
1733 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1734
1735 /* Wait for the reset */
1736 fibril_usleep(20);
1737
1738 /* check if RST_BIT cleared */
1739 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1740 return EINVAL;
1741
1742 e1000_initialize_registers(e1000);
1743 e1000_initialize_rx_registers(e1000);
1744 e1000_initialize_tx_registers(e1000);
1745 e1000_fill_mac_from_eeprom(e1000);
1746 e1000_initialize_filters(e1000);
1747 e1000_initialize_vlan(e1000);
1748
1749 return EOK;
1750}
1751
1752/** Activate the device to receive and transmit frames
1753 *
1754 * @param nic NIC driver data
1755 *
1756 * @return EOK if activated successfully
1757 * @return Error code otherwise
1758 *
1759 */
1760static errno_t e1000_on_activating(nic_t *nic)
1761{
1762 assert(nic);
1763
1764 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1765
1766 fibril_mutex_lock(&e1000->rx_lock);
1767 fibril_mutex_lock(&e1000->tx_lock);
1768 fibril_mutex_lock(&e1000->ctrl_lock);
1769
1770 e1000_enable_interrupts(e1000);
1771
1772 errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
1773 if (rc != EOK) {
1774 e1000_disable_interrupts(e1000);
1775 fibril_mutex_unlock(&e1000->ctrl_lock);
1776 fibril_mutex_unlock(&e1000->tx_lock);
1777 fibril_mutex_unlock(&e1000->rx_lock);
1778 return rc;
1779 }
1780
1781 e1000_clear_rx_ring(e1000);
1782 e1000_enable_rx(e1000);
1783
1784 e1000_clear_tx_ring(nic);
1785 e1000_enable_tx(e1000);
1786
1787 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1788 ctrl |= CTRL_SLU;
1789 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1790
1791 fibril_mutex_unlock(&e1000->ctrl_lock);
1792 fibril_mutex_unlock(&e1000->tx_lock);
1793 fibril_mutex_unlock(&e1000->rx_lock);
1794
1795 return EOK;
1796}
1797
1798/** Callback for NIC_STATE_DOWN change
1799 *
1800 * @param nic NIC driver data
1801 *
1802 * @return EOK if succeed
1803 * @return Error code otherwise
1804 *
1805 */
1806static errno_t e1000_on_down_unlocked(nic_t *nic)
1807{
1808 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1809
1810 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1811 ctrl &= ~CTRL_SLU;
1812 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1813
1814 e1000_disable_tx(e1000);
1815 e1000_disable_rx(e1000);
1816
1817 hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
1818 e1000_disable_interrupts(e1000);
1819
1820 /*
1821 * Wait for the for the end of all data
1822 * transfers to descriptors.
1823 */
1824 fibril_usleep(100);
1825
1826 return EOK;
1827}
1828
1829/** Callback for NIC_STATE_DOWN change
1830 *
1831 * @param nic NIC driver data
1832 *
1833 * @return EOK if succeed
1834 * @return Error code otherwise
1835 *
1836 */
1837static errno_t e1000_on_down(nic_t *nic)
1838{
1839 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1840
1841 fibril_mutex_lock(&e1000->rx_lock);
1842 fibril_mutex_lock(&e1000->tx_lock);
1843 fibril_mutex_lock(&e1000->ctrl_lock);
1844
1845 errno_t rc = e1000_on_down_unlocked(nic);
1846
1847 fibril_mutex_unlock(&e1000->ctrl_lock);
1848 fibril_mutex_unlock(&e1000->tx_lock);
1849 fibril_mutex_unlock(&e1000->rx_lock);
1850
1851 return rc;
1852}
1853
1854/** Callback for NIC_STATE_STOPPED change
1855 *
1856 * @param nic NIC driver data
1857 *
1858 * @return EOK if succeed
1859 * @return Error code otherwise
1860 *
1861 */
1862static errno_t e1000_on_stopping(nic_t *nic)
1863{
1864 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1865
1866 fibril_mutex_lock(&e1000->rx_lock);
1867 fibril_mutex_lock(&e1000->tx_lock);
1868 fibril_mutex_lock(&e1000->ctrl_lock);
1869
1870 errno_t rc = e1000_on_down_unlocked(nic);
1871 if (rc == EOK)
1872 rc = e1000_reset(nic);
1873
1874 fibril_mutex_unlock(&e1000->ctrl_lock);
1875 fibril_mutex_unlock(&e1000->tx_lock);
1876 fibril_mutex_unlock(&e1000->rx_lock);
1877
1878 return rc;
1879}
1880
1881/** Create driver data structure
1882 *
1883 * @return Intialized device data structure or NULL
1884 *
1885 */
1886static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1887{
1888 nic_t *nic = nic_create_and_bind(dev);
1889 if (!nic)
1890 return NULL;
1891
1892 e1000_t *e1000 = malloc(sizeof(e1000_t));
1893 if (!e1000) {
1894 nic_unbind_and_destroy(dev);
1895 return NULL;
1896 }
1897
1898 memset(e1000, 0, sizeof(e1000_t));
1899 e1000->dev = dev;
1900
1901 nic_set_specific(nic, e1000);
1902 nic_set_send_frame_handler(nic, e1000_send_frame);
1903 nic_set_state_change_handlers(nic, e1000_on_activating,
1904 e1000_on_down, e1000_on_stopping);
1905 nic_set_filtering_change_handlers(nic,
1906 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1907 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1908 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1909
1910 fibril_mutex_initialize(&e1000->ctrl_lock);
1911 fibril_mutex_initialize(&e1000->rx_lock);
1912 fibril_mutex_initialize(&e1000->tx_lock);
1913 fibril_mutex_initialize(&e1000->eeprom_lock);
1914
1915 return e1000;
1916}
1917
1918/** Delete driver data structure
1919 *
1920 * @param data E1000 device data structure
1921 *
1922 */
1923static void e1000_delete_dev_data(ddf_dev_t *dev)
1924{
1925 assert(dev);
1926
1927 if (ddf_dev_data_get(dev) != NULL)
1928 nic_unbind_and_destroy(dev);
1929}
1930
1931/** Clean up the E1000 device structure.
1932 *
1933 * @param dev Device structure.
1934 *
1935 */
1936static void e1000_dev_cleanup(ddf_dev_t *dev)
1937{
1938 assert(dev);
1939
1940 e1000_delete_dev_data(dev);
1941}
1942
1943/** Fill the irq and io_addr part of device data structure
1944 *
1945 * The hw_resources must be obtained before calling this function
1946 *
1947 * @param dev Device structure
1948 * @param hw_resources Hardware resources obtained from the parent device
1949 *
1950 * @return EOK if succeed
1951 * @return An error code otherwise
1952 *
1953 */
1954static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
1955 const hw_res_list_parsed_t *hw_resources)
1956{
1957 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1958
1959 if (hw_resources->irqs.count != 1)
1960 return EINVAL;
1961
1962 e1000->irq = hw_resources->irqs.irqs[0];
1963 e1000->reg_base_phys =
1964 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1965
1966 return EOK;
1967}
1968
1969/** Obtain information about hardware resources of the device
1970 *
1971 * The device must be connected to the parent
1972 *
1973 * @param dev Device structure
1974 *
1975 * @return EOK if succeed
1976 * @return An error code otherwise
1977 *
1978 */
1979static errno_t e1000_get_resource_info(ddf_dev_t *dev)
1980{
1981 assert(dev != NULL);
1982 assert(NIC_DATA_DEV(dev) != NULL);
1983
1984 hw_res_list_parsed_t hw_res_parsed;
1985 hw_res_list_parsed_init(&hw_res_parsed);
1986
1987 /* Get hw resources form parent driver */
1988 errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1989 if (rc != EOK)
1990 return rc;
1991
1992 /* Fill resources information to the device */
1993 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1994 hw_res_list_parsed_clean(&hw_res_parsed);
1995
1996 return rc;
1997}
1998
1999/** Initialize the E1000 device structure
2000 *
2001 * @param dev Device information
2002 *
2003 * @return EOK if succeed
2004 * @return An error code otherwise
2005 *
2006 */
2007static errno_t e1000_device_initialize(ddf_dev_t *dev)
2008{
2009 /* Allocate driver data for the device. */
2010 e1000_t *e1000 = e1000_create_dev_data(dev);
2011 if (e1000 == NULL) {
2012 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
2013 return ENOMEM;
2014 }
2015
2016 e1000->parent_sess = ddf_dev_parent_sess_get(dev);
2017 if (e1000->parent_sess == NULL) {
2018 ddf_msg(LVL_ERROR, "Failed connecting parent device.");
2019 return EIO;
2020 }
2021
2022 /* Obtain and fill hardware resources info */
2023 errno_t rc = e1000_get_resource_info(dev);
2024 if (rc != EOK) {
2025 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2026 e1000_dev_cleanup(dev);
2027 return rc;
2028 }
2029
2030 uint16_t device_id;
2031 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2032 &device_id);
2033 if (rc != EOK) {
2034 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2035 e1000_dev_cleanup(dev);
2036 return rc;
2037 }
2038
2039 e1000_board_t board;
2040 switch (device_id) {
2041 case 0x100e:
2042 case 0x1015:
2043 case 0x1016:
2044 case 0x1017:
2045 board = E1000_82540;
2046 break;
2047 case 0x1013:
2048 case 0x1018:
2049 case 0x1078:
2050 board = E1000_82541;
2051 break;
2052 case 0x1076:
2053 case 0x1077:
2054 case 0x107c:
2055 board = E1000_82541REV2;
2056 break;
2057 case 0x100f:
2058 case 0x1011:
2059 case 0x1026:
2060 case 0x1027:
2061 case 0x1028:
2062 board = E1000_82545;
2063 break;
2064 case 0x1010:
2065 case 0x1012:
2066 case 0x101d:
2067 case 0x1079:
2068 case 0x107a:
2069 case 0x107b:
2070 board = E1000_82546;
2071 break;
2072 case 0x1019:
2073 case 0x101a:
2074 board = E1000_82547;
2075 break;
2076 case 0x10b9:
2077 board = E1000_82572;
2078 break;
2079 case 0x1096:
2080 board = E1000_80003ES2;
2081 break;
2082 default:
2083 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2084 device_id);
2085 e1000_dev_cleanup(dev);
2086 return ENOTSUP;
2087 }
2088
2089 switch (board) {
2090 case E1000_82540:
2091 case E1000_82541:
2092 case E1000_82541REV2:
2093 case E1000_82545:
2094 case E1000_82546:
2095 e1000->info.eerd_start = 0x01;
2096 e1000->info.eerd_done = 0x10;
2097 e1000->info.eerd_address_offset = 8;
2098 e1000->info.eerd_data_offset = 16;
2099 break;
2100 case E1000_82547:
2101 case E1000_82572:
2102 case E1000_80003ES2:
2103 e1000->info.eerd_start = 0x01;
2104 e1000->info.eerd_done = 0x02;
2105 e1000->info.eerd_address_offset = 2;
2106 e1000->info.eerd_data_offset = 16;
2107 break;
2108 }
2109
2110 return EOK;
2111}
2112
2113/** Enable the I/O ports of the device.
2114 *
2115 * @param dev E1000 device.
2116 *
2117 * @return EOK if successed
2118 * @return An error code otherwise
2119 *
2120 */
2121static errno_t e1000_pio_enable(ddf_dev_t *dev)
2122{
2123 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2124
2125 errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2126 &e1000->reg_base_virt);
2127 if (rc != EOK)
2128 return EADDRNOTAVAIL;
2129
2130 return EOK;
2131}
2132
2133/** Probe and initialize the newly added device.
2134 *
2135 * @param dev E1000 device.
2136 *
2137 */
2138errno_t e1000_dev_add(ddf_dev_t *dev)
2139{
2140 ddf_fun_t *fun;
2141
2142 /* Initialize device structure for E1000 */
2143 errno_t rc = e1000_device_initialize(dev);
2144 if (rc != EOK)
2145 return rc;
2146
2147 /* Device initialization */
2148 nic_t *nic = ddf_dev_data_get(dev);
2149 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2150
2151 /* Map registers */
2152 rc = e1000_pio_enable(dev);
2153 if (rc != EOK)
2154 goto err_destroy;
2155
2156 e1000_initialize_registers(e1000);
2157 rc = e1000_initialize_tx_structure(e1000);
2158 if (rc != EOK)
2159 goto err_pio;
2160
2161 fibril_mutex_lock(&e1000->rx_lock);
2162
2163 e1000_fill_mac_from_eeprom(e1000);
2164 e1000_initialize_filters(e1000);
2165
2166 fibril_mutex_unlock(&e1000->rx_lock);
2167
2168 e1000_initialize_vlan(e1000);
2169
2170 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2171 if (fun == NULL)
2172 goto err_tx_structure;
2173 nic_set_ddf_fun(nic, fun);
2174 ddf_fun_set_ops(fun, &e1000_dev_ops);
2175
2176 cap_irq_handle_t irq_handle;
2177 rc = e1000_register_int_handler(nic, &irq_handle);
2178 if (rc != EOK) {
2179 goto err_fun_create;
2180 }
2181
2182 rc = e1000_initialize_rx_structure(nic);
2183 if (rc != EOK)
2184 goto err_irq;
2185
2186 nic_address_t e1000_address;
2187 e1000_get_address(e1000, &e1000_address);
2188 rc = nic_report_address(nic, &e1000_address);
2189 if (rc != EOK)
2190 goto err_rx_structure;
2191
2192 struct timespec period;
2193 period.tv_sec = 0;
2194 period.tv_nsec = USEC2NSEC(E1000_DEFAULT_INTERRUPT_INTERVAL_USEC);
2195 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2196 if (rc != EOK)
2197 goto err_rx_structure;
2198
2199 rc = ddf_fun_bind(fun);
2200 if (rc != EOK)
2201 goto err_fun_bind;
2202
2203 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2204 if (rc != EOK)
2205 goto err_add_to_cat;
2206
2207 return EOK;
2208
2209err_add_to_cat:
2210 ddf_fun_unbind(fun);
2211err_fun_bind:
2212err_rx_structure:
2213 e1000_uninitialize_rx_structure(nic);
2214err_irq:
2215 unregister_interrupt_handler(dev, irq_handle);
2216err_fun_create:
2217 ddf_fun_destroy(fun);
2218 nic_set_ddf_fun(nic, NULL);
2219err_tx_structure:
2220 e1000_uninitialize_tx_structure(e1000);
2221err_pio:
2222 // TODO: e1000_pio_disable(dev);
2223err_destroy:
2224 e1000_dev_cleanup(dev);
2225 return rc;
2226}
2227
2228/** Quiesce E1000 device.
2229 *
2230 * @param dev E1000 device.
2231 *
2232 */
2233errno_t e1000_dev_quiesce(ddf_dev_t *dev)
2234{
2235 nic_t *nic = ddf_dev_data_get(dev);
2236 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2237 errno_t rc;
2238
2239 ddf_msg(LVL_DEBUG, "e1000_dev_quiesce()");
2240
2241 e1000_disable_interrupts(e1000);
2242 rc = e1000_reset(nic);
2243 if (rc != EOK)
2244 ddf_msg(LVL_ERROR, "e1000_dev_quiesce failed");
2245 return rc;
2246}
2247
2248/** Read 16-bit value from EEPROM of E1000 adapter
2249 *
2250 * Read using the EERD register.
2251 *
2252 * @param device E1000 device
2253 * @param eeprom_address 8-bit EEPROM address
2254 *
2255 * @return 16-bit value from EEPROM
2256 *
2257 */
2258static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2259{
2260 fibril_mutex_lock(&e1000->eeprom_lock);
2261
2262 /* Write address and START bit to EERD register */
2263 uint32_t write_data = e1000->info.eerd_start |
2264 (((uint32_t) eeprom_address) <<
2265 e1000->info.eerd_address_offset);
2266 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2267
2268 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2269 while ((eerd & e1000->info.eerd_done) == 0) {
2270 fibril_usleep(1);
2271 eerd = E1000_REG_READ(e1000, E1000_EERD);
2272 }
2273
2274 fibril_mutex_unlock(&e1000->eeprom_lock);
2275
2276 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2277}
2278
2279/** Get MAC address of the E1000 adapter
2280 *
2281 * @param device E1000 device
2282 * @param address Place to store the address
2283 * @param max_len Maximal addresss length to store
2284 *
2285 * @return EOK if succeed
2286 * @return An error code otherwise
2287 *
2288 */
2289static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
2290{
2291 fibril_mutex_lock(&e1000->rx_lock);
2292
2293 uint8_t *mac0_dest = (uint8_t *) address->address;
2294 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2295 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2296 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2297 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2298 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2299
2300 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2301 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2302
2303 *mac0_dest = (uint8_t) ral;
2304 *mac1_dest = (uint8_t) (ral >> 8);
2305 *mac2_dest = (uint8_t) (ral >> 16);
2306 *mac3_dest = (uint8_t) (ral >> 24);
2307 *mac4_dest = (uint8_t) rah;
2308 *mac5_dest = (uint8_t) (rah >> 8);
2309
2310 fibril_mutex_unlock(&e1000->rx_lock);
2311 return EOK;
2312}
2313
2314/** Set card MAC address
2315 *
2316 * @param device E1000 device
2317 * @param address Address
2318 *
2319 * @return EOK if succeed
2320 * @return An error code otherwise
2321 */
2322static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2323{
2324 nic_t *nic = NIC_DATA_FUN(fun);
2325 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2326
2327 fibril_mutex_lock(&e1000->rx_lock);
2328 fibril_mutex_lock(&e1000->tx_lock);
2329
2330 errno_t rc = nic_report_address(nic, addr);
2331 if (rc == EOK)
2332 e1000_write_receive_address(e1000, 0, addr, false);
2333
2334 fibril_mutex_unlock(&e1000->tx_lock);
2335 fibril_mutex_unlock(&e1000->rx_lock);
2336
2337 return rc;
2338}
2339
2340static void e1000_eeprom_get_address(e1000_t *e1000,
2341 nic_address_t *address)
2342{
2343 uint16_t *mac0_dest = (uint16_t *) address->address;
2344 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2345 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2346
2347 *mac0_dest = e1000_eeprom_read(e1000, 0);
2348 *mac2_dest = e1000_eeprom_read(e1000, 1);
2349 *mac4_dest = e1000_eeprom_read(e1000, 2);
2350}
2351
2352/** Send frame
2353 *
2354 * @param nic NIC driver data structure
2355 * @param data Frame data
2356 * @param size Frame size in bytes
2357 *
2358 * @return EOK if succeed
2359 * @return Error code in the case of error
2360 *
2361 */
2362static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2363{
2364 assert(nic);
2365
2366 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2367 fibril_mutex_lock(&e1000->tx_lock);
2368
2369 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2370 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2371 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2372
2373 bool descriptor_available = false;
2374
2375 /* Descriptor never used */
2376 if (tx_descriptor_addr->length == 0)
2377 descriptor_available = true;
2378
2379 /* Descriptor done */
2380 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2381 descriptor_available = true;
2382
2383 if (!descriptor_available) {
2384 /* Frame lost */
2385 fibril_mutex_unlock(&e1000->tx_lock);
2386 return;
2387 }
2388
2389 memcpy(e1000->tx_frame_virt[tdt], data, size);
2390
2391 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2392 tx_descriptor_addr->length = size;
2393
2394 /*
2395 * Report status to STATUS.DD (descriptor done),
2396 * add ethernet CRC, end of packet.
2397 */
2398 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2399 TXDESCRIPTOR_COMMAND_IFCS |
2400 TXDESCRIPTOR_COMMAND_EOP;
2401
2402 tx_descriptor_addr->checksum_offset = 0;
2403 tx_descriptor_addr->status = 0;
2404 if (e1000->vlan_tag_add) {
2405 tx_descriptor_addr->special = e1000->vlan_tag;
2406 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2407 } else
2408 tx_descriptor_addr->special = 0;
2409
2410 tx_descriptor_addr->checksum_start_field = 0;
2411
2412 tdt++;
2413 if (tdt == E1000_TX_FRAME_COUNT)
2414 tdt = 0;
2415
2416 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2417
2418 fibril_mutex_unlock(&e1000->tx_lock);
2419}
2420
2421int main(void)
2422{
2423 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2424
2425 if (nic_driver_init(NAME) != EOK)
2426 return 1;
2427
2428 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2429 &e1000_nic_iface);
2430
2431 ddf_log_init(NAME);
2432 return ddf_driver_main(&e1000_driver);
2433}
Note: See TracBrowser for help on using the repository browser.