source: mainline/uspace/drv/nic/e1k/e1k.c@ b1213b0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b1213b0 was b1213b0, checked in by Jiri Svoboda <jiri@…>, 13 years ago

Merge internet stack rewrite (IP+ICMP, UDP, IP over Ethernet).
  • Property mode set to 100644
File size: 55.6 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <byteorder.h>
41#include <sysinfo.h>
42#include <ipc/irc.h>
43#include <ipc/ns.h>
44#include <libarch/ddi.h>
45#include <as.h>
46#include <ddf/log.h>
47#include <ddf/interrupt.h>
48#include <device/hw_res_parsed.h>
49#include <device/pci.h>
50#include <nic.h>
51#include <ops/nic.h>
52#include "e1k.h"
53
54#define NAME "e1k"
55
56#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
57
58/* Must be power of 8 */
59#define E1000_RX_FRAME_COUNT 128
60#define E1000_TX_FRAME_COUNT 128
61
62#define E1000_RECEIVE_ADDRESS 16
63
64/** Maximum sending frame size */
65#define E1000_MAX_SEND_FRAME_SIZE 2048
66/** Maximum receiving frame size */
67#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
68
69/** nic_driver_data_t* -> e1000_t* cast */
70#define DRIVER_DATA_NIC(nic) \
71 ((e1000_t *) nic_get_specific(nic))
72
73/** device_t* -> nic_driver_data_t* cast */
74#define NIC_DATA_DEV(dev) \
75 ((nic_t *) ((dev)->driver_data))
76
77/** device_t* -> e1000_t* cast */
78#define DRIVER_DATA_DEV(dev) \
79 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
80
81/** Cast pointer to uint64_t
82 *
83 * @param ptr Pointer to cast
84 *
85 * @return The uint64_t pointer representation.
86 *
87 */
88#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
89
90/** Cast the memaddr part to the void*
91 *
92 * @param memaddr The memaddr value
93 *
94 */
95#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
96
97#define E1000_REG_BASE(e1000) \
98 ((e1000)->reg_base_virt)
99
100#define E1000_REG_ADDR(e1000, reg) \
101 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
102
103#define E1000_REG_READ(e1000, reg) \
104 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
105
106#define E1000_REG_WRITE(e1000, reg, value) \
107 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
108
109/** E1000 device data */
110typedef struct {
111 /** Device configuration */
112 e1000_info_t info;
113
114 /** Physical registers base address */
115 void *reg_base_phys;
116 /** Virtual registers base address */
117 void *reg_base_virt;
118
119 /** Physical tx ring address */
120 void *tx_ring_phys;
121 /** Virtual tx ring address */
122 void *tx_ring_virt;
123
124 /** Ring of TX frames, physical address */
125 void **tx_frame_phys;
126 /** Ring of TX frames, virtual address */
127 void **tx_frame_virt;
128
129 /** Physical rx ring address */
130 void *rx_ring_phys;
131 /** Virtual rx ring address */
132 void *rx_ring_virt;
133
134 /** Ring of RX frames, physical address */
135 void **rx_frame_phys;
136 /** Ring of RX frames, virtual address */
137 void **rx_frame_virt;
138
139 /** VLAN tag */
140 uint16_t vlan_tag;
141
142 /** Add VLAN tag to frame */
143 bool vlan_tag_add;
144
145 /** Used unicast Receive Address count */
146 unsigned int unicast_ra_count;
147
148 /** Used milticast Receive addrress count */
149 unsigned int multicast_ra_count;
150
151 /** The irq assigned */
152 int irq;
153
154 /** Lock for CTRL register */
155 fibril_mutex_t ctrl_lock;
156
157 /** Lock for receiver */
158 fibril_mutex_t rx_lock;
159
160 /** Lock for transmitter */
161 fibril_mutex_t tx_lock;
162
163 /** Lock for EEPROM access */
164 fibril_mutex_t eeprom_lock;
165} e1000_t;
166
167/** Global mutex for work with shared irq structure */
168FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
169
170static int e1000_get_address(e1000_t *, nic_address_t *);
171static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
172static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
173
174static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
175static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
176
177static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
178static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
179static int e1000_get_operation_mode(ddf_fun_t *, int *,
180 nic_channel_mode_t *, nic_role_t *);
181static int e1000_set_operation_mode(ddf_fun_t *, int,
182 nic_channel_mode_t, nic_role_t);
183static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
184static int e1000_autoneg_disable(ddf_fun_t *);
185static int e1000_autoneg_restart(ddf_fun_t *);
186
187static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
188
189/** Network interface options for E1000 card driver */
190static nic_iface_t e1000_nic_iface;
191
192/** Network interface options for E1000 card driver */
193static nic_iface_t e1000_nic_iface = {
194 .set_address = &e1000_set_addr,
195 .get_device_info = &e1000_get_device_info,
196 .get_cable_state = &e1000_get_cable_state,
197 .get_operation_mode = &e1000_get_operation_mode,
198 .set_operation_mode = &e1000_set_operation_mode,
199 .autoneg_enable = &e1000_autoneg_enable,
200 .autoneg_disable = &e1000_autoneg_disable,
201 .autoneg_restart = &e1000_autoneg_restart,
202 .vlan_set_tag = &e1000_vlan_set_tag,
203 .defective_get_mode = &e1000_defective_get_mode,
204 .defective_set_mode = &e1000_defective_set_mode,
205};
206
207/** Basic device operations for E1000 driver */
208static ddf_dev_ops_t e1000_dev_ops;
209
210static int e1000_dev_add(ddf_dev_t *);
211
212/** Basic driver operations for E1000 driver */
213static driver_ops_t e1000_driver_ops = {
214 .dev_add = e1000_dev_add
215};
216
217/** Driver structure for E1000 driver */
218static driver_t e1000_driver = {
219 .name = NAME,
220 .driver_ops = &e1000_driver_ops
221};
222
223/* The default implementation callbacks */
224static int e1000_on_activating(nic_t *);
225static int e1000_on_stopping(nic_t *);
226static void e1000_send_frame(nic_t *, void *, size_t);
227
228/** PIO ranges used in the IRQ code. */
229irq_pio_range_t e1000_irq_pio_ranges[] = {
230 {
231 .base = 0,
232 .size = PAGE_SIZE, /* XXX */
233 }
234};
235
236/** Commands to deal with interrupt
237 *
238 */
239irq_cmd_t e1000_irq_commands[] = {
240 {
241 /* Get the interrupt status */
242 .cmd = CMD_PIO_READ_32,
243 .addr = NULL,
244 .dstarg = 2
245 },
246 {
247 .cmd = CMD_PREDICATE,
248 .value = 2,
249 .srcarg = 2
250 },
251 {
252 /* Disable interrupts until interrupt routine is finished */
253 .cmd = CMD_PIO_WRITE_32,
254 .addr = NULL,
255 .value = 0xffffffff
256 },
257 {
258 .cmd = CMD_ACCEPT
259 }
260};
261
262/** Interrupt code definition */
263irq_code_t e1000_irq_code = {
264 .rangecount = sizeof(e1000_irq_pio_ranges) /
265 sizeof(irq_pio_range_t),
266 .ranges = e1000_irq_pio_ranges,
267 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
268 .cmds = e1000_irq_commands
269};
270
271/** Get the device information
272 *
273 * @param dev NIC device
274 * @param info Information to fill
275 *
276 * @return EOK
277 *
278 */
279static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
280{
281 assert(dev);
282 assert(info);
283
284 bzero(info, sizeof(nic_device_info_t));
285
286 info->vendor_id = 0x8086;
287 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
288 "Intel Corporation");
289 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
290 "Intel Pro");
291
292 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
293 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
294 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
295
296 return EOK;
297}
298
299/** Check the cable state
300 *
301 * @param[in] dev device
302 * @param[out] state state to fill
303 *
304 * @return EOK
305 *
306 */
307static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
308{
309 assert(dev);
310 assert(DRIVER_DATA_DEV(dev));
311 assert(state);
312
313 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
314 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
315 *state = NIC_CS_PLUGGED;
316 else
317 *state = NIC_CS_UNPLUGGED;
318
319 return EOK;
320}
321
322static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
323{
324 return useconds * 4;
325}
326
327/** Get operation mode of the device
328 *
329 */
330static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
331 nic_channel_mode_t *duplex, nic_role_t *role)
332{
333 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
334 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
335
336 if (status & STATUS_FD)
337 *duplex = NIC_CM_FULL_DUPLEX;
338 else
339 *duplex = NIC_CM_HALF_DUPLEX;
340
341 uint32_t speed_bits =
342 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
343
344 if (speed_bits == STATUS_SPEED_10)
345 *speed = 10;
346 else if (speed_bits == STATUS_SPEED_100)
347 *speed = 100;
348 else if ((speed_bits == STATUS_SPEED_1000A) ||
349 (speed_bits == STATUS_SPEED_1000B))
350 *speed = 1000;
351
352 *role = NIC_ROLE_UNKNOWN;
353 return EOK;
354}
355
356static void e1000_link_restart(e1000_t *e1000)
357{
358 fibril_mutex_lock(&e1000->ctrl_lock);
359
360 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
361
362 if (ctrl & CTRL_SLU) {
363 ctrl &= ~(CTRL_SLU);
364 fibril_mutex_unlock(&e1000->ctrl_lock);
365 usleep(10);
366 fibril_mutex_lock(&e1000->ctrl_lock);
367 ctrl |= CTRL_SLU;
368 }
369
370 fibril_mutex_unlock(&e1000->ctrl_lock);
371
372 e1000_link_restart(e1000);
373}
374
375/** Set operation mode of the device
376 *
377 */
378static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
379 nic_channel_mode_t duplex, nic_role_t role)
380{
381 if ((speed != 10) && (speed != 100) && (speed != 1000))
382 return EINVAL;
383
384 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
385 return EINVAL;
386
387 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
388
389 fibril_mutex_lock(&e1000->ctrl_lock);
390 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
391
392 ctrl |= CTRL_FRCSPD;
393 ctrl |= CTRL_FRCDPLX;
394 ctrl &= ~(CTRL_ASDE);
395
396 if (duplex == NIC_CM_FULL_DUPLEX)
397 ctrl |= CTRL_FD;
398 else
399 ctrl &= ~(CTRL_FD);
400
401 ctrl &= ~(CTRL_SPEED_MASK);
402 if (speed == 1000)
403 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
404 else if (speed == 100)
405 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
406 else
407 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
408
409 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
410
411 fibril_mutex_unlock(&e1000->ctrl_lock);
412
413 e1000_link_restart(e1000);
414
415 return EOK;
416}
417
418/** Enable auto-negotiation
419 *
420 * @param dev Device to update
421 * @param advertisement Ignored on E1000
422 *
423 * @return EOK if advertisement mode set successfully
424 *
425 */
426static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
427{
428 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
429
430 fibril_mutex_lock(&e1000->ctrl_lock);
431
432 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
433
434 ctrl &= ~(CTRL_FRCSPD);
435 ctrl &= ~(CTRL_FRCDPLX);
436 ctrl |= CTRL_ASDE;
437
438 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
439
440 fibril_mutex_unlock(&e1000->ctrl_lock);
441
442 e1000_link_restart(e1000);
443
444 return EOK;
445}
446
447/** Disable auto-negotiation
448 *
449 * @param dev Device to update
450 *
451 * @return EOK
452 *
453 */
454static int e1000_autoneg_disable(ddf_fun_t *dev)
455{
456 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
457
458 fibril_mutex_lock(&e1000->ctrl_lock);
459
460 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
461
462 ctrl |= CTRL_FRCSPD;
463 ctrl |= CTRL_FRCDPLX;
464 ctrl &= ~(CTRL_ASDE);
465
466 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
467
468 fibril_mutex_unlock(&e1000->ctrl_lock);
469
470 e1000_link_restart(e1000);
471
472 return EOK;
473}
474
475/** Restart auto-negotiation
476 *
477 * @param dev Device to update
478 *
479 * @return EOK if advertisement mode set successfully
480 *
481 */
482static int e1000_autoneg_restart(ddf_fun_t *dev)
483{
484 return e1000_autoneg_enable(dev, 0);
485}
486
487/** Get state of acceptance of weird frames
488 *
489 * @param device Device to check
490 * @param[out] mode Current mode
491 *
492 */
493static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
494{
495 e1000_t *e1000 = DRIVER_DATA_DEV(device);
496
497 *mode = 0;
498 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
499 if (rctl & RCTL_SBP)
500 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
501
502 return EOK;
503};
504
505/** Set acceptance of weird frames
506 *
507 * @param device Device to update
508 * @param mode Mode to set
509 *
510 * @return ENOTSUP if the mode is not supported
511 * @return EOK of mode was set
512 *
513 */
514static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
515{
516 e1000_t *e1000 = DRIVER_DATA_DEV(device);
517 int rc = EOK;
518
519 fibril_mutex_lock(&e1000->rx_lock);
520
521 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
522 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
523 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
524
525 if (short_mode && bad_mode)
526 rctl |= RCTL_SBP;
527 else if ((!short_mode) && (!bad_mode))
528 rctl &= ~RCTL_SBP;
529 else
530 rc = ENOTSUP;
531
532 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
533
534 fibril_mutex_unlock(&e1000->rx_lock);
535 return rc;
536};
537
538/** Write receive address to RA registr
539 *
540 * @param e1000 E1000 data structure
541 * @param position RA register position
542 * @param address Ethernet address
543 * @param set_av_bit Set the Addtess Valid bit
544 *
545 */
546static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
547 const nic_address_t * address, bool set_av_bit)
548{
549 uint8_t *mac0 = (uint8_t *) address->address;
550 uint8_t *mac1 = (uint8_t *) address->address + 1;
551 uint8_t *mac2 = (uint8_t *) address->address + 2;
552 uint8_t *mac3 = (uint8_t *) address->address + 3;
553 uint8_t *mac4 = (uint8_t *) address->address + 4;
554 uint8_t *mac5 = (uint8_t *) address->address + 5;
555
556 uint32_t rah;
557 uint32_t ral;
558
559 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
560 rah = ((*mac5) << 8) | ((*mac4));
561
562 if (set_av_bit)
563 rah |= RAH_AV;
564 else
565 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
566
567 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
568 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
569}
570
571/** Disable receive address in RA registr
572 *
573 * Clear Address Valid bit
574 *
575 * @param e1000 E1000 data structure
576 * @param position RA register position
577 *
578 */
579static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
580{
581 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
582 rah = rah & ~RAH_AV;
583 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
584}
585
586/** Clear all unicast addresses from RA registers
587 *
588 * @param e1000 E1000 data structure
589 *
590 */
591static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
592{
593 for (unsigned int ra_num = 1;
594 ra_num <= e1000->unicast_ra_count;
595 ra_num++)
596 e1000_disable_receive_address(e1000, ra_num);
597
598 e1000->unicast_ra_count = 0;
599}
600
601/** Clear all multicast addresses from RA registers
602 *
603 * @param e1000 E1000 data structure
604 *
605 */
606static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
607{
608 unsigned int first_multicast_ra_num =
609 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
610
611 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
612 ra_num >= first_multicast_ra_num;
613 ra_num--)
614 e1000_disable_receive_address(e1000, ra_num);
615
616 e1000->multicast_ra_count = 0;
617}
618
619/** Return receive address filter positions count usable for unicast
620 *
621 * @param e1000 E1000 data structure
622 *
623 * @return receive address filter positions count usable for unicast
624 *
625 */
626static unsigned int get_free_unicast_address_count(e1000_t *e1000)
627{
628 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
629}
630
631/** Return receive address filter positions count usable for multicast
632 *
633 * @param e1000 E1000 data structure
634 *
635 * @return receive address filter positions count usable for multicast
636 *
637 */
638static unsigned int get_free_multicast_address_count(e1000_t *e1000)
639{
640 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
641}
642
643/** Write unicast receive addresses to receive address filter registers
644 *
645 * @param e1000 E1000 data structure
646 * @param addr Pointer to address array
647 * @param addr_cnt Address array count
648 *
649 */
650static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
651 const nic_address_t *addr, size_t addr_cnt)
652{
653 assert(addr_cnt <= get_free_unicast_address_count(e1000));
654
655 nic_address_t *addr_iterator = (nic_address_t *) addr;
656
657 /* ra_num = 0 is primary address */
658 for (unsigned int ra_num = 1;
659 ra_num <= addr_cnt;
660 ra_num++) {
661 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
662 addr_iterator++;
663 }
664}
665
666/** Write multicast receive addresses to receive address filter registers
667 *
668 * @param e1000 E1000 data structure
669 * @param addr Pointer to address array
670 * @param addr_cnt Address array count
671 *
672 */
673static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
674 const nic_address_t *addr, size_t addr_cnt)
675{
676 assert(addr_cnt <= get_free_multicast_address_count(e1000));
677
678 nic_address_t *addr_iterator = (nic_address_t *) addr;
679
680 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
681 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
682 ra_num >= first_multicast_ra_num;
683 ra_num--) {
684 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
685 addr_iterator++;
686 }
687}
688
689/** Disable receiving frames for default address
690 *
691 * @param e1000 E1000 data structure
692 *
693 */
694static void disable_ra0_address_filter(e1000_t *e1000)
695{
696 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
697 rah0 = rah0 & ~RAH_AV;
698 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
699}
700
701/** Enable receiving frames for default address
702 *
703 * @param e1000 E1000 data structure
704 *
705 */
706static void enable_ra0_address_filter(e1000_t *e1000)
707{
708 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
709 rah0 = rah0 | RAH_AV;
710 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
711}
712
713/** Disable unicast promiscuous mode
714 *
715 * @param e1000 E1000 data structure
716 *
717 */
718static void e1000_disable_unicast_promisc(e1000_t *e1000)
719{
720 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
721 rctl = rctl & ~RCTL_UPE;
722 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
723}
724
725/** Enable unicast promiscuous mode
726 *
727 * @param e1000 E1000 data structure
728 *
729 */
730static void e1000_enable_unicast_promisc(e1000_t *e1000)
731{
732 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
733 rctl = rctl | RCTL_UPE;
734 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
735}
736
737/** Disable multicast promiscuous mode
738 *
739 * @param e1000 E1000 data structure
740 *
741 */
742static void e1000_disable_multicast_promisc(e1000_t *e1000)
743{
744 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
745 rctl = rctl & ~RCTL_MPE;
746 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
747}
748
749/** Enable multicast promiscuous mode
750 *
751 * @param e1000 E1000 data structure
752 *
753 */
754static void e1000_enable_multicast_promisc(e1000_t *e1000)
755{
756 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
757 rctl = rctl | RCTL_MPE;
758 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
759}
760
761/** Enable accepting of broadcast frames
762 *
763 * @param e1000 E1000 data structure
764 *
765 */
766static void e1000_enable_broadcast_accept(e1000_t *e1000)
767{
768 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
769 rctl = rctl | RCTL_BAM;
770 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
771}
772
773/** Disable accepting of broadcast frames
774 *
775 * @param e1000 E1000 data structure
776 *
777 */
778static void e1000_disable_broadcast_accept(e1000_t *e1000)
779{
780 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
781 rctl = rctl & ~RCTL_BAM;
782 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
783}
784
785/** Enable VLAN filtering according to VFTA registers
786 *
787 * @param e1000 E1000 data structure
788 *
789 */
790static void e1000_enable_vlan_filter(e1000_t *e1000)
791{
792 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
793 rctl = rctl | RCTL_VFE;
794 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
795}
796
797/** Disable VLAN filtering
798 *
799 * @param e1000 E1000 data structure
800 *
801 */
802static void e1000_disable_vlan_filter(e1000_t *e1000)
803{
804 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
805 rctl = rctl & ~RCTL_VFE;
806 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
807}
808
809/** Set multicast frames acceptance mode
810 *
811 * @param nic NIC device to update
812 * @param mode Mode to set
813 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
814 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
815 *
816 * @return EOK
817 *
818 */
819static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
820 const nic_address_t *addr, size_t addr_cnt)
821{
822 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
823 int rc = EOK;
824
825 fibril_mutex_lock(&e1000->rx_lock);
826
827 switch (mode) {
828 case NIC_MULTICAST_BLOCKED:
829 e1000_clear_multicast_receive_addresses(e1000);
830 e1000_disable_multicast_promisc(e1000);
831 nic_report_hw_filtering(nic, -1, 1, -1);
832 break;
833 case NIC_MULTICAST_LIST:
834 e1000_clear_multicast_receive_addresses(e1000);
835 if (addr_cnt > get_free_multicast_address_count(e1000)) {
836 /*
837 * Future work: fill MTA table
838 * Not strictly neccessary, it only saves some compares
839 * in the NIC library.
840 */
841 e1000_enable_multicast_promisc(e1000);
842 nic_report_hw_filtering(nic, -1, 0, -1);
843 } else {
844 e1000_disable_multicast_promisc(e1000);
845 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
846 nic_report_hw_filtering(nic, -1, 1, -1);
847 }
848 break;
849 case NIC_MULTICAST_PROMISC:
850 e1000_enable_multicast_promisc(e1000);
851 e1000_clear_multicast_receive_addresses(e1000);
852 nic_report_hw_filtering(nic, -1, 1, -1);
853 break;
854 default:
855 rc = ENOTSUP;
856 break;
857 }
858
859 fibril_mutex_unlock(&e1000->rx_lock);
860 return rc;
861}
862
863/** Set unicast frames acceptance mode
864 *
865 * @param nic NIC device to update
866 * @param mode Mode to set
867 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
868 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
869 *
870 * @return EOK
871 *
872 */
873static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
874 const nic_address_t *addr, size_t addr_cnt)
875{
876 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
877 int rc = EOK;
878
879 fibril_mutex_lock(&e1000->rx_lock);
880
881 switch (mode) {
882 case NIC_UNICAST_BLOCKED:
883 disable_ra0_address_filter(e1000);
884 e1000_clear_unicast_receive_addresses(e1000);
885 e1000_disable_unicast_promisc(e1000);
886 nic_report_hw_filtering(nic, 1, -1, -1);
887 break;
888 case NIC_UNICAST_DEFAULT:
889 enable_ra0_address_filter(e1000);
890 e1000_clear_unicast_receive_addresses(e1000);
891 e1000_disable_unicast_promisc(e1000);
892 nic_report_hw_filtering(nic, 1, -1, -1);
893 break;
894 case NIC_UNICAST_LIST:
895 enable_ra0_address_filter(e1000);
896 e1000_clear_unicast_receive_addresses(e1000);
897 if (addr_cnt > get_free_unicast_address_count(e1000)) {
898 e1000_enable_unicast_promisc(e1000);
899 nic_report_hw_filtering(nic, 0, -1, -1);
900 } else {
901 e1000_disable_unicast_promisc(e1000);
902 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
903 nic_report_hw_filtering(nic, 1, -1, -1);
904 }
905 break;
906 case NIC_UNICAST_PROMISC:
907 e1000_enable_unicast_promisc(e1000);
908 enable_ra0_address_filter(e1000);
909 e1000_clear_unicast_receive_addresses(e1000);
910 nic_report_hw_filtering(nic, 1, -1, -1);
911 break;
912 default:
913 rc = ENOTSUP;
914 break;
915 }
916
917 fibril_mutex_unlock(&e1000->rx_lock);
918 return rc;
919}
920
921/** Set broadcast frames acceptance mode
922 *
923 * @param nic NIC device to update
924 * @param mode Mode to set
925 *
926 * @return EOK
927 *
928 */
929static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
930{
931 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
932 int rc = EOK;
933
934 fibril_mutex_lock(&e1000->rx_lock);
935
936 switch (mode) {
937 case NIC_BROADCAST_BLOCKED:
938 e1000_disable_broadcast_accept(e1000);
939 break;
940 case NIC_BROADCAST_ACCEPTED:
941 e1000_enable_broadcast_accept(e1000);
942 break;
943 default:
944 rc = ENOTSUP;
945 break;
946 }
947
948 fibril_mutex_unlock(&e1000->rx_lock);
949 return rc;
950}
951
952/** Check if receiving is enabled
953 *
954 * @param e1000 E1000 data structure
955 *
956 * @return true if receiving is enabled
957 *
958 */
959static bool e1000_is_rx_enabled(e1000_t *e1000)
960{
961 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
962 return true;
963
964 return false;
965}
966
967/** Enable receiving
968 *
969 * @param e1000 E1000 data structure
970 *
971 */
972static void e1000_enable_rx(e1000_t *e1000)
973{
974 /* Set Receive Enable Bit */
975 E1000_REG_WRITE(e1000, E1000_RCTL,
976 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
977}
978
979/** Disable receiving
980 *
981 * @param e1000 E1000 data structure
982 *
983 */
984static void e1000_disable_rx(e1000_t *e1000)
985{
986 /* Clear Receive Enable Bit */
987 E1000_REG_WRITE(e1000, E1000_RCTL,
988 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
989}
990
991/** Set VLAN mask
992 *
993 * @param nic NIC device to update
994 * @param vlan_mask VLAN mask
995 *
996 */
997static void e1000_on_vlan_mask_change(nic_t *nic,
998 const nic_vlan_mask_t *vlan_mask)
999{
1000 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1001
1002 fibril_mutex_lock(&e1000->rx_lock);
1003
1004 if (vlan_mask) {
1005 /*
1006 * Disable receiving, so that frame matching
1007 * partially written VLAN is not received.
1008 */
1009 bool rx_enabled = e1000_is_rx_enabled(e1000);
1010 if (rx_enabled)
1011 e1000_disable_rx(e1000);
1012
1013 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1014 uint32_t bitmap_part =
1015 ((uint32_t) vlan_mask->bitmap[i]) |
1016 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1017 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1018 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1019 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1020 }
1021
1022 e1000_enable_vlan_filter(e1000);
1023 if (rx_enabled)
1024 e1000_enable_rx(e1000);
1025 } else
1026 e1000_disable_vlan_filter(e1000);
1027
1028 fibril_mutex_unlock(&e1000->rx_lock);
1029}
1030
1031/** Set VLAN mask
1032 *
1033 * @param device E1000 device
1034 * @param tag VLAN tag
1035 *
1036 * @return EOK
1037 * @return ENOTSUP
1038 *
1039 */
1040static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
1041 bool strip)
1042{
1043 /* VLAN CFI bit cannot be set */
1044 if (tag & VLANTAG_CFI)
1045 return ENOTSUP;
1046
1047 /*
1048 * CTRL.VME is neccessary for both strip and add
1049 * but CTRL.VME means stripping tags on receive.
1050 */
1051 if (!strip && add)
1052 return ENOTSUP;
1053
1054 e1000_t *e1000 = DRIVER_DATA_DEV(device);
1055
1056 e1000->vlan_tag = tag;
1057 e1000->vlan_tag_add = add;
1058
1059 fibril_mutex_lock(&e1000->ctrl_lock);
1060
1061 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1062 if (strip)
1063 ctrl |= CTRL_VME;
1064 else
1065 ctrl &= ~CTRL_VME;
1066
1067 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1068
1069 fibril_mutex_unlock(&e1000->ctrl_lock);
1070 return EOK;
1071}
1072
1073/** Fill receive descriptor with new empty buffer
1074 *
1075 * Store frame in e1000->rx_frame_phys
1076 *
1077 * @param nic NIC data stricture
1078 * @param offset Receive descriptor offset
1079 *
1080 */
1081static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1082{
1083 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1084
1085 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1086 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1087
1088 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1089 rx_descriptor->length = 0;
1090 rx_descriptor->checksum = 0;
1091 rx_descriptor->status = 0;
1092 rx_descriptor->errors = 0;
1093 rx_descriptor->special = 0;
1094}
1095
1096/** Clear receive descriptor
1097 *
1098 * @param e1000 E1000 data
1099 * @param offset Receive descriptor offset
1100 *
1101 */
1102static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1103{
1104 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1105 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1106
1107 rx_descriptor->length = 0;
1108 rx_descriptor->checksum = 0;
1109 rx_descriptor->status = 0;
1110 rx_descriptor->errors = 0;
1111 rx_descriptor->special = 0;
1112}
1113
1114/** Clear receive descriptor
1115 *
1116 * @param nic NIC data
1117 * @param offset Receive descriptor offset
1118 *
1119 */
1120static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1121{
1122 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1123
1124 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1125 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1126
1127 tx_descriptor->phys_addr = 0;
1128 tx_descriptor->length = 0;
1129 tx_descriptor->checksum_offset = 0;
1130 tx_descriptor->command = 0;
1131 tx_descriptor->status = 0;
1132 tx_descriptor->checksum_start_field = 0;
1133 tx_descriptor->special = 0;
1134}
1135
1136/** Increment tail pointer for receive or transmit ring
1137 *
1138 * @param tail Old Tail
1139 * @param descriptors_count Ring length
1140 *
1141 * @return New tail
1142 *
1143 */
1144static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1145{
1146 if (tail + 1 == descriptors_count)
1147 return 0;
1148 else
1149 return tail + 1;
1150}
1151
1152/** Receive frames
1153 *
1154 * @param nic NIC data
1155 *
1156 */
1157static void e1000_receive_frames(nic_t *nic)
1158{
1159 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1160
1161 fibril_mutex_lock(&e1000->rx_lock);
1162
1163 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1164 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1165
1166 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1167 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1168
1169 while (rx_descriptor->status & 0x01) {
1170 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1171
1172 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1173 if (frame != NULL) {
1174 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1175 nic_received_frame(nic, frame);
1176 } else {
1177 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1178 }
1179
1180 e1000_fill_new_rx_descriptor(nic, next_tail);
1181
1182 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1183 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1184
1185 rx_descriptor = (e1000_rx_descriptor_t *)
1186 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1187 }
1188
1189 fibril_mutex_unlock(&e1000->rx_lock);
1190}
1191
1192/** Enable E1000 interupts
1193 *
1194 * @param e1000 E1000 data structure
1195 *
1196 */
1197static void e1000_enable_interrupts(e1000_t *e1000)
1198{
1199 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1200}
1201
1202/** Disable E1000 interupts
1203 *
1204 * @param e1000 E1000 data structure
1205 *
1206 */
1207static void e1000_disable_interrupts(e1000_t *e1000)
1208{
1209 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1210}
1211
1212/** Interrupt handler implementation
1213 *
1214 * This function is called from e1000_interrupt_handler()
1215 * and e1000_poll()
1216 *
1217 * @param nic NIC data
1218 * @param icr ICR register value
1219 *
1220 */
1221static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1222{
1223 if (icr & ICR_RXT0)
1224 e1000_receive_frames(nic);
1225}
1226
1227/** Handle device interrupt
1228 *
1229 * @param dev E1000 device
1230 * @param iid IPC call id
1231 * @param icall IPC call structure
1232 *
1233 */
1234static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1235 ipc_call_t *icall)
1236{
1237 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1238 nic_t *nic = NIC_DATA_DEV(dev);
1239 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1240
1241 e1000_interrupt_handler_impl(nic, icr);
1242 e1000_enable_interrupts(e1000);
1243}
1244
1245/** Register interrupt handler for the card in the system
1246 *
1247 * Note: The global irq_reg_mutex is locked because of work with global
1248 * structure.
1249 *
1250 * @param nic Driver data
1251 *
1252 * @return EOK if the handler was registered
1253 * @return Negative error code otherwise
1254 *
1255 */
1256inline static int e1000_register_int_handler(nic_t *nic)
1257{
1258 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1259
1260 /* Lock the mutex in whole driver while working with global structure */
1261 fibril_mutex_lock(&irq_reg_mutex);
1262
1263 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1264 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1265 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1266
1267 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1268 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1269
1270 fibril_mutex_unlock(&irq_reg_mutex);
1271 return rc;
1272}
1273
1274/** Force receiving all frames in the receive buffer
1275 *
1276 * @param nic NIC data
1277 *
1278 */
1279static void e1000_poll(nic_t *nic)
1280{
1281 assert(nic);
1282
1283 e1000_t *e1000 = nic_get_specific(nic);
1284 assert(e1000);
1285
1286 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1287 e1000_interrupt_handler_impl(nic, icr);
1288}
1289
1290/** Calculates ITR register interrupt from timeval structure
1291 *
1292 * @param period Period
1293 *
1294 */
1295static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1296{
1297 // TODO: use also tv_sec
1298 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1299}
1300
1301/** Set polling mode
1302 *
1303 * @param device Device to set
1304 * @param mode Mode to set
1305 * @param period Period for NIC_POLL_PERIODIC
1306 *
1307 * @return EOK if succeed
1308 * @return ENOTSUP if the mode is not supported
1309 *
1310 */
1311static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1312 const struct timeval *period)
1313{
1314 assert(nic);
1315
1316 e1000_t *e1000 = nic_get_specific(nic);
1317 assert(e1000);
1318
1319 switch (mode) {
1320 case NIC_POLL_IMMEDIATE:
1321 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1322 e1000_enable_interrupts(e1000);
1323 break;
1324 case NIC_POLL_ON_DEMAND:
1325 e1000_disable_interrupts(e1000);
1326 break;
1327 case NIC_POLL_PERIODIC:
1328 assert(period);
1329 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1330 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1331 e1000_enable_interrupts(e1000);
1332 break;
1333 default:
1334 return ENOTSUP;
1335 }
1336
1337 return EOK;
1338}
1339
1340/** Initialize receive registers
1341 *
1342 * @param e1000 E1000 data structure
1343 *
1344 */
1345static void e1000_initialize_rx_registers(e1000_t *e1000)
1346{
1347 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1348 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1349
1350 /* It is not posible to let HW use all descriptors */
1351 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1352
1353 /* Set Broadcast Enable Bit */
1354 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1355}
1356
1357/** Initialize receive structure
1358 *
1359 * @param nic NIC data
1360 *
1361 * @return EOK if succeed
1362 * @return Negative error code otherwise
1363 *
1364 */
1365static int e1000_initialize_rx_structure(nic_t *nic)
1366{
1367 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1368 fibril_mutex_lock(&e1000->rx_lock);
1369
1370 int rc = dmamem_map_anonymous(
1371 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1372 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
1373 &e1000->rx_ring_virt);
1374 if (rc != EOK)
1375 return rc;
1376
1377 E1000_REG_WRITE(e1000, E1000_RDBAH,
1378 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1379 E1000_REG_WRITE(e1000, E1000_RDBAL,
1380 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1381
1382 e1000->rx_frame_phys =
1383 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1384 e1000->rx_frame_virt =
1385 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1386 if (e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {
1387 rc = ENOMEM;
1388 goto error;
1389 }
1390
1391 size_t i;
1392 void *frame_virt;
1393 void *frame_phys;
1394
1395 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1396 rc = dmamem_map_anonymous(
1397 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1398 0, &frame_phys, &frame_virt);
1399 if (rc != EOK)
1400 goto error;
1401
1402 e1000->rx_frame_virt[i] = frame_virt;
1403 e1000->rx_frame_phys[i] = frame_phys;
1404 }
1405
1406 /* Write descriptor */
1407 for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
1408 e1000_fill_new_rx_descriptor(nic, i);
1409
1410 e1000_initialize_rx_registers(e1000);
1411
1412 fibril_mutex_unlock(&e1000->rx_lock);
1413 return EOK;
1414
1415error:
1416 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1417 if (e1000->rx_frame_virt[i] != NULL) {
1418 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1419 e1000->rx_frame_virt[i] = NULL;
1420 e1000->rx_frame_phys[i] = NULL;
1421 }
1422 }
1423
1424 if (e1000->rx_frame_phys != NULL) {
1425 free(e1000->rx_frame_phys);
1426 e1000->rx_frame_phys = NULL;
1427 }
1428
1429 if (e1000->rx_frame_virt != NULL) {
1430 free(e1000->rx_frame_virt);
1431 e1000->rx_frame_phys = NULL;
1432 }
1433
1434 return rc;
1435}
1436
1437/** Uninitialize receive structure
1438 *
1439 * @param nic NIC data
1440 *
1441 */
1442static void e1000_uninitialize_rx_structure(nic_t *nic)
1443{
1444 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1445
1446 /* Write descriptor */
1447 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1448 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1449 e1000->rx_frame_virt[offset] = NULL;
1450 e1000->rx_frame_phys[offset] = NULL;
1451 }
1452
1453 free(e1000->rx_frame_virt);
1454 free(e1000->rx_frame_phys);
1455 e1000->rx_frame_virt = NULL;
1456 e1000->rx_frame_phys = NULL;
1457 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1458}
1459
1460/** Clear receive descriptor ring
1461 *
1462 * @param e1000 E1000 data
1463 *
1464 */
1465static void e1000_clear_rx_ring(e1000_t *e1000)
1466{
1467 /* Write descriptor */
1468 for (unsigned int offset = 0;
1469 offset < E1000_RX_FRAME_COUNT;
1470 offset++)
1471 e1000_clear_rx_descriptor(e1000, offset);
1472}
1473
1474/** Initialize filters
1475 *
1476 * @param e1000 E1000 data
1477 *
1478 */
1479static void e1000_initialize_filters(e1000_t *e1000)
1480{
1481 /* Initialize address filter */
1482 e1000->unicast_ra_count = 0;
1483 e1000->multicast_ra_count = 0;
1484 e1000_clear_unicast_receive_addresses(e1000);
1485}
1486
1487/** Initialize VLAN
1488 *
1489 * @param e1000 E1000 data
1490 *
1491 */
1492static void e1000_initialize_vlan(e1000_t *e1000)
1493{
1494 e1000->vlan_tag_add = false;
1495}
1496
1497/** Fill MAC address from EEPROM to RA[0] register
1498 *
1499 * @param e1000 E1000 data
1500 *
1501 */
1502static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1503{
1504 /* MAC address from eeprom to RA[0] */
1505 nic_address_t address;
1506 e1000_eeprom_get_address(e1000, &address);
1507 e1000_write_receive_address(e1000, 0, &address, true);
1508}
1509
1510/** Initialize other registers
1511 *
1512 * @param dev E1000 data.
1513 *
1514 * @return EOK if succeed
1515 * @return Negative error code otherwise
1516 *
1517 */
1518static void e1000_initialize_registers(e1000_t *e1000)
1519{
1520 E1000_REG_WRITE(e1000, E1000_ITR,
1521 e1000_calculate_itr_interval_from_usecs(
1522 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1523 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1524 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1525 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1526 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1527 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1528 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1529}
1530
1531/** Initialize transmit registers
1532 *
1533 * @param e1000 E1000 data.
1534 *
1535 */
1536static void e1000_initialize_tx_registers(e1000_t *e1000)
1537{
1538 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1539 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1540 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1541
1542 E1000_REG_WRITE(e1000, E1000_TIPG,
1543 10 << TIPG_IPGT_SHIFT |
1544 8 << TIPG_IPGR1_SHIFT |
1545 6 << TIPG_IPGR2_SHIFT);
1546
1547 E1000_REG_WRITE(e1000, E1000_TCTL,
1548 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1549 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1550 TCTL_PSP /* Pad Short Packets */);
1551}
1552
1553/** Initialize transmit structure
1554 *
1555 * @param e1000 E1000 data.
1556 *
1557 */
1558static int e1000_initialize_tx_structure(e1000_t *e1000)
1559{
1560 size_t i;
1561
1562 fibril_mutex_lock(&e1000->tx_lock);
1563
1564 e1000->tx_ring_phys = NULL;
1565 e1000->tx_ring_virt = NULL;
1566 e1000->tx_frame_phys = NULL;
1567 e1000->tx_frame_virt = NULL;
1568
1569 int rc = dmamem_map_anonymous(
1570 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1571 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
1572 &e1000->tx_ring_virt);
1573 if (rc != EOK)
1574 goto error;
1575
1576 bzero(e1000->tx_ring_virt,
1577 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1578
1579 e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1580 e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1581
1582 if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) {
1583 rc = ENOMEM;
1584 goto error;
1585 }
1586
1587 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1588 rc = dmamem_map_anonymous(
1589 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
1590 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1591 if (rc != EOK)
1592 goto error;
1593 }
1594
1595 E1000_REG_WRITE(e1000, E1000_TDBAH,
1596 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1597 E1000_REG_WRITE(e1000, E1000_TDBAL,
1598 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1599
1600 e1000_initialize_tx_registers(e1000);
1601
1602 fibril_mutex_unlock(&e1000->tx_lock);
1603 return EOK;
1604
1605error:
1606 if (e1000->tx_ring_virt != NULL) {
1607 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1608 e1000->tx_ring_virt = NULL;
1609 }
1610
1611 if (e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {
1612 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1613 if (e1000->tx_frame_virt[i] != NULL) {
1614 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1615 e1000->tx_frame_virt[i] = NULL;
1616 e1000->tx_frame_phys[i] = NULL;
1617 }
1618 }
1619 }
1620
1621 if (e1000->tx_frame_phys != NULL) {
1622 free(e1000->tx_frame_phys);
1623 e1000->tx_frame_phys = NULL;
1624 }
1625
1626 if (e1000->tx_frame_virt != NULL) {
1627 free(e1000->tx_frame_virt);
1628 e1000->tx_frame_phys = NULL;
1629 }
1630
1631 return rc;
1632}
1633
1634/** Uninitialize transmit structure
1635 *
1636 * @param nic NIC data
1637 *
1638 */
1639static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1640{
1641 size_t i;
1642
1643 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1644 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1645 e1000->tx_frame_virt[i] = NULL;
1646 e1000->tx_frame_phys[i] = NULL;
1647 }
1648
1649 if (e1000->tx_frame_phys != NULL) {
1650 free(e1000->tx_frame_phys);
1651 e1000->tx_frame_phys = NULL;
1652 }
1653
1654 if (e1000->tx_frame_virt != NULL) {
1655 free(e1000->tx_frame_virt);
1656 e1000->tx_frame_phys = NULL;
1657 }
1658
1659 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1660}
1661
1662/** Clear transmit descriptor ring
1663 *
1664 * @param nic NIC data
1665 *
1666 */
1667static void e1000_clear_tx_ring(nic_t *nic)
1668{
1669 /* Write descriptor */
1670 for (unsigned int offset = 0;
1671 offset < E1000_TX_FRAME_COUNT;
1672 offset++)
1673 e1000_clear_tx_descriptor(nic, offset);
1674}
1675
1676/** Enable transmit
1677 *
1678 * @param e1000 E1000 data
1679 *
1680 */
1681static void e1000_enable_tx(e1000_t *e1000)
1682{
1683 /* Set Transmit Enable Bit */
1684 E1000_REG_WRITE(e1000, E1000_TCTL,
1685 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1686}
1687
1688/** Disable transmit
1689 *
1690 * @param e1000 E1000 data
1691 *
1692 */
1693static void e1000_disable_tx(e1000_t *e1000)
1694{
1695 /* Clear Transmit Enable Bit */
1696 E1000_REG_WRITE(e1000, E1000_TCTL,
1697 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1698}
1699
1700/** Reset E1000 device
1701 *
1702 * @param e1000 The E1000 data
1703 *
1704 */
1705static int e1000_reset(nic_t *nic)
1706{
1707 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1708
1709 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1710
1711 /* Wait for the reset */
1712 usleep(20);
1713
1714 /* check if RST_BIT cleared */
1715 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1716 return EINVAL;
1717
1718 e1000_initialize_registers(e1000);
1719 e1000_initialize_rx_registers(e1000);
1720 e1000_initialize_tx_registers(e1000);
1721 e1000_fill_mac_from_eeprom(e1000);
1722 e1000_initialize_filters(e1000);
1723 e1000_initialize_vlan(e1000);
1724
1725 return EOK;
1726}
1727
1728/** Activate the device to receive and transmit frames
1729 *
1730 * @param nic NIC driver data
1731 *
1732 * @return EOK if activated successfully
1733 * @return Error code otherwise
1734 *
1735 */
1736static int e1000_on_activating(nic_t *nic)
1737{
1738 assert(nic);
1739
1740 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1741
1742 fibril_mutex_lock(&e1000->rx_lock);
1743 fibril_mutex_lock(&e1000->tx_lock);
1744 fibril_mutex_lock(&e1000->ctrl_lock);
1745
1746 e1000_enable_interrupts(e1000);
1747
1748 nic_enable_interrupt(nic, e1000->irq);
1749
1750 e1000_clear_rx_ring(e1000);
1751 e1000_enable_rx(e1000);
1752
1753 e1000_clear_tx_ring(nic);
1754 e1000_enable_tx(e1000);
1755
1756 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1757 ctrl |= CTRL_SLU;
1758 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1759
1760 fibril_mutex_unlock(&e1000->ctrl_lock);
1761 fibril_mutex_unlock(&e1000->tx_lock);
1762 fibril_mutex_unlock(&e1000->rx_lock);
1763
1764 return EOK;
1765}
1766
1767/** Callback for NIC_STATE_DOWN change
1768 *
1769 * @param nic NIC driver data
1770 *
1771 * @return EOK if succeed
1772 * @return Error code otherwise
1773 *
1774 */
1775static int e1000_on_down_unlocked(nic_t *nic)
1776{
1777 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1778
1779 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1780 ctrl &= ~CTRL_SLU;
1781 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1782
1783 e1000_disable_tx(e1000);
1784 e1000_disable_rx(e1000);
1785
1786 nic_disable_interrupt(nic, e1000->irq);
1787 e1000_disable_interrupts(e1000);
1788
1789 /*
1790 * Wait for the for the end of all data
1791 * transfers to descriptors.
1792 */
1793 usleep(100);
1794
1795 return EOK;
1796}
1797
1798/** Callback for NIC_STATE_DOWN change
1799 *
1800 * @param nic NIC driver data
1801 *
1802 * @return EOK if succeed
1803 * @return Error code otherwise
1804 *
1805 */
1806static int e1000_on_down(nic_t *nic)
1807{
1808 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1809
1810 fibril_mutex_lock(&e1000->rx_lock);
1811 fibril_mutex_lock(&e1000->tx_lock);
1812 fibril_mutex_lock(&e1000->ctrl_lock);
1813
1814 int rc = e1000_on_down_unlocked(nic);
1815
1816 fibril_mutex_unlock(&e1000->ctrl_lock);
1817 fibril_mutex_unlock(&e1000->tx_lock);
1818 fibril_mutex_unlock(&e1000->rx_lock);
1819
1820 return rc;
1821}
1822
1823/** Callback for NIC_STATE_STOPPED change
1824 *
1825 * @param nic NIC driver data
1826 *
1827 * @return EOK if succeed
1828 * @return Error code otherwise
1829 *
1830 */
1831static int e1000_on_stopping(nic_t *nic)
1832{
1833 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1834
1835 fibril_mutex_lock(&e1000->rx_lock);
1836 fibril_mutex_lock(&e1000->tx_lock);
1837 fibril_mutex_lock(&e1000->ctrl_lock);
1838
1839 int rc = e1000_on_down_unlocked(nic);
1840 if (rc == EOK)
1841 rc = e1000_reset(nic);
1842
1843 fibril_mutex_unlock(&e1000->ctrl_lock);
1844 fibril_mutex_unlock(&e1000->tx_lock);
1845 fibril_mutex_unlock(&e1000->rx_lock);
1846
1847 return rc;
1848}
1849
1850/** Create driver data structure
1851 *
1852 * @return Intialized device data structure or NULL
1853 *
1854 */
1855static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1856{
1857 assert(dev);
1858 assert(!dev->driver_data);
1859
1860 nic_t *nic = nic_create_and_bind(dev);
1861 if (!nic)
1862 return NULL;
1863
1864 e1000_t *e1000 = malloc(sizeof(e1000_t));
1865 if (!e1000) {
1866 nic_unbind_and_destroy(dev);
1867 return NULL;
1868 }
1869
1870 bzero(e1000, sizeof(e1000_t));
1871
1872 nic_set_specific(nic, e1000);
1873 nic_set_send_frame_handler(nic, e1000_send_frame);
1874 nic_set_state_change_handlers(nic, e1000_on_activating,
1875 e1000_on_down, e1000_on_stopping);
1876 nic_set_filtering_change_handlers(nic,
1877 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1878 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1879 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1880
1881 fibril_mutex_initialize(&e1000->ctrl_lock);
1882 fibril_mutex_initialize(&e1000->rx_lock);
1883 fibril_mutex_initialize(&e1000->tx_lock);
1884 fibril_mutex_initialize(&e1000->eeprom_lock);
1885
1886 return e1000;
1887}
1888
1889/** Delete driver data structure
1890 *
1891 * @param data E1000 device data structure
1892 *
1893 */
1894inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1895{
1896 assert(dev);
1897
1898 if (dev->driver_data != NULL)
1899 nic_unbind_and_destroy(dev);
1900}
1901
1902/** Clean up the E1000 device structure.
1903 *
1904 * @param dev Device structure.
1905 *
1906 */
1907static void e1000_dev_cleanup(ddf_dev_t *dev)
1908{
1909 assert(dev);
1910
1911 e1000_delete_dev_data(dev);
1912
1913 if (dev->parent_sess != NULL) {
1914 async_hangup(dev->parent_sess);
1915 dev->parent_sess = NULL;
1916 }
1917}
1918
1919/** Fill the irq and io_addr part of device data structure
1920 *
1921 * The hw_resources must be obtained before calling this function
1922 *
1923 * @param dev Device structure
1924 * @param hw_resources Hardware resources obtained from the parent device
1925 *
1926 * @return EOK if succeed
1927 * @return Negative error code otherwise
1928 *
1929 */
1930static int e1000_fill_resource_info(ddf_dev_t *dev,
1931 const hw_res_list_parsed_t *hw_resources)
1932{
1933 assert(dev != NULL);
1934 assert(hw_resources != NULL);
1935 assert(dev->driver_data != NULL);
1936
1937 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1938
1939 if (hw_resources->irqs.count != 1)
1940 return EINVAL;
1941
1942 e1000->irq = hw_resources->irqs.irqs[0];
1943 e1000->reg_base_phys =
1944 MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
1945
1946 return EOK;
1947}
1948
1949/** Obtain information about hardware resources of the device
1950 *
1951 * The device must be connected to the parent
1952 *
1953 * @param dev Device structure
1954 *
1955 * @return EOK if succeed
1956 * @return Negative error code otherwise
1957 *
1958 */
1959static int e1000_get_resource_info(ddf_dev_t *dev)
1960{
1961 assert(dev != NULL);
1962 assert(NIC_DATA_DEV(dev) != NULL);
1963
1964 hw_res_list_parsed_t hw_res_parsed;
1965 hw_res_list_parsed_init(&hw_res_parsed);
1966
1967 /* Get hw resources form parent driver */
1968 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1969 if (rc != EOK)
1970 return rc;
1971
1972 /* Fill resources information to the device */
1973 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1974 hw_res_list_parsed_clean(&hw_res_parsed);
1975
1976 return rc;
1977}
1978
1979/** Initialize the E1000 device structure
1980 *
1981 * @param dev Device information
1982 *
1983 * @return EOK if succeed
1984 * @return Negative error code otherwise
1985 *
1986 */
1987static int e1000_device_initialize(ddf_dev_t *dev)
1988{
1989 /* Allocate driver data for the device. */
1990 e1000_t *e1000 = e1000_create_dev_data(dev);
1991 if (e1000 == NULL) {
1992 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1993 return ENOMEM;
1994 }
1995
1996 /* Obtain and fill hardware resources info */
1997 int rc = e1000_get_resource_info(dev);
1998 if (rc != EOK) {
1999 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2000 e1000_dev_cleanup(dev);
2001 return rc;
2002 }
2003
2004 uint16_t device_id;
2005 rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
2006 &device_id);
2007 if (rc != EOK) {
2008 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2009 e1000_dev_cleanup(dev);
2010 return rc;
2011 }
2012
2013 e1000_board_t board;
2014 switch (device_id) {
2015 case 0x100e:
2016 case 0x1015:
2017 case 0x1016:
2018 case 0x1017:
2019 board = E1000_82540;
2020 break;
2021 case 0x1013:
2022 case 0x1018:
2023 case 0x1078:
2024 board = E1000_82541;
2025 break;
2026 case 0x1076:
2027 case 0x1077:
2028 case 0x107c:
2029 board = E1000_82541REV2;
2030 break;
2031 case 0x100f:
2032 case 0x1011:
2033 case 0x1026:
2034 case 0x1027:
2035 case 0x1028:
2036 board = E1000_82545;
2037 break;
2038 case 0x1010:
2039 case 0x1012:
2040 case 0x101d:
2041 case 0x1079:
2042 case 0x107a:
2043 case 0x107b:
2044 board = E1000_82546;
2045 break;
2046 case 0x1019:
2047 case 0x101a:
2048 board = E1000_82547;
2049 break;
2050 case 0x10b9:
2051 board = E1000_82572;
2052 break;
2053 case 0x1096:
2054 board = E1000_80003ES2;
2055 break;
2056 default:
2057 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2058 device_id);
2059 e1000_dev_cleanup(dev);
2060 return ENOTSUP;
2061 }
2062
2063 switch (board) {
2064 case E1000_82540:
2065 case E1000_82541:
2066 case E1000_82541REV2:
2067 case E1000_82545:
2068 case E1000_82546:
2069 e1000->info.eerd_start = 0x01;
2070 e1000->info.eerd_done = 0x10;
2071 e1000->info.eerd_address_offset = 8;
2072 e1000->info.eerd_data_offset = 16;
2073 break;
2074 case E1000_82547:
2075 case E1000_82572:
2076 case E1000_80003ES2:
2077 e1000->info.eerd_start = 0x01;
2078 e1000->info.eerd_done = 0x02;
2079 e1000->info.eerd_address_offset = 2;
2080 e1000->info.eerd_data_offset = 16;
2081 break;
2082 }
2083
2084 return EOK;
2085}
2086
2087/** Enable the I/O ports of the device.
2088 *
2089 * @param dev E1000 device.
2090 *
2091 * @return EOK if successed
2092 * @return Negative error code otherwise
2093 *
2094 */
2095static int e1000_pio_enable(ddf_dev_t *dev)
2096{
2097 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2098
2099 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2100 &e1000->reg_base_virt);
2101 if (rc != EOK)
2102 return EADDRNOTAVAIL;
2103
2104 return EOK;
2105}
2106
2107/** Probe and initialize the newly added device.
2108 *
2109 * @param dev E1000 device.
2110 *
2111 */
2112int e1000_dev_add(ddf_dev_t *dev)
2113{
2114 ddf_fun_t *fun;
2115 assert(dev);
2116
2117 /* Initialize device structure for E1000 */
2118 int rc = e1000_device_initialize(dev);
2119 if (rc != EOK)
2120 return rc;
2121
2122 /* Device initialization */
2123 nic_t *nic = dev->driver_data;
2124 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2125
2126 /* Map registers */
2127 rc = e1000_pio_enable(dev);
2128 if (rc != EOK)
2129 goto err_destroy;
2130
2131 e1000_initialize_registers(e1000);
2132 rc = e1000_initialize_tx_structure(e1000);
2133 if (rc != EOK)
2134 goto err_pio;
2135
2136 fibril_mutex_lock(&e1000->rx_lock);
2137
2138 e1000_fill_mac_from_eeprom(e1000);
2139 e1000_initialize_filters(e1000);
2140
2141 fibril_mutex_unlock(&e1000->rx_lock);
2142
2143 e1000_initialize_vlan(e1000);
2144
2145 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2146 if (fun == NULL)
2147 goto err_tx_structure;
2148 nic_set_ddf_fun(nic, fun);
2149 fun->ops = &e1000_dev_ops;
2150 fun->driver_data = nic;
2151
2152 rc = e1000_register_int_handler(nic);
2153 if (rc != EOK)
2154 goto err_fun_create;
2155
2156 rc = nic_connect_to_services(nic);
2157 if (rc != EOK)
2158 goto err_irq;
2159
2160 rc = e1000_initialize_rx_structure(nic);
2161 if (rc != EOK)
2162 goto err_irq;
2163
2164 nic_address_t e1000_address;
2165 e1000_get_address(e1000, &e1000_address);
2166 rc = nic_report_address(nic, &e1000_address);
2167 if (rc != EOK)
2168 goto err_rx_structure;
2169
2170 struct timeval period;
2171 period.tv_sec = 0;
2172 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2173 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2174 if (rc != EOK)
2175 goto err_rx_structure;
2176
2177 rc = ddf_fun_bind(fun);
2178 if (rc != EOK)
2179 goto err_fun_bind;
2180
2181 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2182 if (rc != EOK)
2183 goto err_add_to_cat;
2184
2185 return EOK;
2186
2187err_add_to_cat:
2188 ddf_fun_unbind(fun);
2189err_fun_bind:
2190err_rx_structure:
2191 e1000_uninitialize_rx_structure(nic);
2192err_irq:
2193 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2194err_fun_create:
2195 ddf_fun_destroy(fun);
2196 nic_set_ddf_fun(nic, NULL);
2197err_tx_structure:
2198 e1000_uninitialize_tx_structure(e1000);
2199err_pio:
2200 // TODO: e1000_pio_disable(dev);
2201err_destroy:
2202 e1000_dev_cleanup(dev);
2203 return rc;
2204}
2205
2206/** Read 16-bit value from EEPROM of E1000 adapter
2207 *
2208 * Read using the EERD register.
2209 *
2210 * @param device E1000 device
2211 * @param eeprom_address 8-bit EEPROM address
2212 *
2213 * @return 16-bit value from EEPROM
2214 *
2215 */
2216static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2217{
2218 fibril_mutex_lock(&e1000->eeprom_lock);
2219
2220 /* Write address and START bit to EERD register */
2221 uint32_t write_data = e1000->info.eerd_start |
2222 (((uint32_t) eeprom_address) <<
2223 e1000->info.eerd_address_offset);
2224 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2225
2226 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2227 while ((eerd & e1000->info.eerd_done) == 0) {
2228 usleep(1);
2229 eerd = E1000_REG_READ(e1000, E1000_EERD);
2230 }
2231
2232 fibril_mutex_unlock(&e1000->eeprom_lock);
2233
2234 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2235}
2236
2237/** Get MAC address of the E1000 adapter
2238 *
2239 * @param device E1000 device
2240 * @param address Place to store the address
2241 * @param max_len Maximal addresss length to store
2242 *
2243 * @return EOK if succeed
2244 * @return Negative error code otherwise
2245 *
2246 */
2247static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2248{
2249 fibril_mutex_lock(&e1000->rx_lock);
2250
2251 uint8_t *mac0_dest = (uint8_t *) address->address;
2252 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2253 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2254 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2255 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2256 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2257
2258 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2259 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2260
2261 *mac0_dest = (uint8_t) ral;
2262 *mac1_dest = (uint8_t) (ral >> 8);
2263 *mac2_dest = (uint8_t) (ral >> 16);
2264 *mac3_dest = (uint8_t) (ral >> 24);
2265 *mac4_dest = (uint8_t) rah;
2266 *mac5_dest = (uint8_t) (rah >> 8);
2267
2268 fibril_mutex_unlock(&e1000->rx_lock);
2269 return EOK;
2270};
2271
2272/** Set card MAC address
2273 *
2274 * @param device E1000 device
2275 * @param address Address
2276 *
2277 * @return EOK if succeed
2278 * @return Negative error code otherwise
2279 */
2280static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
2281{
2282 nic_t *nic = NIC_DATA_DEV(dev);
2283 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2284
2285 fibril_mutex_lock(&e1000->rx_lock);
2286 fibril_mutex_lock(&e1000->tx_lock);
2287
2288 int rc = nic_report_address(nic, addr);
2289 if (rc == EOK)
2290 e1000_write_receive_address(e1000, 0, addr, false);
2291
2292 fibril_mutex_unlock(&e1000->tx_lock);
2293 fibril_mutex_unlock(&e1000->rx_lock);
2294
2295 return rc;
2296}
2297
2298static void e1000_eeprom_get_address(e1000_t *e1000,
2299 nic_address_t *address)
2300{
2301 uint16_t *mac0_dest = (uint16_t *) address->address;
2302 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2303 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2304
2305 *mac0_dest = e1000_eeprom_read(e1000, 0);
2306 *mac2_dest = e1000_eeprom_read(e1000, 1);
2307 *mac4_dest = e1000_eeprom_read(e1000, 2);
2308}
2309
2310/** Send frame
2311 *
2312 * @param nic NIC driver data structure
2313 * @param data Frame data
2314 * @param size Frame size in bytes
2315 *
2316 * @return EOK if succeed
2317 * @return Error code in the case of error
2318 *
2319 */
2320static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2321{
2322 assert(nic);
2323
2324 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2325 fibril_mutex_lock(&e1000->tx_lock);
2326
2327 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2328 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2329 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2330
2331 bool descriptor_available = false;
2332
2333 /* Descriptor never used */
2334 if (tx_descriptor_addr->length == 0)
2335 descriptor_available = true;
2336
2337 /* Descriptor done */
2338 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2339 descriptor_available = true;
2340
2341 if (!descriptor_available) {
2342 /* Frame lost */
2343 fibril_mutex_unlock(&e1000->tx_lock);
2344 return;
2345 }
2346
2347 memcpy(e1000->tx_frame_virt[tdt], data, size);
2348
2349 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2350 tx_descriptor_addr->length = size;
2351
2352 /*
2353 * Report status to STATUS.DD (descriptor done),
2354 * add ethernet CRC, end of packet.
2355 */
2356 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2357 TXDESCRIPTOR_COMMAND_IFCS |
2358 TXDESCRIPTOR_COMMAND_EOP;
2359
2360 tx_descriptor_addr->checksum_offset = 0;
2361 tx_descriptor_addr->status = 0;
2362 if (e1000->vlan_tag_add) {
2363 tx_descriptor_addr->special = e1000->vlan_tag;
2364 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2365 } else
2366 tx_descriptor_addr->special = 0;
2367
2368 tx_descriptor_addr->checksum_start_field = 0;
2369
2370 tdt++;
2371 if (tdt == E1000_TX_FRAME_COUNT)
2372 tdt = 0;
2373
2374 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2375
2376 fibril_mutex_unlock(&e1000->tx_lock);
2377}
2378
2379int main(void)
2380{
2381 int rc = nic_driver_init(NAME);
2382 if (rc != EOK)
2383 return rc;
2384
2385 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2386 &e1000_nic_iface);
2387
2388 ddf_log_init(NAME, LVL_ERROR);
2389 ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
2390 return ddf_driver_main(&e1000_driver);
2391}
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