source: mainline/uspace/drv/nic/e1k/e1k.c@ ad5f149

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ad5f149 was 7de1988c, checked in by Jakub Jermar <jakub@…>, 12 years ago

Adapt drivers using parsed HW resources to use the new interface.
  • Property mode set to 100644
File size: 55.7 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35/* XXX Fix this */
36#define _DDF_DATA_IMPLANT
37
38#include <assert.h>
39#include <stdio.h>
40#include <errno.h>
41#include <adt/list.h>
42#include <align.h>
43#include <byteorder.h>
44#include <sysinfo.h>
45#include <ipc/irc.h>
46#include <ipc/ns.h>
47#include <ddi.h>
48#include <as.h>
49#include <ddf/log.h>
50#include <ddf/interrupt.h>
51#include <device/hw_res_parsed.h>
52#include <device/pci.h>
53#include <nic.h>
54#include <ops/nic.h>
55#include "e1k.h"
56
57#define NAME "e1k"
58
59#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
60
61/* Must be power of 8 */
62#define E1000_RX_FRAME_COUNT 128
63#define E1000_TX_FRAME_COUNT 128
64
65#define E1000_RECEIVE_ADDRESS 16
66
67/** Maximum sending frame size */
68#define E1000_MAX_SEND_FRAME_SIZE 2048
69/** Maximum receiving frame size */
70#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
71
72/** nic_driver_data_t* -> e1000_t* cast */
73#define DRIVER_DATA_NIC(nic) \
74 ((e1000_t *) nic_get_specific(nic))
75
76/** ddf_fun_t * -> nic_driver_data_t* cast */
77#define NIC_DATA_FUN(fun) \
78 ((nic_t *) ddf_fun_data_get(fun))
79
80/** ddf_dev_t * -> nic_driver_data_t* cast */
81#define NIC_DATA_DEV(dev) \
82 ((nic_t *) ddf_dev_data_get(dev))
83
84/** ddf_dev_t * -> e1000_t* cast */
85#define DRIVER_DATA_DEV(dev) \
86 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
87
88/** ddf_fun_t * -> e1000_t* cast */
89#define DRIVER_DATA_FUN(fun) \
90 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
91
92/** Cast pointer to uint64_t
93 *
94 * @param ptr Pointer to cast
95 *
96 * @return The uint64_t pointer representation.
97 *
98 */
99#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
100
101/** Cast the memaddr part to the void*
102 *
103 * @param memaddr The memaddr value
104 *
105 */
106#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
107
108#define E1000_REG_BASE(e1000) \
109 ((e1000)->reg_base_virt)
110
111#define E1000_REG_ADDR(e1000, reg) \
112 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
113
114#define E1000_REG_READ(e1000, reg) \
115 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
116
117#define E1000_REG_WRITE(e1000, reg, value) \
118 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
119
120/** E1000 device data */
121typedef struct {
122 /** Device configuration */
123 e1000_info_t info;
124
125 /** Physical registers base address */
126 void *reg_base_phys;
127 /** Virtual registers base address */
128 void *reg_base_virt;
129
130 /** Physical tx ring address */
131 uintptr_t tx_ring_phys;
132 /** Virtual tx ring address */
133 void *tx_ring_virt;
134
135 /** Ring of TX frames, physical address */
136 uintptr_t *tx_frame_phys;
137 /** Ring of TX frames, virtual address */
138 void **tx_frame_virt;
139
140 /** Physical rx ring address */
141 uintptr_t rx_ring_phys;
142 /** Virtual rx ring address */
143 void *rx_ring_virt;
144
145 /** Ring of RX frames, physical address */
146 uintptr_t *rx_frame_phys;
147 /** Ring of RX frames, virtual address */
148 void **rx_frame_virt;
149
150 /** VLAN tag */
151 uint16_t vlan_tag;
152
153 /** Add VLAN tag to frame */
154 bool vlan_tag_add;
155
156 /** Used unicast Receive Address count */
157 unsigned int unicast_ra_count;
158
159 /** Used milticast Receive addrress count */
160 unsigned int multicast_ra_count;
161
162 /** The irq assigned */
163 int irq;
164
165 /** Lock for CTRL register */
166 fibril_mutex_t ctrl_lock;
167
168 /** Lock for receiver */
169 fibril_mutex_t rx_lock;
170
171 /** Lock for transmitter */
172 fibril_mutex_t tx_lock;
173
174 /** Lock for EEPROM access */
175 fibril_mutex_t eeprom_lock;
176} e1000_t;
177
178/** Global mutex for work with shared irq structure */
179FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
180
181static int e1000_get_address(e1000_t *, nic_address_t *);
182static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
183static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
184
185static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
186static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
187
188static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
189static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
190static int e1000_get_operation_mode(ddf_fun_t *, int *,
191 nic_channel_mode_t *, nic_role_t *);
192static int e1000_set_operation_mode(ddf_fun_t *, int,
193 nic_channel_mode_t, nic_role_t);
194static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
195static int e1000_autoneg_disable(ddf_fun_t *);
196static int e1000_autoneg_restart(ddf_fun_t *);
197
198static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
199
200/** Network interface options for E1000 card driver */
201static nic_iface_t e1000_nic_iface;
202
203/** Network interface options for E1000 card driver */
204static nic_iface_t e1000_nic_iface = {
205 .set_address = &e1000_set_addr,
206 .get_device_info = &e1000_get_device_info,
207 .get_cable_state = &e1000_get_cable_state,
208 .get_operation_mode = &e1000_get_operation_mode,
209 .set_operation_mode = &e1000_set_operation_mode,
210 .autoneg_enable = &e1000_autoneg_enable,
211 .autoneg_disable = &e1000_autoneg_disable,
212 .autoneg_restart = &e1000_autoneg_restart,
213 .vlan_set_tag = &e1000_vlan_set_tag,
214 .defective_get_mode = &e1000_defective_get_mode,
215 .defective_set_mode = &e1000_defective_set_mode,
216};
217
218/** Basic device operations for E1000 driver */
219static ddf_dev_ops_t e1000_dev_ops;
220
221static int e1000_dev_add(ddf_dev_t *);
222
223/** Basic driver operations for E1000 driver */
224static driver_ops_t e1000_driver_ops = {
225 .dev_add = e1000_dev_add
226};
227
228/** Driver structure for E1000 driver */
229static driver_t e1000_driver = {
230 .name = NAME,
231 .driver_ops = &e1000_driver_ops
232};
233
234/* The default implementation callbacks */
235static int e1000_on_activating(nic_t *);
236static int e1000_on_stopping(nic_t *);
237static void e1000_send_frame(nic_t *, void *, size_t);
238
239/** PIO ranges used in the IRQ code. */
240irq_pio_range_t e1000_irq_pio_ranges[] = {
241 {
242 .base = 0,
243 .size = PAGE_SIZE, /* XXX */
244 }
245};
246
247/** Commands to deal with interrupt
248 *
249 */
250irq_cmd_t e1000_irq_commands[] = {
251 {
252 /* Get the interrupt status */
253 .cmd = CMD_PIO_READ_32,
254 .addr = NULL,
255 .dstarg = 2
256 },
257 {
258 .cmd = CMD_PREDICATE,
259 .value = 2,
260 .srcarg = 2
261 },
262 {
263 /* Disable interrupts until interrupt routine is finished */
264 .cmd = CMD_PIO_WRITE_32,
265 .addr = NULL,
266 .value = 0xffffffff
267 },
268 {
269 .cmd = CMD_ACCEPT
270 }
271};
272
273/** Interrupt code definition */
274irq_code_t e1000_irq_code = {
275 .rangecount = sizeof(e1000_irq_pio_ranges) /
276 sizeof(irq_pio_range_t),
277 .ranges = e1000_irq_pio_ranges,
278 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
279 .cmds = e1000_irq_commands
280};
281
282/** Get the device information
283 *
284 * @param dev NIC device
285 * @param info Information to fill
286 *
287 * @return EOK
288 *
289 */
290static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
291{
292 assert(dev);
293 assert(info);
294
295 memset(info, 0, sizeof(nic_device_info_t));
296
297 info->vendor_id = 0x8086;
298 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
299 "Intel Corporation");
300 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
301 "Intel Pro");
302
303 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
304 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
305 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
306
307 return EOK;
308}
309
310/** Check the cable state
311 *
312 * @param[in] dev device
313 * @param[out] state state to fill
314 *
315 * @return EOK
316 *
317 */
318static int e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
319{
320 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
321 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
322 *state = NIC_CS_PLUGGED;
323 else
324 *state = NIC_CS_UNPLUGGED;
325
326 return EOK;
327}
328
329static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
330{
331 return useconds * 4;
332}
333
334/** Get operation mode of the device
335 *
336 */
337static int e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
338 nic_channel_mode_t *duplex, nic_role_t *role)
339{
340 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
341 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
342
343 if (status & STATUS_FD)
344 *duplex = NIC_CM_FULL_DUPLEX;
345 else
346 *duplex = NIC_CM_HALF_DUPLEX;
347
348 uint32_t speed_bits =
349 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
350
351 if (speed_bits == STATUS_SPEED_10)
352 *speed = 10;
353 else if (speed_bits == STATUS_SPEED_100)
354 *speed = 100;
355 else if ((speed_bits == STATUS_SPEED_1000A) ||
356 (speed_bits == STATUS_SPEED_1000B))
357 *speed = 1000;
358
359 *role = NIC_ROLE_UNKNOWN;
360 return EOK;
361}
362
363static void e1000_link_restart(e1000_t *e1000)
364{
365 fibril_mutex_lock(&e1000->ctrl_lock);
366
367 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
368
369 if (ctrl & CTRL_SLU) {
370 ctrl &= ~(CTRL_SLU);
371 fibril_mutex_unlock(&e1000->ctrl_lock);
372 usleep(10);
373 fibril_mutex_lock(&e1000->ctrl_lock);
374 ctrl |= CTRL_SLU;
375 }
376
377 fibril_mutex_unlock(&e1000->ctrl_lock);
378
379 e1000_link_restart(e1000);
380}
381
382/** Set operation mode of the device
383 *
384 */
385static int e1000_set_operation_mode(ddf_fun_t *fun, int speed,
386 nic_channel_mode_t duplex, nic_role_t role)
387{
388 if ((speed != 10) && (speed != 100) && (speed != 1000))
389 return EINVAL;
390
391 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
392 return EINVAL;
393
394 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
395
396 fibril_mutex_lock(&e1000->ctrl_lock);
397 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
398
399 ctrl |= CTRL_FRCSPD;
400 ctrl |= CTRL_FRCDPLX;
401 ctrl &= ~(CTRL_ASDE);
402
403 if (duplex == NIC_CM_FULL_DUPLEX)
404 ctrl |= CTRL_FD;
405 else
406 ctrl &= ~(CTRL_FD);
407
408 ctrl &= ~(CTRL_SPEED_MASK);
409 if (speed == 1000)
410 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
411 else if (speed == 100)
412 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
413 else
414 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
415
416 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
417
418 fibril_mutex_unlock(&e1000->ctrl_lock);
419
420 e1000_link_restart(e1000);
421
422 return EOK;
423}
424
425/** Enable auto-negotiation
426 *
427 * @param dev Device to update
428 * @param advertisement Ignored on E1000
429 *
430 * @return EOK if advertisement mode set successfully
431 *
432 */
433static int e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
434{
435 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
436
437 fibril_mutex_lock(&e1000->ctrl_lock);
438
439 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
440
441 ctrl &= ~(CTRL_FRCSPD);
442 ctrl &= ~(CTRL_FRCDPLX);
443 ctrl |= CTRL_ASDE;
444
445 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
446
447 fibril_mutex_unlock(&e1000->ctrl_lock);
448
449 e1000_link_restart(e1000);
450
451 return EOK;
452}
453
454/** Disable auto-negotiation
455 *
456 * @param dev Device to update
457 *
458 * @return EOK
459 *
460 */
461static int e1000_autoneg_disable(ddf_fun_t *fun)
462{
463 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
464
465 fibril_mutex_lock(&e1000->ctrl_lock);
466
467 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
468
469 ctrl |= CTRL_FRCSPD;
470 ctrl |= CTRL_FRCDPLX;
471 ctrl &= ~(CTRL_ASDE);
472
473 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
474
475 fibril_mutex_unlock(&e1000->ctrl_lock);
476
477 e1000_link_restart(e1000);
478
479 return EOK;
480}
481
482/** Restart auto-negotiation
483 *
484 * @param dev Device to update
485 *
486 * @return EOK if advertisement mode set successfully
487 *
488 */
489static int e1000_autoneg_restart(ddf_fun_t *dev)
490{
491 return e1000_autoneg_enable(dev, 0);
492}
493
494/** Get state of acceptance of weird frames
495 *
496 * @param device Device to check
497 * @param[out] mode Current mode
498 *
499 */
500static int e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
501{
502 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
503
504 *mode = 0;
505 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
506 if (rctl & RCTL_SBP)
507 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
508
509 return EOK;
510};
511
512/** Set acceptance of weird frames
513 *
514 * @param device Device to update
515 * @param mode Mode to set
516 *
517 * @return ENOTSUP if the mode is not supported
518 * @return EOK of mode was set
519 *
520 */
521static int e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
522{
523 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
524 int rc = EOK;
525
526 fibril_mutex_lock(&e1000->rx_lock);
527
528 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
529 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
530 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
531
532 if (short_mode && bad_mode)
533 rctl |= RCTL_SBP;
534 else if ((!short_mode) && (!bad_mode))
535 rctl &= ~RCTL_SBP;
536 else
537 rc = ENOTSUP;
538
539 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
540
541 fibril_mutex_unlock(&e1000->rx_lock);
542 return rc;
543};
544
545/** Write receive address to RA registr
546 *
547 * @param e1000 E1000 data structure
548 * @param position RA register position
549 * @param address Ethernet address
550 * @param set_av_bit Set the Addtess Valid bit
551 *
552 */
553static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
554 const nic_address_t * address, bool set_av_bit)
555{
556 uint8_t *mac0 = (uint8_t *) address->address;
557 uint8_t *mac1 = (uint8_t *) address->address + 1;
558 uint8_t *mac2 = (uint8_t *) address->address + 2;
559 uint8_t *mac3 = (uint8_t *) address->address + 3;
560 uint8_t *mac4 = (uint8_t *) address->address + 4;
561 uint8_t *mac5 = (uint8_t *) address->address + 5;
562
563 uint32_t rah;
564 uint32_t ral;
565
566 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
567 rah = ((*mac5) << 8) | ((*mac4));
568
569 if (set_av_bit)
570 rah |= RAH_AV;
571 else
572 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
573
574 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
575 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
576}
577
578/** Disable receive address in RA registr
579 *
580 * Clear Address Valid bit
581 *
582 * @param e1000 E1000 data structure
583 * @param position RA register position
584 *
585 */
586static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
587{
588 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
589 rah = rah & ~RAH_AV;
590 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
591}
592
593/** Clear all unicast addresses from RA registers
594 *
595 * @param e1000 E1000 data structure
596 *
597 */
598static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
599{
600 for (unsigned int ra_num = 1;
601 ra_num <= e1000->unicast_ra_count;
602 ra_num++)
603 e1000_disable_receive_address(e1000, ra_num);
604
605 e1000->unicast_ra_count = 0;
606}
607
608/** Clear all multicast addresses from RA registers
609 *
610 * @param e1000 E1000 data structure
611 *
612 */
613static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
614{
615 unsigned int first_multicast_ra_num =
616 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
617
618 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
619 ra_num >= first_multicast_ra_num;
620 ra_num--)
621 e1000_disable_receive_address(e1000, ra_num);
622
623 e1000->multicast_ra_count = 0;
624}
625
626/** Return receive address filter positions count usable for unicast
627 *
628 * @param e1000 E1000 data structure
629 *
630 * @return receive address filter positions count usable for unicast
631 *
632 */
633static unsigned int get_free_unicast_address_count(e1000_t *e1000)
634{
635 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
636}
637
638/** Return receive address filter positions count usable for multicast
639 *
640 * @param e1000 E1000 data structure
641 *
642 * @return receive address filter positions count usable for multicast
643 *
644 */
645static unsigned int get_free_multicast_address_count(e1000_t *e1000)
646{
647 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
648}
649
650/** Write unicast receive addresses to receive address filter registers
651 *
652 * @param e1000 E1000 data structure
653 * @param addr Pointer to address array
654 * @param addr_cnt Address array count
655 *
656 */
657static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
658 const nic_address_t *addr, size_t addr_cnt)
659{
660 assert(addr_cnt <= get_free_unicast_address_count(e1000));
661
662 nic_address_t *addr_iterator = (nic_address_t *) addr;
663
664 /* ra_num = 0 is primary address */
665 for (unsigned int ra_num = 1;
666 ra_num <= addr_cnt;
667 ra_num++) {
668 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
669 addr_iterator++;
670 }
671}
672
673/** Write multicast receive addresses to receive address filter registers
674 *
675 * @param e1000 E1000 data structure
676 * @param addr Pointer to address array
677 * @param addr_cnt Address array count
678 *
679 */
680static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
681 const nic_address_t *addr, size_t addr_cnt)
682{
683 assert(addr_cnt <= get_free_multicast_address_count(e1000));
684
685 nic_address_t *addr_iterator = (nic_address_t *) addr;
686
687 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
688 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
689 ra_num >= first_multicast_ra_num;
690 ra_num--) {
691 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
692 addr_iterator++;
693 }
694}
695
696/** Disable receiving frames for default address
697 *
698 * @param e1000 E1000 data structure
699 *
700 */
701static void disable_ra0_address_filter(e1000_t *e1000)
702{
703 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
704 rah0 = rah0 & ~RAH_AV;
705 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
706}
707
708/** Enable receiving frames for default address
709 *
710 * @param e1000 E1000 data structure
711 *
712 */
713static void enable_ra0_address_filter(e1000_t *e1000)
714{
715 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
716 rah0 = rah0 | RAH_AV;
717 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
718}
719
720/** Disable unicast promiscuous mode
721 *
722 * @param e1000 E1000 data structure
723 *
724 */
725static void e1000_disable_unicast_promisc(e1000_t *e1000)
726{
727 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
728 rctl = rctl & ~RCTL_UPE;
729 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
730}
731
732/** Enable unicast promiscuous mode
733 *
734 * @param e1000 E1000 data structure
735 *
736 */
737static void e1000_enable_unicast_promisc(e1000_t *e1000)
738{
739 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
740 rctl = rctl | RCTL_UPE;
741 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
742}
743
744/** Disable multicast promiscuous mode
745 *
746 * @param e1000 E1000 data structure
747 *
748 */
749static void e1000_disable_multicast_promisc(e1000_t *e1000)
750{
751 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
752 rctl = rctl & ~RCTL_MPE;
753 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
754}
755
756/** Enable multicast promiscuous mode
757 *
758 * @param e1000 E1000 data structure
759 *
760 */
761static void e1000_enable_multicast_promisc(e1000_t *e1000)
762{
763 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
764 rctl = rctl | RCTL_MPE;
765 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
766}
767
768/** Enable accepting of broadcast frames
769 *
770 * @param e1000 E1000 data structure
771 *
772 */
773static void e1000_enable_broadcast_accept(e1000_t *e1000)
774{
775 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
776 rctl = rctl | RCTL_BAM;
777 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
778}
779
780/** Disable accepting of broadcast frames
781 *
782 * @param e1000 E1000 data structure
783 *
784 */
785static void e1000_disable_broadcast_accept(e1000_t *e1000)
786{
787 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
788 rctl = rctl & ~RCTL_BAM;
789 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
790}
791
792/** Enable VLAN filtering according to VFTA registers
793 *
794 * @param e1000 E1000 data structure
795 *
796 */
797static void e1000_enable_vlan_filter(e1000_t *e1000)
798{
799 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
800 rctl = rctl | RCTL_VFE;
801 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
802}
803
804/** Disable VLAN filtering
805 *
806 * @param e1000 E1000 data structure
807 *
808 */
809static void e1000_disable_vlan_filter(e1000_t *e1000)
810{
811 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
812 rctl = rctl & ~RCTL_VFE;
813 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
814}
815
816/** Set multicast frames acceptance mode
817 *
818 * @param nic NIC device to update
819 * @param mode Mode to set
820 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
821 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
822 *
823 * @return EOK
824 *
825 */
826static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
827 const nic_address_t *addr, size_t addr_cnt)
828{
829 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
830 int rc = EOK;
831
832 fibril_mutex_lock(&e1000->rx_lock);
833
834 switch (mode) {
835 case NIC_MULTICAST_BLOCKED:
836 e1000_clear_multicast_receive_addresses(e1000);
837 e1000_disable_multicast_promisc(e1000);
838 nic_report_hw_filtering(nic, -1, 1, -1);
839 break;
840 case NIC_MULTICAST_LIST:
841 e1000_clear_multicast_receive_addresses(e1000);
842 if (addr_cnt > get_free_multicast_address_count(e1000)) {
843 /*
844 * Future work: fill MTA table
845 * Not strictly neccessary, it only saves some compares
846 * in the NIC library.
847 */
848 e1000_enable_multicast_promisc(e1000);
849 nic_report_hw_filtering(nic, -1, 0, -1);
850 } else {
851 e1000_disable_multicast_promisc(e1000);
852 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
853 nic_report_hw_filtering(nic, -1, 1, -1);
854 }
855 break;
856 case NIC_MULTICAST_PROMISC:
857 e1000_enable_multicast_promisc(e1000);
858 e1000_clear_multicast_receive_addresses(e1000);
859 nic_report_hw_filtering(nic, -1, 1, -1);
860 break;
861 default:
862 rc = ENOTSUP;
863 break;
864 }
865
866 fibril_mutex_unlock(&e1000->rx_lock);
867 return rc;
868}
869
870/** Set unicast frames acceptance mode
871 *
872 * @param nic NIC device to update
873 * @param mode Mode to set
874 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
875 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
876 *
877 * @return EOK
878 *
879 */
880static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
881 const nic_address_t *addr, size_t addr_cnt)
882{
883 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
884 int rc = EOK;
885
886 fibril_mutex_lock(&e1000->rx_lock);
887
888 switch (mode) {
889 case NIC_UNICAST_BLOCKED:
890 disable_ra0_address_filter(e1000);
891 e1000_clear_unicast_receive_addresses(e1000);
892 e1000_disable_unicast_promisc(e1000);
893 nic_report_hw_filtering(nic, 1, -1, -1);
894 break;
895 case NIC_UNICAST_DEFAULT:
896 enable_ra0_address_filter(e1000);
897 e1000_clear_unicast_receive_addresses(e1000);
898 e1000_disable_unicast_promisc(e1000);
899 nic_report_hw_filtering(nic, 1, -1, -1);
900 break;
901 case NIC_UNICAST_LIST:
902 enable_ra0_address_filter(e1000);
903 e1000_clear_unicast_receive_addresses(e1000);
904 if (addr_cnt > get_free_unicast_address_count(e1000)) {
905 e1000_enable_unicast_promisc(e1000);
906 nic_report_hw_filtering(nic, 0, -1, -1);
907 } else {
908 e1000_disable_unicast_promisc(e1000);
909 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
910 nic_report_hw_filtering(nic, 1, -1, -1);
911 }
912 break;
913 case NIC_UNICAST_PROMISC:
914 e1000_enable_unicast_promisc(e1000);
915 enable_ra0_address_filter(e1000);
916 e1000_clear_unicast_receive_addresses(e1000);
917 nic_report_hw_filtering(nic, 1, -1, -1);
918 break;
919 default:
920 rc = ENOTSUP;
921 break;
922 }
923
924 fibril_mutex_unlock(&e1000->rx_lock);
925 return rc;
926}
927
928/** Set broadcast frames acceptance mode
929 *
930 * @param nic NIC device to update
931 * @param mode Mode to set
932 *
933 * @return EOK
934 *
935 */
936static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
937{
938 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
939 int rc = EOK;
940
941 fibril_mutex_lock(&e1000->rx_lock);
942
943 switch (mode) {
944 case NIC_BROADCAST_BLOCKED:
945 e1000_disable_broadcast_accept(e1000);
946 break;
947 case NIC_BROADCAST_ACCEPTED:
948 e1000_enable_broadcast_accept(e1000);
949 break;
950 default:
951 rc = ENOTSUP;
952 break;
953 }
954
955 fibril_mutex_unlock(&e1000->rx_lock);
956 return rc;
957}
958
959/** Check if receiving is enabled
960 *
961 * @param e1000 E1000 data structure
962 *
963 * @return true if receiving is enabled
964 *
965 */
966static bool e1000_is_rx_enabled(e1000_t *e1000)
967{
968 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
969 return true;
970
971 return false;
972}
973
974/** Enable receiving
975 *
976 * @param e1000 E1000 data structure
977 *
978 */
979static void e1000_enable_rx(e1000_t *e1000)
980{
981 /* Set Receive Enable Bit */
982 E1000_REG_WRITE(e1000, E1000_RCTL,
983 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
984}
985
986/** Disable receiving
987 *
988 * @param e1000 E1000 data structure
989 *
990 */
991static void e1000_disable_rx(e1000_t *e1000)
992{
993 /* Clear Receive Enable Bit */
994 E1000_REG_WRITE(e1000, E1000_RCTL,
995 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
996}
997
998/** Set VLAN mask
999 *
1000 * @param nic NIC device to update
1001 * @param vlan_mask VLAN mask
1002 *
1003 */
1004static void e1000_on_vlan_mask_change(nic_t *nic,
1005 const nic_vlan_mask_t *vlan_mask)
1006{
1007 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1008
1009 fibril_mutex_lock(&e1000->rx_lock);
1010
1011 if (vlan_mask) {
1012 /*
1013 * Disable receiving, so that frame matching
1014 * partially written VLAN is not received.
1015 */
1016 bool rx_enabled = e1000_is_rx_enabled(e1000);
1017 if (rx_enabled)
1018 e1000_disable_rx(e1000);
1019
1020 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1021 uint32_t bitmap_part =
1022 ((uint32_t) vlan_mask->bitmap[i]) |
1023 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1024 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1025 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1026 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1027 }
1028
1029 e1000_enable_vlan_filter(e1000);
1030 if (rx_enabled)
1031 e1000_enable_rx(e1000);
1032 } else
1033 e1000_disable_vlan_filter(e1000);
1034
1035 fibril_mutex_unlock(&e1000->rx_lock);
1036}
1037
1038/** Set VLAN mask
1039 *
1040 * @param device E1000 device
1041 * @param tag VLAN tag
1042 *
1043 * @return EOK
1044 * @return ENOTSUP
1045 *
1046 */
1047static int e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1048 bool strip)
1049{
1050 /* VLAN CFI bit cannot be set */
1051 if (tag & VLANTAG_CFI)
1052 return ENOTSUP;
1053
1054 /*
1055 * CTRL.VME is neccessary for both strip and add
1056 * but CTRL.VME means stripping tags on receive.
1057 */
1058 if (!strip && add)
1059 return ENOTSUP;
1060
1061 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1062
1063 e1000->vlan_tag = tag;
1064 e1000->vlan_tag_add = add;
1065
1066 fibril_mutex_lock(&e1000->ctrl_lock);
1067
1068 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1069 if (strip)
1070 ctrl |= CTRL_VME;
1071 else
1072 ctrl &= ~CTRL_VME;
1073
1074 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1075
1076 fibril_mutex_unlock(&e1000->ctrl_lock);
1077 return EOK;
1078}
1079
1080/** Fill receive descriptor with new empty buffer
1081 *
1082 * Store frame in e1000->rx_frame_phys
1083 *
1084 * @param nic NIC data stricture
1085 * @param offset Receive descriptor offset
1086 *
1087 */
1088static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1089{
1090 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1091
1092 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1093 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1094
1095 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1096 rx_descriptor->length = 0;
1097 rx_descriptor->checksum = 0;
1098 rx_descriptor->status = 0;
1099 rx_descriptor->errors = 0;
1100 rx_descriptor->special = 0;
1101}
1102
1103/** Clear receive descriptor
1104 *
1105 * @param e1000 E1000 data
1106 * @param offset Receive descriptor offset
1107 *
1108 */
1109static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1110{
1111 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1112 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1113
1114 rx_descriptor->length = 0;
1115 rx_descriptor->checksum = 0;
1116 rx_descriptor->status = 0;
1117 rx_descriptor->errors = 0;
1118 rx_descriptor->special = 0;
1119}
1120
1121/** Clear receive descriptor
1122 *
1123 * @param nic NIC data
1124 * @param offset Receive descriptor offset
1125 *
1126 */
1127static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1128{
1129 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1130
1131 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1132 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1133
1134 tx_descriptor->phys_addr = 0;
1135 tx_descriptor->length = 0;
1136 tx_descriptor->checksum_offset = 0;
1137 tx_descriptor->command = 0;
1138 tx_descriptor->status = 0;
1139 tx_descriptor->checksum_start_field = 0;
1140 tx_descriptor->special = 0;
1141}
1142
1143/** Increment tail pointer for receive or transmit ring
1144 *
1145 * @param tail Old Tail
1146 * @param descriptors_count Ring length
1147 *
1148 * @return New tail
1149 *
1150 */
1151static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1152{
1153 if (tail + 1 == descriptors_count)
1154 return 0;
1155 else
1156 return tail + 1;
1157}
1158
1159/** Receive frames
1160 *
1161 * @param nic NIC data
1162 *
1163 */
1164static void e1000_receive_frames(nic_t *nic)
1165{
1166 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1167
1168 fibril_mutex_lock(&e1000->rx_lock);
1169
1170 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1171 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1172
1173 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1174 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1175
1176 while (rx_descriptor->status & 0x01) {
1177 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1178
1179 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1180 if (frame != NULL) {
1181 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1182 nic_received_frame(nic, frame);
1183 } else {
1184 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1185 }
1186
1187 e1000_fill_new_rx_descriptor(nic, next_tail);
1188
1189 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1190 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1191
1192 rx_descriptor = (e1000_rx_descriptor_t *)
1193 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1194 }
1195
1196 fibril_mutex_unlock(&e1000->rx_lock);
1197}
1198
1199/** Enable E1000 interupts
1200 *
1201 * @param e1000 E1000 data structure
1202 *
1203 */
1204static void e1000_enable_interrupts(e1000_t *e1000)
1205{
1206 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1207}
1208
1209/** Disable E1000 interupts
1210 *
1211 * @param e1000 E1000 data structure
1212 *
1213 */
1214static void e1000_disable_interrupts(e1000_t *e1000)
1215{
1216 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1217}
1218
1219/** Interrupt handler implementation
1220 *
1221 * This function is called from e1000_interrupt_handler()
1222 * and e1000_poll()
1223 *
1224 * @param nic NIC data
1225 * @param icr ICR register value
1226 *
1227 */
1228static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1229{
1230 if (icr & ICR_RXT0)
1231 e1000_receive_frames(nic);
1232}
1233
1234/** Handle device interrupt
1235 *
1236 * @param dev E1000 device
1237 * @param iid IPC call id
1238 * @param icall IPC call structure
1239 *
1240 */
1241static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
1242 ipc_call_t *icall)
1243{
1244 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1245 nic_t *nic = NIC_DATA_DEV(dev);
1246 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1247
1248 e1000_interrupt_handler_impl(nic, icr);
1249 e1000_enable_interrupts(e1000);
1250}
1251
1252/** Register interrupt handler for the card in the system
1253 *
1254 * Note: The global irq_reg_mutex is locked because of work with global
1255 * structure.
1256 *
1257 * @param nic Driver data
1258 *
1259 * @return EOK if the handler was registered
1260 * @return Negative error code otherwise
1261 *
1262 */
1263inline static int e1000_register_int_handler(nic_t *nic)
1264{
1265 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1266
1267 /* Lock the mutex in whole driver while working with global structure */
1268 fibril_mutex_lock(&irq_reg_mutex);
1269
1270 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1271 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1272 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1273
1274 int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
1275 e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
1276
1277 fibril_mutex_unlock(&irq_reg_mutex);
1278 return rc;
1279}
1280
1281/** Force receiving all frames in the receive buffer
1282 *
1283 * @param nic NIC data
1284 *
1285 */
1286static void e1000_poll(nic_t *nic)
1287{
1288 assert(nic);
1289
1290 e1000_t *e1000 = nic_get_specific(nic);
1291 assert(e1000);
1292
1293 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1294 e1000_interrupt_handler_impl(nic, icr);
1295}
1296
1297/** Calculates ITR register interrupt from timeval structure
1298 *
1299 * @param period Period
1300 *
1301 */
1302static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1303{
1304 // TODO: use also tv_sec
1305 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1306}
1307
1308/** Set polling mode
1309 *
1310 * @param device Device to set
1311 * @param mode Mode to set
1312 * @param period Period for NIC_POLL_PERIODIC
1313 *
1314 * @return EOK if succeed
1315 * @return ENOTSUP if the mode is not supported
1316 *
1317 */
1318static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1319 const struct timeval *period)
1320{
1321 assert(nic);
1322
1323 e1000_t *e1000 = nic_get_specific(nic);
1324 assert(e1000);
1325
1326 switch (mode) {
1327 case NIC_POLL_IMMEDIATE:
1328 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1329 e1000_enable_interrupts(e1000);
1330 break;
1331 case NIC_POLL_ON_DEMAND:
1332 e1000_disable_interrupts(e1000);
1333 break;
1334 case NIC_POLL_PERIODIC:
1335 assert(period);
1336 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1337 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1338 e1000_enable_interrupts(e1000);
1339 break;
1340 default:
1341 return ENOTSUP;
1342 }
1343
1344 return EOK;
1345}
1346
1347/** Initialize receive registers
1348 *
1349 * @param e1000 E1000 data structure
1350 *
1351 */
1352static void e1000_initialize_rx_registers(e1000_t *e1000)
1353{
1354 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1355 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1356
1357 /* It is not posible to let HW use all descriptors */
1358 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1359
1360 /* Set Broadcast Enable Bit */
1361 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1362}
1363
1364/** Initialize receive structure
1365 *
1366 * @param nic NIC data
1367 *
1368 * @return EOK if succeed
1369 * @return Negative error code otherwise
1370 *
1371 */
1372static int e1000_initialize_rx_structure(nic_t *nic)
1373{
1374 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1375 fibril_mutex_lock(&e1000->rx_lock);
1376
1377 int rc = dmamem_map_anonymous(
1378 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1379 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1380 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1381 if (rc != EOK)
1382 return rc;
1383
1384 E1000_REG_WRITE(e1000, E1000_RDBAH,
1385 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1386 E1000_REG_WRITE(e1000, E1000_RDBAL,
1387 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1388
1389 e1000->rx_frame_phys = (uintptr_t *)
1390 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1391 e1000->rx_frame_virt =
1392 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1393 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1394 rc = ENOMEM;
1395 goto error;
1396 }
1397
1398 size_t i;
1399 uintptr_t frame_phys;
1400 void *frame_virt;
1401
1402 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1403 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1404 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1405 &frame_phys, &frame_virt);
1406 if (rc != EOK)
1407 goto error;
1408
1409 e1000->rx_frame_phys[i] = frame_phys;
1410 e1000->rx_frame_virt[i] = frame_virt;
1411 }
1412
1413 /* Write descriptor */
1414 for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
1415 e1000_fill_new_rx_descriptor(nic, i);
1416
1417 e1000_initialize_rx_registers(e1000);
1418
1419 fibril_mutex_unlock(&e1000->rx_lock);
1420 return EOK;
1421
1422error:
1423 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1424 if (e1000->rx_frame_virt[i] != NULL) {
1425 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1426 e1000->rx_frame_phys[i] = 0;
1427 e1000->rx_frame_virt[i] = NULL;
1428 }
1429 }
1430
1431 if (e1000->rx_frame_phys != NULL) {
1432 free(e1000->rx_frame_phys);
1433 e1000->rx_frame_phys = NULL;
1434 }
1435
1436 if (e1000->rx_frame_virt != NULL) {
1437 free(e1000->rx_frame_virt);
1438 e1000->rx_frame_virt = NULL;
1439 }
1440
1441 return rc;
1442}
1443
1444/** Uninitialize receive structure
1445 *
1446 * @param nic NIC data
1447 *
1448 */
1449static void e1000_uninitialize_rx_structure(nic_t *nic)
1450{
1451 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1452
1453 /* Write descriptor */
1454 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1455 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1456 e1000->rx_frame_phys[offset] = 0;
1457 e1000->rx_frame_virt[offset] = NULL;
1458 }
1459
1460 free(e1000->rx_frame_virt);
1461
1462 e1000->rx_frame_phys = NULL;
1463 e1000->rx_frame_virt = NULL;
1464
1465 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1466}
1467
1468/** Clear receive descriptor ring
1469 *
1470 * @param e1000 E1000 data
1471 *
1472 */
1473static void e1000_clear_rx_ring(e1000_t *e1000)
1474{
1475 /* Write descriptor */
1476 for (unsigned int offset = 0;
1477 offset < E1000_RX_FRAME_COUNT;
1478 offset++)
1479 e1000_clear_rx_descriptor(e1000, offset);
1480}
1481
1482/** Initialize filters
1483 *
1484 * @param e1000 E1000 data
1485 *
1486 */
1487static void e1000_initialize_filters(e1000_t *e1000)
1488{
1489 /* Initialize address filter */
1490 e1000->unicast_ra_count = 0;
1491 e1000->multicast_ra_count = 0;
1492 e1000_clear_unicast_receive_addresses(e1000);
1493}
1494
1495/** Initialize VLAN
1496 *
1497 * @param e1000 E1000 data
1498 *
1499 */
1500static void e1000_initialize_vlan(e1000_t *e1000)
1501{
1502 e1000->vlan_tag_add = false;
1503}
1504
1505/** Fill MAC address from EEPROM to RA[0] register
1506 *
1507 * @param e1000 E1000 data
1508 *
1509 */
1510static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1511{
1512 /* MAC address from eeprom to RA[0] */
1513 nic_address_t address;
1514 e1000_eeprom_get_address(e1000, &address);
1515 e1000_write_receive_address(e1000, 0, &address, true);
1516}
1517
1518/** Initialize other registers
1519 *
1520 * @param dev E1000 data.
1521 *
1522 * @return EOK if succeed
1523 * @return Negative error code otherwise
1524 *
1525 */
1526static void e1000_initialize_registers(e1000_t *e1000)
1527{
1528 E1000_REG_WRITE(e1000, E1000_ITR,
1529 e1000_calculate_itr_interval_from_usecs(
1530 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1531 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1532 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1533 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1534 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1535 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1536 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1537}
1538
1539/** Initialize transmit registers
1540 *
1541 * @param e1000 E1000 data.
1542 *
1543 */
1544static void e1000_initialize_tx_registers(e1000_t *e1000)
1545{
1546 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1547 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1548 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1549
1550 E1000_REG_WRITE(e1000, E1000_TIPG,
1551 10 << TIPG_IPGT_SHIFT |
1552 8 << TIPG_IPGR1_SHIFT |
1553 6 << TIPG_IPGR2_SHIFT);
1554
1555 E1000_REG_WRITE(e1000, E1000_TCTL,
1556 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1557 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1558 TCTL_PSP /* Pad Short Packets */);
1559}
1560
1561/** Initialize transmit structure
1562 *
1563 * @param e1000 E1000 data.
1564 *
1565 */
1566static int e1000_initialize_tx_structure(e1000_t *e1000)
1567{
1568 size_t i;
1569
1570 fibril_mutex_lock(&e1000->tx_lock);
1571
1572 e1000->tx_ring_phys = 0;
1573 e1000->tx_ring_virt = NULL;
1574
1575 e1000->tx_frame_phys = NULL;
1576 e1000->tx_frame_virt = NULL;
1577
1578 int rc = dmamem_map_anonymous(
1579 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1580 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1581 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1582 if (rc != EOK)
1583 goto error;
1584
1585 memset(e1000->tx_ring_virt, 0,
1586 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1587
1588 e1000->tx_frame_phys = (uintptr_t *)
1589 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1590 e1000->tx_frame_virt =
1591 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1592
1593 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1594 rc = ENOMEM;
1595 goto error;
1596 }
1597
1598 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1599 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1600 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1601 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1602 if (rc != EOK)
1603 goto error;
1604 }
1605
1606 E1000_REG_WRITE(e1000, E1000_TDBAH,
1607 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1608 E1000_REG_WRITE(e1000, E1000_TDBAL,
1609 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1610
1611 e1000_initialize_tx_registers(e1000);
1612
1613 fibril_mutex_unlock(&e1000->tx_lock);
1614 return EOK;
1615
1616error:
1617 if (e1000->tx_ring_virt != NULL) {
1618 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1619 e1000->tx_ring_virt = NULL;
1620 }
1621
1622 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1623 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1624 if (e1000->tx_frame_virt[i] != NULL) {
1625 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1626 e1000->tx_frame_phys[i] = 0;
1627 e1000->tx_frame_virt[i] = NULL;
1628 }
1629 }
1630 }
1631
1632 if (e1000->tx_frame_phys != NULL) {
1633 free(e1000->tx_frame_phys);
1634 e1000->tx_frame_phys = NULL;
1635 }
1636
1637 if (e1000->tx_frame_virt != NULL) {
1638 free(e1000->tx_frame_virt);
1639 e1000->tx_frame_virt = NULL;
1640 }
1641
1642 return rc;
1643}
1644
1645/** Uninitialize transmit structure
1646 *
1647 * @param nic NIC data
1648 *
1649 */
1650static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1651{
1652 size_t i;
1653
1654 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1655 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1656 e1000->tx_frame_phys[i] = 0;
1657 e1000->tx_frame_virt[i] = NULL;
1658 }
1659
1660 if (e1000->tx_frame_phys != NULL) {
1661 free(e1000->tx_frame_phys);
1662 e1000->tx_frame_phys = NULL;
1663 }
1664
1665 if (e1000->tx_frame_virt != NULL) {
1666 free(e1000->tx_frame_virt);
1667 e1000->tx_frame_virt = NULL;
1668 }
1669
1670 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1671}
1672
1673/** Clear transmit descriptor ring
1674 *
1675 * @param nic NIC data
1676 *
1677 */
1678static void e1000_clear_tx_ring(nic_t *nic)
1679{
1680 /* Write descriptor */
1681 for (unsigned int offset = 0;
1682 offset < E1000_TX_FRAME_COUNT;
1683 offset++)
1684 e1000_clear_tx_descriptor(nic, offset);
1685}
1686
1687/** Enable transmit
1688 *
1689 * @param e1000 E1000 data
1690 *
1691 */
1692static void e1000_enable_tx(e1000_t *e1000)
1693{
1694 /* Set Transmit Enable Bit */
1695 E1000_REG_WRITE(e1000, E1000_TCTL,
1696 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1697}
1698
1699/** Disable transmit
1700 *
1701 * @param e1000 E1000 data
1702 *
1703 */
1704static void e1000_disable_tx(e1000_t *e1000)
1705{
1706 /* Clear Transmit Enable Bit */
1707 E1000_REG_WRITE(e1000, E1000_TCTL,
1708 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1709}
1710
1711/** Reset E1000 device
1712 *
1713 * @param e1000 The E1000 data
1714 *
1715 */
1716static int e1000_reset(nic_t *nic)
1717{
1718 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1719
1720 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1721
1722 /* Wait for the reset */
1723 usleep(20);
1724
1725 /* check if RST_BIT cleared */
1726 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1727 return EINVAL;
1728
1729 e1000_initialize_registers(e1000);
1730 e1000_initialize_rx_registers(e1000);
1731 e1000_initialize_tx_registers(e1000);
1732 e1000_fill_mac_from_eeprom(e1000);
1733 e1000_initialize_filters(e1000);
1734 e1000_initialize_vlan(e1000);
1735
1736 return EOK;
1737}
1738
1739/** Activate the device to receive and transmit frames
1740 *
1741 * @param nic NIC driver data
1742 *
1743 * @return EOK if activated successfully
1744 * @return Error code otherwise
1745 *
1746 */
1747static int e1000_on_activating(nic_t *nic)
1748{
1749 assert(nic);
1750
1751 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1752
1753 fibril_mutex_lock(&e1000->rx_lock);
1754 fibril_mutex_lock(&e1000->tx_lock);
1755 fibril_mutex_lock(&e1000->ctrl_lock);
1756
1757 e1000_enable_interrupts(e1000);
1758
1759 nic_enable_interrupt(nic, e1000->irq);
1760
1761 e1000_clear_rx_ring(e1000);
1762 e1000_enable_rx(e1000);
1763
1764 e1000_clear_tx_ring(nic);
1765 e1000_enable_tx(e1000);
1766
1767 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1768 ctrl |= CTRL_SLU;
1769 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1770
1771 fibril_mutex_unlock(&e1000->ctrl_lock);
1772 fibril_mutex_unlock(&e1000->tx_lock);
1773 fibril_mutex_unlock(&e1000->rx_lock);
1774
1775 return EOK;
1776}
1777
1778/** Callback for NIC_STATE_DOWN change
1779 *
1780 * @param nic NIC driver data
1781 *
1782 * @return EOK if succeed
1783 * @return Error code otherwise
1784 *
1785 */
1786static int e1000_on_down_unlocked(nic_t *nic)
1787{
1788 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1789
1790 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1791 ctrl &= ~CTRL_SLU;
1792 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1793
1794 e1000_disable_tx(e1000);
1795 e1000_disable_rx(e1000);
1796
1797 nic_disable_interrupt(nic, e1000->irq);
1798 e1000_disable_interrupts(e1000);
1799
1800 /*
1801 * Wait for the for the end of all data
1802 * transfers to descriptors.
1803 */
1804 usleep(100);
1805
1806 return EOK;
1807}
1808
1809/** Callback for NIC_STATE_DOWN change
1810 *
1811 * @param nic NIC driver data
1812 *
1813 * @return EOK if succeed
1814 * @return Error code otherwise
1815 *
1816 */
1817static int e1000_on_down(nic_t *nic)
1818{
1819 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1820
1821 fibril_mutex_lock(&e1000->rx_lock);
1822 fibril_mutex_lock(&e1000->tx_lock);
1823 fibril_mutex_lock(&e1000->ctrl_lock);
1824
1825 int rc = e1000_on_down_unlocked(nic);
1826
1827 fibril_mutex_unlock(&e1000->ctrl_lock);
1828 fibril_mutex_unlock(&e1000->tx_lock);
1829 fibril_mutex_unlock(&e1000->rx_lock);
1830
1831 return rc;
1832}
1833
1834/** Callback for NIC_STATE_STOPPED change
1835 *
1836 * @param nic NIC driver data
1837 *
1838 * @return EOK if succeed
1839 * @return Error code otherwise
1840 *
1841 */
1842static int e1000_on_stopping(nic_t *nic)
1843{
1844 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1845
1846 fibril_mutex_lock(&e1000->rx_lock);
1847 fibril_mutex_lock(&e1000->tx_lock);
1848 fibril_mutex_lock(&e1000->ctrl_lock);
1849
1850 int rc = e1000_on_down_unlocked(nic);
1851 if (rc == EOK)
1852 rc = e1000_reset(nic);
1853
1854 fibril_mutex_unlock(&e1000->ctrl_lock);
1855 fibril_mutex_unlock(&e1000->tx_lock);
1856 fibril_mutex_unlock(&e1000->rx_lock);
1857
1858 return rc;
1859}
1860
1861/** Create driver data structure
1862 *
1863 * @return Intialized device data structure or NULL
1864 *
1865 */
1866static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1867{
1868 nic_t *nic = nic_create_and_bind(dev);
1869 if (!nic)
1870 return NULL;
1871
1872 e1000_t *e1000 = malloc(sizeof(e1000_t));
1873 if (!e1000) {
1874 nic_unbind_and_destroy(dev);
1875 return NULL;
1876 }
1877
1878 memset(e1000, 0, sizeof(e1000_t));
1879
1880 nic_set_specific(nic, e1000);
1881 nic_set_send_frame_handler(nic, e1000_send_frame);
1882 nic_set_state_change_handlers(nic, e1000_on_activating,
1883 e1000_on_down, e1000_on_stopping);
1884 nic_set_filtering_change_handlers(nic,
1885 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1886 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1887 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1888
1889 fibril_mutex_initialize(&e1000->ctrl_lock);
1890 fibril_mutex_initialize(&e1000->rx_lock);
1891 fibril_mutex_initialize(&e1000->tx_lock);
1892 fibril_mutex_initialize(&e1000->eeprom_lock);
1893
1894 return e1000;
1895}
1896
1897/** Delete driver data structure
1898 *
1899 * @param data E1000 device data structure
1900 *
1901 */
1902inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1903{
1904 assert(dev);
1905
1906 if (ddf_dev_data_get(dev) != NULL)
1907 nic_unbind_and_destroy(dev);
1908}
1909
1910/** Clean up the E1000 device structure.
1911 *
1912 * @param dev Device structure.
1913 *
1914 */
1915static void e1000_dev_cleanup(ddf_dev_t *dev)
1916{
1917 assert(dev);
1918
1919 e1000_delete_dev_data(dev);
1920}
1921
1922/** Fill the irq and io_addr part of device data structure
1923 *
1924 * The hw_resources must be obtained before calling this function
1925 *
1926 * @param dev Device structure
1927 * @param hw_resources Hardware resources obtained from the parent device
1928 *
1929 * @return EOK if succeed
1930 * @return Negative error code otherwise
1931 *
1932 */
1933static int e1000_fill_resource_info(ddf_dev_t *dev,
1934 const hw_res_list_parsed_t *hw_resources)
1935{
1936 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1937
1938 if (hw_resources->irqs.count != 1)
1939 return EINVAL;
1940
1941 e1000->irq = hw_resources->irqs.irqs[0];
1942 e1000->reg_base_phys =
1943 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1944
1945 return EOK;
1946}
1947
1948/** Obtain information about hardware resources of the device
1949 *
1950 * The device must be connected to the parent
1951 *
1952 * @param dev Device structure
1953 *
1954 * @return EOK if succeed
1955 * @return Negative error code otherwise
1956 *
1957 */
1958static int e1000_get_resource_info(ddf_dev_t *dev)
1959{
1960 assert(dev != NULL);
1961 assert(NIC_DATA_DEV(dev) != NULL);
1962
1963 hw_res_list_parsed_t hw_res_parsed;
1964 hw_res_list_parsed_init(&hw_res_parsed);
1965
1966 /* Get hw resources form parent driver */
1967 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1968 if (rc != EOK)
1969 return rc;
1970
1971 /* Fill resources information to the device */
1972 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1973 hw_res_list_parsed_clean(&hw_res_parsed);
1974
1975 return rc;
1976}
1977
1978/** Initialize the E1000 device structure
1979 *
1980 * @param dev Device information
1981 *
1982 * @return EOK if succeed
1983 * @return Negative error code otherwise
1984 *
1985 */
1986static int e1000_device_initialize(ddf_dev_t *dev)
1987{
1988 /* Allocate driver data for the device. */
1989 e1000_t *e1000 = e1000_create_dev_data(dev);
1990 if (e1000 == NULL) {
1991 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1992 return ENOMEM;
1993 }
1994
1995 /* Obtain and fill hardware resources info */
1996 int rc = e1000_get_resource_info(dev);
1997 if (rc != EOK) {
1998 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
1999 e1000_dev_cleanup(dev);
2000 return rc;
2001 }
2002
2003 uint16_t device_id;
2004 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2005 &device_id);
2006 if (rc != EOK) {
2007 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2008 e1000_dev_cleanup(dev);
2009 return rc;
2010 }
2011
2012 e1000_board_t board;
2013 switch (device_id) {
2014 case 0x100e:
2015 case 0x1015:
2016 case 0x1016:
2017 case 0x1017:
2018 board = E1000_82540;
2019 break;
2020 case 0x1013:
2021 case 0x1018:
2022 case 0x1078:
2023 board = E1000_82541;
2024 break;
2025 case 0x1076:
2026 case 0x1077:
2027 case 0x107c:
2028 board = E1000_82541REV2;
2029 break;
2030 case 0x100f:
2031 case 0x1011:
2032 case 0x1026:
2033 case 0x1027:
2034 case 0x1028:
2035 board = E1000_82545;
2036 break;
2037 case 0x1010:
2038 case 0x1012:
2039 case 0x101d:
2040 case 0x1079:
2041 case 0x107a:
2042 case 0x107b:
2043 board = E1000_82546;
2044 break;
2045 case 0x1019:
2046 case 0x101a:
2047 board = E1000_82547;
2048 break;
2049 case 0x10b9:
2050 board = E1000_82572;
2051 break;
2052 case 0x1096:
2053 board = E1000_80003ES2;
2054 break;
2055 default:
2056 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2057 device_id);
2058 e1000_dev_cleanup(dev);
2059 return ENOTSUP;
2060 }
2061
2062 switch (board) {
2063 case E1000_82540:
2064 case E1000_82541:
2065 case E1000_82541REV2:
2066 case E1000_82545:
2067 case E1000_82546:
2068 e1000->info.eerd_start = 0x01;
2069 e1000->info.eerd_done = 0x10;
2070 e1000->info.eerd_address_offset = 8;
2071 e1000->info.eerd_data_offset = 16;
2072 break;
2073 case E1000_82547:
2074 case E1000_82572:
2075 case E1000_80003ES2:
2076 e1000->info.eerd_start = 0x01;
2077 e1000->info.eerd_done = 0x02;
2078 e1000->info.eerd_address_offset = 2;
2079 e1000->info.eerd_data_offset = 16;
2080 break;
2081 }
2082
2083 return EOK;
2084}
2085
2086/** Enable the I/O ports of the device.
2087 *
2088 * @param dev E1000 device.
2089 *
2090 * @return EOK if successed
2091 * @return Negative error code otherwise
2092 *
2093 */
2094static int e1000_pio_enable(ddf_dev_t *dev)
2095{
2096 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2097
2098 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2099 &e1000->reg_base_virt);
2100 if (rc != EOK)
2101 return EADDRNOTAVAIL;
2102
2103 return EOK;
2104}
2105
2106/** Probe and initialize the newly added device.
2107 *
2108 * @param dev E1000 device.
2109 *
2110 */
2111int e1000_dev_add(ddf_dev_t *dev)
2112{
2113 ddf_fun_t *fun;
2114 assert(dev);
2115
2116 /* Initialize device structure for E1000 */
2117 int rc = e1000_device_initialize(dev);
2118 if (rc != EOK)
2119 return rc;
2120
2121 /* Device initialization */
2122 nic_t *nic = ddf_dev_data_get(dev);
2123 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2124
2125 /* Map registers */
2126 rc = e1000_pio_enable(dev);
2127 if (rc != EOK)
2128 goto err_destroy;
2129
2130 e1000_initialize_registers(e1000);
2131 rc = e1000_initialize_tx_structure(e1000);
2132 if (rc != EOK)
2133 goto err_pio;
2134
2135 fibril_mutex_lock(&e1000->rx_lock);
2136
2137 e1000_fill_mac_from_eeprom(e1000);
2138 e1000_initialize_filters(e1000);
2139
2140 fibril_mutex_unlock(&e1000->rx_lock);
2141
2142 e1000_initialize_vlan(e1000);
2143
2144 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2145 if (fun == NULL)
2146 goto err_tx_structure;
2147 nic_set_ddf_fun(nic, fun);
2148 ddf_fun_set_ops(fun, &e1000_dev_ops);
2149 ddf_fun_data_implant(fun, nic);
2150
2151 rc = e1000_register_int_handler(nic);
2152 if (rc != EOK)
2153 goto err_fun_create;
2154
2155 rc = nic_connect_to_services(nic);
2156 if (rc != EOK)
2157 goto err_irq;
2158
2159 rc = e1000_initialize_rx_structure(nic);
2160 if (rc != EOK)
2161 goto err_irq;
2162
2163 nic_address_t e1000_address;
2164 e1000_get_address(e1000, &e1000_address);
2165 rc = nic_report_address(nic, &e1000_address);
2166 if (rc != EOK)
2167 goto err_rx_structure;
2168
2169 struct timeval period;
2170 period.tv_sec = 0;
2171 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2172 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2173 if (rc != EOK)
2174 goto err_rx_structure;
2175
2176 rc = ddf_fun_bind(fun);
2177 if (rc != EOK)
2178 goto err_fun_bind;
2179
2180 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2181 if (rc != EOK)
2182 goto err_add_to_cat;
2183
2184 return EOK;
2185
2186err_add_to_cat:
2187 ddf_fun_unbind(fun);
2188err_fun_bind:
2189err_rx_structure:
2190 e1000_uninitialize_rx_structure(nic);
2191err_irq:
2192 unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
2193err_fun_create:
2194 ddf_fun_destroy(fun);
2195 nic_set_ddf_fun(nic, NULL);
2196err_tx_structure:
2197 e1000_uninitialize_tx_structure(e1000);
2198err_pio:
2199 // TODO: e1000_pio_disable(dev);
2200err_destroy:
2201 e1000_dev_cleanup(dev);
2202 return rc;
2203}
2204
2205/** Read 16-bit value from EEPROM of E1000 adapter
2206 *
2207 * Read using the EERD register.
2208 *
2209 * @param device E1000 device
2210 * @param eeprom_address 8-bit EEPROM address
2211 *
2212 * @return 16-bit value from EEPROM
2213 *
2214 */
2215static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2216{
2217 fibril_mutex_lock(&e1000->eeprom_lock);
2218
2219 /* Write address and START bit to EERD register */
2220 uint32_t write_data = e1000->info.eerd_start |
2221 (((uint32_t) eeprom_address) <<
2222 e1000->info.eerd_address_offset);
2223 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2224
2225 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2226 while ((eerd & e1000->info.eerd_done) == 0) {
2227 usleep(1);
2228 eerd = E1000_REG_READ(e1000, E1000_EERD);
2229 }
2230
2231 fibril_mutex_unlock(&e1000->eeprom_lock);
2232
2233 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2234}
2235
2236/** Get MAC address of the E1000 adapter
2237 *
2238 * @param device E1000 device
2239 * @param address Place to store the address
2240 * @param max_len Maximal addresss length to store
2241 *
2242 * @return EOK if succeed
2243 * @return Negative error code otherwise
2244 *
2245 */
2246static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2247{
2248 fibril_mutex_lock(&e1000->rx_lock);
2249
2250 uint8_t *mac0_dest = (uint8_t *) address->address;
2251 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2252 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2253 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2254 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2255 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2256
2257 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2258 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2259
2260 *mac0_dest = (uint8_t) ral;
2261 *mac1_dest = (uint8_t) (ral >> 8);
2262 *mac2_dest = (uint8_t) (ral >> 16);
2263 *mac3_dest = (uint8_t) (ral >> 24);
2264 *mac4_dest = (uint8_t) rah;
2265 *mac5_dest = (uint8_t) (rah >> 8);
2266
2267 fibril_mutex_unlock(&e1000->rx_lock);
2268 return EOK;
2269};
2270
2271/** Set card MAC address
2272 *
2273 * @param device E1000 device
2274 * @param address Address
2275 *
2276 * @return EOK if succeed
2277 * @return Negative error code otherwise
2278 */
2279static int e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2280{
2281 nic_t *nic = NIC_DATA_FUN(fun);
2282 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2283
2284 fibril_mutex_lock(&e1000->rx_lock);
2285 fibril_mutex_lock(&e1000->tx_lock);
2286
2287 int rc = nic_report_address(nic, addr);
2288 if (rc == EOK)
2289 e1000_write_receive_address(e1000, 0, addr, false);
2290
2291 fibril_mutex_unlock(&e1000->tx_lock);
2292 fibril_mutex_unlock(&e1000->rx_lock);
2293
2294 return rc;
2295}
2296
2297static void e1000_eeprom_get_address(e1000_t *e1000,
2298 nic_address_t *address)
2299{
2300 uint16_t *mac0_dest = (uint16_t *) address->address;
2301 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2302 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2303
2304 *mac0_dest = e1000_eeprom_read(e1000, 0);
2305 *mac2_dest = e1000_eeprom_read(e1000, 1);
2306 *mac4_dest = e1000_eeprom_read(e1000, 2);
2307}
2308
2309/** Send frame
2310 *
2311 * @param nic NIC driver data structure
2312 * @param data Frame data
2313 * @param size Frame size in bytes
2314 *
2315 * @return EOK if succeed
2316 * @return Error code in the case of error
2317 *
2318 */
2319static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2320{
2321 assert(nic);
2322
2323 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2324 fibril_mutex_lock(&e1000->tx_lock);
2325
2326 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2327 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2328 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2329
2330 bool descriptor_available = false;
2331
2332 /* Descriptor never used */
2333 if (tx_descriptor_addr->length == 0)
2334 descriptor_available = true;
2335
2336 /* Descriptor done */
2337 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2338 descriptor_available = true;
2339
2340 if (!descriptor_available) {
2341 /* Frame lost */
2342 fibril_mutex_unlock(&e1000->tx_lock);
2343 return;
2344 }
2345
2346 memcpy(e1000->tx_frame_virt[tdt], data, size);
2347
2348 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2349 tx_descriptor_addr->length = size;
2350
2351 /*
2352 * Report status to STATUS.DD (descriptor done),
2353 * add ethernet CRC, end of packet.
2354 */
2355 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2356 TXDESCRIPTOR_COMMAND_IFCS |
2357 TXDESCRIPTOR_COMMAND_EOP;
2358
2359 tx_descriptor_addr->checksum_offset = 0;
2360 tx_descriptor_addr->status = 0;
2361 if (e1000->vlan_tag_add) {
2362 tx_descriptor_addr->special = e1000->vlan_tag;
2363 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2364 } else
2365 tx_descriptor_addr->special = 0;
2366
2367 tx_descriptor_addr->checksum_start_field = 0;
2368
2369 tdt++;
2370 if (tdt == E1000_TX_FRAME_COUNT)
2371 tdt = 0;
2372
2373 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2374
2375 fibril_mutex_unlock(&e1000->tx_lock);
2376}
2377
2378int main(void)
2379{
2380 int rc = nic_driver_init(NAME);
2381 if (rc != EOK)
2382 return rc;
2383
2384 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2385 &e1000_nic_iface);
2386
2387 ddf_log_init(NAME);
2388 ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
2389 return ddf_driver_main(&e1000_driver);
2390}
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