source: mainline/uspace/drv/nic/e1k/e1k.c@ 3f74275

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3f74275 was 3f74275, checked in by Jakub Jermar <jakub@…>, 8 years ago

Fix terminology around capabilities, capability handles and kernel objects
  • Property mode set to 100644
File size: 55.9 KB
Line 
1/*
2 * Copyright (c) 2011 Zdenek Bouska
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file e1k.c
30 *
31 * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
32 *
33 */
34
35#include <assert.h>
36#include <stdio.h>
37#include <errno.h>
38#include <adt/list.h>
39#include <align.h>
40#include <thread.h>
41#include <byteorder.h>
42#include <irc.h>
43#include <as.h>
44#include <ddi.h>
45#include <ddf/log.h>
46#include <ddf/interrupt.h>
47#include <device/hw_res_parsed.h>
48#include <pci_dev_iface.h>
49#include <nic.h>
50#include <ops/nic.h>
51#include "e1k.h"
52
53#define NAME "e1k"
54
55#define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
56
57/* Must be power of 8 */
58#define E1000_RX_FRAME_COUNT 128
59#define E1000_TX_FRAME_COUNT 128
60
61#define E1000_RECEIVE_ADDRESS 16
62
63/** Maximum sending frame size */
64#define E1000_MAX_SEND_FRAME_SIZE 2048
65/** Maximum receiving frame size */
66#define E1000_MAX_RECEIVE_FRAME_SIZE 2048
67
68/** nic_driver_data_t* -> e1000_t* cast */
69#define DRIVER_DATA_NIC(nic) \
70 ((e1000_t *) nic_get_specific(nic))
71
72/** ddf_fun_t * -> nic_driver_data_t* cast */
73#define NIC_DATA_FUN(fun) \
74 ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
75
76/** ddf_dev_t * -> nic_driver_data_t* cast */
77#define NIC_DATA_DEV(dev) \
78 ((nic_t *) ddf_dev_data_get(dev))
79
80/** ddf_dev_t * -> e1000_t* cast */
81#define DRIVER_DATA_DEV(dev) \
82 (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
83
84/** ddf_fun_t * -> e1000_t* cast */
85#define DRIVER_DATA_FUN(fun) \
86 (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
87
88/** Cast pointer to uint64_t
89 *
90 * @param ptr Pointer to cast
91 *
92 * @return The uint64_t pointer representation.
93 *
94 */
95#define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
96
97/** Cast the memaddr part to the void*
98 *
99 * @param memaddr The memaddr value
100 *
101 */
102#define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
103
104#define E1000_REG_BASE(e1000) \
105 ((e1000)->reg_base_virt)
106
107#define E1000_REG_ADDR(e1000, reg) \
108 ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
109
110#define E1000_REG_READ(e1000, reg) \
111 (pio_read_32(E1000_REG_ADDR(e1000, reg)))
112
113#define E1000_REG_WRITE(e1000, reg, value) \
114 (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
115
116/** E1000 device data */
117typedef struct {
118 /** Device configuration */
119 e1000_info_t info;
120
121 /** Physical registers base address */
122 void *reg_base_phys;
123 /** Virtual registers base address */
124 void *reg_base_virt;
125
126 /** Physical tx ring address */
127 uintptr_t tx_ring_phys;
128 /** Virtual tx ring address */
129 void *tx_ring_virt;
130
131 /** Ring of TX frames, physical address */
132 uintptr_t *tx_frame_phys;
133 /** Ring of TX frames, virtual address */
134 void **tx_frame_virt;
135
136 /** Physical rx ring address */
137 uintptr_t rx_ring_phys;
138 /** Virtual rx ring address */
139 void *rx_ring_virt;
140
141 /** Ring of RX frames, physical address */
142 uintptr_t *rx_frame_phys;
143 /** Ring of RX frames, virtual address */
144 void **rx_frame_virt;
145
146 /** VLAN tag */
147 uint16_t vlan_tag;
148
149 /** Add VLAN tag to frame */
150 bool vlan_tag_add;
151
152 /** Used unicast Receive Address count */
153 unsigned int unicast_ra_count;
154
155 /** Used milticast Receive addrress count */
156 unsigned int multicast_ra_count;
157
158 /** The irq assigned */
159 int irq;
160
161 /** Lock for CTRL register */
162 fibril_mutex_t ctrl_lock;
163
164 /** Lock for receiver */
165 fibril_mutex_t rx_lock;
166
167 /** Lock for transmitter */
168 fibril_mutex_t tx_lock;
169
170 /** Lock for EEPROM access */
171 fibril_mutex_t eeprom_lock;
172} e1000_t;
173
174/** Global mutex for work with shared irq structure */
175FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
176
177static int e1000_get_address(e1000_t *, nic_address_t *);
178static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
179static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
180
181static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
182static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
183
184static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
185static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
186static int e1000_get_operation_mode(ddf_fun_t *, int *,
187 nic_channel_mode_t *, nic_role_t *);
188static int e1000_set_operation_mode(ddf_fun_t *, int,
189 nic_channel_mode_t, nic_role_t);
190static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
191static int e1000_autoneg_disable(ddf_fun_t *);
192static int e1000_autoneg_restart(ddf_fun_t *);
193
194static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
195
196/** Network interface options for E1000 card driver */
197static nic_iface_t e1000_nic_iface;
198
199/** Network interface options for E1000 card driver */
200static nic_iface_t e1000_nic_iface = {
201 .set_address = &e1000_set_addr,
202 .get_device_info = &e1000_get_device_info,
203 .get_cable_state = &e1000_get_cable_state,
204 .get_operation_mode = &e1000_get_operation_mode,
205 .set_operation_mode = &e1000_set_operation_mode,
206 .autoneg_enable = &e1000_autoneg_enable,
207 .autoneg_disable = &e1000_autoneg_disable,
208 .autoneg_restart = &e1000_autoneg_restart,
209 .vlan_set_tag = &e1000_vlan_set_tag,
210 .defective_get_mode = &e1000_defective_get_mode,
211 .defective_set_mode = &e1000_defective_set_mode,
212};
213
214/** Basic device operations for E1000 driver */
215static ddf_dev_ops_t e1000_dev_ops;
216
217static int e1000_dev_add(ddf_dev_t *);
218
219/** Basic driver operations for E1000 driver */
220static driver_ops_t e1000_driver_ops = {
221 .dev_add = e1000_dev_add
222};
223
224/** Driver structure for E1000 driver */
225static driver_t e1000_driver = {
226 .name = NAME,
227 .driver_ops = &e1000_driver_ops
228};
229
230/* The default implementation callbacks */
231static int e1000_on_activating(nic_t *);
232static int e1000_on_stopping(nic_t *);
233static void e1000_send_frame(nic_t *, void *, size_t);
234
235/** PIO ranges used in the IRQ code. */
236irq_pio_range_t e1000_irq_pio_ranges[] = {
237 {
238 .base = 0,
239 .size = PAGE_SIZE, /* XXX */
240 }
241};
242
243/** Commands to deal with interrupt
244 *
245 */
246irq_cmd_t e1000_irq_commands[] = {
247 {
248 /* Get the interrupt status */
249 .cmd = CMD_PIO_READ_32,
250 .addr = NULL,
251 .dstarg = 2
252 },
253 {
254 .cmd = CMD_PREDICATE,
255 .value = 2,
256 .srcarg = 2
257 },
258 {
259 /* Disable interrupts until interrupt routine is finished */
260 .cmd = CMD_PIO_WRITE_32,
261 .addr = NULL,
262 .value = 0xffffffff
263 },
264 {
265 .cmd = CMD_ACCEPT
266 }
267};
268
269/** Interrupt code definition */
270irq_code_t e1000_irq_code = {
271 .rangecount = sizeof(e1000_irq_pio_ranges) /
272 sizeof(irq_pio_range_t),
273 .ranges = e1000_irq_pio_ranges,
274 .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
275 .cmds = e1000_irq_commands
276};
277
278/** Get the device information
279 *
280 * @param dev NIC device
281 * @param info Information to fill
282 *
283 * @return EOK
284 *
285 */
286static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
287{
288 assert(dev);
289 assert(info);
290
291 memset(info, 0, sizeof(nic_device_info_t));
292
293 info->vendor_id = 0x8086;
294 str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
295 "Intel Corporation");
296 str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
297 "Intel Pro");
298
299 info->ethernet_support[ETH_10M] = ETH_10BASE_T;
300 info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
301 info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
302
303 return EOK;
304}
305
306/** Check the cable state
307 *
308 * @param[in] dev device
309 * @param[out] state state to fill
310 *
311 * @return EOK
312 *
313 */
314static int e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
315{
316 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
317 if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
318 *state = NIC_CS_PLUGGED;
319 else
320 *state = NIC_CS_UNPLUGGED;
321
322 return EOK;
323}
324
325static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
326{
327 return useconds * 4;
328}
329
330/** Get operation mode of the device
331 *
332 */
333static int e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
334 nic_channel_mode_t *duplex, nic_role_t *role)
335{
336 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
337 uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
338
339 if (status & STATUS_FD)
340 *duplex = NIC_CM_FULL_DUPLEX;
341 else
342 *duplex = NIC_CM_HALF_DUPLEX;
343
344 uint32_t speed_bits =
345 (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
346
347 if (speed_bits == STATUS_SPEED_10)
348 *speed = 10;
349 else if (speed_bits == STATUS_SPEED_100)
350 *speed = 100;
351 else if ((speed_bits == STATUS_SPEED_1000A) ||
352 (speed_bits == STATUS_SPEED_1000B))
353 *speed = 1000;
354
355 *role = NIC_ROLE_UNKNOWN;
356 return EOK;
357}
358
359static void e1000_link_restart(e1000_t *e1000)
360{
361 fibril_mutex_lock(&e1000->ctrl_lock);
362
363 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
364
365 if (ctrl & CTRL_SLU) {
366 ctrl &= ~(CTRL_SLU);
367 fibril_mutex_unlock(&e1000->ctrl_lock);
368 thread_usleep(10);
369 fibril_mutex_lock(&e1000->ctrl_lock);
370 ctrl |= CTRL_SLU;
371 }
372
373 fibril_mutex_unlock(&e1000->ctrl_lock);
374
375 e1000_link_restart(e1000);
376}
377
378/** Set operation mode of the device
379 *
380 */
381static int e1000_set_operation_mode(ddf_fun_t *fun, int speed,
382 nic_channel_mode_t duplex, nic_role_t role)
383{
384 if ((speed != 10) && (speed != 100) && (speed != 1000))
385 return EINVAL;
386
387 if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
388 return EINVAL;
389
390 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
391
392 fibril_mutex_lock(&e1000->ctrl_lock);
393 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
394
395 ctrl |= CTRL_FRCSPD;
396 ctrl |= CTRL_FRCDPLX;
397 ctrl &= ~(CTRL_ASDE);
398
399 if (duplex == NIC_CM_FULL_DUPLEX)
400 ctrl |= CTRL_FD;
401 else
402 ctrl &= ~(CTRL_FD);
403
404 ctrl &= ~(CTRL_SPEED_MASK);
405 if (speed == 1000)
406 ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
407 else if (speed == 100)
408 ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
409 else
410 ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
411
412 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
413
414 fibril_mutex_unlock(&e1000->ctrl_lock);
415
416 e1000_link_restart(e1000);
417
418 return EOK;
419}
420
421/** Enable auto-negotiation
422 *
423 * @param dev Device to update
424 * @param advertisement Ignored on E1000
425 *
426 * @return EOK if advertisement mode set successfully
427 *
428 */
429static int e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
430{
431 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
432
433 fibril_mutex_lock(&e1000->ctrl_lock);
434
435 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
436
437 ctrl &= ~(CTRL_FRCSPD);
438 ctrl &= ~(CTRL_FRCDPLX);
439 ctrl |= CTRL_ASDE;
440
441 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
442
443 fibril_mutex_unlock(&e1000->ctrl_lock);
444
445 e1000_link_restart(e1000);
446
447 return EOK;
448}
449
450/** Disable auto-negotiation
451 *
452 * @param dev Device to update
453 *
454 * @return EOK
455 *
456 */
457static int e1000_autoneg_disable(ddf_fun_t *fun)
458{
459 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
460
461 fibril_mutex_lock(&e1000->ctrl_lock);
462
463 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
464
465 ctrl |= CTRL_FRCSPD;
466 ctrl |= CTRL_FRCDPLX;
467 ctrl &= ~(CTRL_ASDE);
468
469 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
470
471 fibril_mutex_unlock(&e1000->ctrl_lock);
472
473 e1000_link_restart(e1000);
474
475 return EOK;
476}
477
478/** Restart auto-negotiation
479 *
480 * @param dev Device to update
481 *
482 * @return EOK if advertisement mode set successfully
483 *
484 */
485static int e1000_autoneg_restart(ddf_fun_t *dev)
486{
487 return e1000_autoneg_enable(dev, 0);
488}
489
490/** Get state of acceptance of weird frames
491 *
492 * @param device Device to check
493 * @param[out] mode Current mode
494 *
495 */
496static int e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
497{
498 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
499
500 *mode = 0;
501 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
502 if (rctl & RCTL_SBP)
503 *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
504
505 return EOK;
506};
507
508/** Set acceptance of weird frames
509 *
510 * @param device Device to update
511 * @param mode Mode to set
512 *
513 * @return ENOTSUP if the mode is not supported
514 * @return EOK of mode was set
515 *
516 */
517static int e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
518{
519 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
520 int rc = EOK;
521
522 fibril_mutex_lock(&e1000->rx_lock);
523
524 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
525 bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
526 bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
527
528 if (short_mode && bad_mode)
529 rctl |= RCTL_SBP;
530 else if ((!short_mode) && (!bad_mode))
531 rctl &= ~RCTL_SBP;
532 else
533 rc = ENOTSUP;
534
535 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
536
537 fibril_mutex_unlock(&e1000->rx_lock);
538 return rc;
539};
540
541/** Write receive address to RA registr
542 *
543 * @param e1000 E1000 data structure
544 * @param position RA register position
545 * @param address Ethernet address
546 * @param set_av_bit Set the Addtess Valid bit
547 *
548 */
549static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
550 const nic_address_t * address, bool set_av_bit)
551{
552 uint8_t *mac0 = (uint8_t *) address->address;
553 uint8_t *mac1 = (uint8_t *) address->address + 1;
554 uint8_t *mac2 = (uint8_t *) address->address + 2;
555 uint8_t *mac3 = (uint8_t *) address->address + 3;
556 uint8_t *mac4 = (uint8_t *) address->address + 4;
557 uint8_t *mac5 = (uint8_t *) address->address + 5;
558
559 uint32_t rah;
560 uint32_t ral;
561
562 ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
563 rah = ((*mac5) << 8) | ((*mac4));
564
565 if (set_av_bit)
566 rah |= RAH_AV;
567 else
568 rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
569
570 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
571 E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
572}
573
574/** Disable receive address in RA registr
575 *
576 * Clear Address Valid bit
577 *
578 * @param e1000 E1000 data structure
579 * @param position RA register position
580 *
581 */
582static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
583{
584 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
585 rah = rah & ~RAH_AV;
586 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
587}
588
589/** Clear all unicast addresses from RA registers
590 *
591 * @param e1000 E1000 data structure
592 *
593 */
594static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
595{
596 for (unsigned int ra_num = 1;
597 ra_num <= e1000->unicast_ra_count;
598 ra_num++)
599 e1000_disable_receive_address(e1000, ra_num);
600
601 e1000->unicast_ra_count = 0;
602}
603
604/** Clear all multicast addresses from RA registers
605 *
606 * @param e1000 E1000 data structure
607 *
608 */
609static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
610{
611 unsigned int first_multicast_ra_num =
612 E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
613
614 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
615 ra_num >= first_multicast_ra_num;
616 ra_num--)
617 e1000_disable_receive_address(e1000, ra_num);
618
619 e1000->multicast_ra_count = 0;
620}
621
622/** Return receive address filter positions count usable for unicast
623 *
624 * @param e1000 E1000 data structure
625 *
626 * @return receive address filter positions count usable for unicast
627 *
628 */
629static unsigned int get_free_unicast_address_count(e1000_t *e1000)
630{
631 return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
632}
633
634/** Return receive address filter positions count usable for multicast
635 *
636 * @param e1000 E1000 data structure
637 *
638 * @return receive address filter positions count usable for multicast
639 *
640 */
641static unsigned int get_free_multicast_address_count(e1000_t *e1000)
642{
643 return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
644}
645
646/** Write unicast receive addresses to receive address filter registers
647 *
648 * @param e1000 E1000 data structure
649 * @param addr Pointer to address array
650 * @param addr_cnt Address array count
651 *
652 */
653static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
654 const nic_address_t *addr, size_t addr_cnt)
655{
656 assert(addr_cnt <= get_free_unicast_address_count(e1000));
657
658 nic_address_t *addr_iterator = (nic_address_t *) addr;
659
660 /* ra_num = 0 is primary address */
661 for (unsigned int ra_num = 1;
662 ra_num <= addr_cnt;
663 ra_num++) {
664 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
665 addr_iterator++;
666 }
667}
668
669/** Write multicast receive addresses to receive address filter registers
670 *
671 * @param e1000 E1000 data structure
672 * @param addr Pointer to address array
673 * @param addr_cnt Address array count
674 *
675 */
676static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
677 const nic_address_t *addr, size_t addr_cnt)
678{
679 assert(addr_cnt <= get_free_multicast_address_count(e1000));
680
681 nic_address_t *addr_iterator = (nic_address_t *) addr;
682
683 unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
684 for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
685 ra_num >= first_multicast_ra_num;
686 ra_num--) {
687 e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
688 addr_iterator++;
689 }
690}
691
692/** Disable receiving frames for default address
693 *
694 * @param e1000 E1000 data structure
695 *
696 */
697static void disable_ra0_address_filter(e1000_t *e1000)
698{
699 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
700 rah0 = rah0 & ~RAH_AV;
701 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
702}
703
704/** Enable receiving frames for default address
705 *
706 * @param e1000 E1000 data structure
707 *
708 */
709static void enable_ra0_address_filter(e1000_t *e1000)
710{
711 uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
712 rah0 = rah0 | RAH_AV;
713 E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
714}
715
716/** Disable unicast promiscuous mode
717 *
718 * @param e1000 E1000 data structure
719 *
720 */
721static void e1000_disable_unicast_promisc(e1000_t *e1000)
722{
723 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
724 rctl = rctl & ~RCTL_UPE;
725 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
726}
727
728/** Enable unicast promiscuous mode
729 *
730 * @param e1000 E1000 data structure
731 *
732 */
733static void e1000_enable_unicast_promisc(e1000_t *e1000)
734{
735 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
736 rctl = rctl | RCTL_UPE;
737 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
738}
739
740/** Disable multicast promiscuous mode
741 *
742 * @param e1000 E1000 data structure
743 *
744 */
745static void e1000_disable_multicast_promisc(e1000_t *e1000)
746{
747 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
748 rctl = rctl & ~RCTL_MPE;
749 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
750}
751
752/** Enable multicast promiscuous mode
753 *
754 * @param e1000 E1000 data structure
755 *
756 */
757static void e1000_enable_multicast_promisc(e1000_t *e1000)
758{
759 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
760 rctl = rctl | RCTL_MPE;
761 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
762}
763
764/** Enable accepting of broadcast frames
765 *
766 * @param e1000 E1000 data structure
767 *
768 */
769static void e1000_enable_broadcast_accept(e1000_t *e1000)
770{
771 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
772 rctl = rctl | RCTL_BAM;
773 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
774}
775
776/** Disable accepting of broadcast frames
777 *
778 * @param e1000 E1000 data structure
779 *
780 */
781static void e1000_disable_broadcast_accept(e1000_t *e1000)
782{
783 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
784 rctl = rctl & ~RCTL_BAM;
785 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
786}
787
788/** Enable VLAN filtering according to VFTA registers
789 *
790 * @param e1000 E1000 data structure
791 *
792 */
793static void e1000_enable_vlan_filter(e1000_t *e1000)
794{
795 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
796 rctl = rctl | RCTL_VFE;
797 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
798}
799
800/** Disable VLAN filtering
801 *
802 * @param e1000 E1000 data structure
803 *
804 */
805static void e1000_disable_vlan_filter(e1000_t *e1000)
806{
807 uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
808 rctl = rctl & ~RCTL_VFE;
809 E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
810}
811
812/** Set multicast frames acceptance mode
813 *
814 * @param nic NIC device to update
815 * @param mode Mode to set
816 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
817 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
818 *
819 * @return EOK
820 *
821 */
822static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
823 const nic_address_t *addr, size_t addr_cnt)
824{
825 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
826 int rc = EOK;
827
828 fibril_mutex_lock(&e1000->rx_lock);
829
830 switch (mode) {
831 case NIC_MULTICAST_BLOCKED:
832 e1000_clear_multicast_receive_addresses(e1000);
833 e1000_disable_multicast_promisc(e1000);
834 nic_report_hw_filtering(nic, -1, 1, -1);
835 break;
836 case NIC_MULTICAST_LIST:
837 e1000_clear_multicast_receive_addresses(e1000);
838 if (addr_cnt > get_free_multicast_address_count(e1000)) {
839 /*
840 * Future work: fill MTA table
841 * Not strictly neccessary, it only saves some compares
842 * in the NIC library.
843 */
844 e1000_enable_multicast_promisc(e1000);
845 nic_report_hw_filtering(nic, -1, 0, -1);
846 } else {
847 e1000_disable_multicast_promisc(e1000);
848 e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
849 nic_report_hw_filtering(nic, -1, 1, -1);
850 }
851 break;
852 case NIC_MULTICAST_PROMISC:
853 e1000_enable_multicast_promisc(e1000);
854 e1000_clear_multicast_receive_addresses(e1000);
855 nic_report_hw_filtering(nic, -1, 1, -1);
856 break;
857 default:
858 rc = ENOTSUP;
859 break;
860 }
861
862 fibril_mutex_unlock(&e1000->rx_lock);
863 return rc;
864}
865
866/** Set unicast frames acceptance mode
867 *
868 * @param nic NIC device to update
869 * @param mode Mode to set
870 * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
871 * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
872 *
873 * @return EOK
874 *
875 */
876static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
877 const nic_address_t *addr, size_t addr_cnt)
878{
879 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
880 int rc = EOK;
881
882 fibril_mutex_lock(&e1000->rx_lock);
883
884 switch (mode) {
885 case NIC_UNICAST_BLOCKED:
886 disable_ra0_address_filter(e1000);
887 e1000_clear_unicast_receive_addresses(e1000);
888 e1000_disable_unicast_promisc(e1000);
889 nic_report_hw_filtering(nic, 1, -1, -1);
890 break;
891 case NIC_UNICAST_DEFAULT:
892 enable_ra0_address_filter(e1000);
893 e1000_clear_unicast_receive_addresses(e1000);
894 e1000_disable_unicast_promisc(e1000);
895 nic_report_hw_filtering(nic, 1, -1, -1);
896 break;
897 case NIC_UNICAST_LIST:
898 enable_ra0_address_filter(e1000);
899 e1000_clear_unicast_receive_addresses(e1000);
900 if (addr_cnt > get_free_unicast_address_count(e1000)) {
901 e1000_enable_unicast_promisc(e1000);
902 nic_report_hw_filtering(nic, 0, -1, -1);
903 } else {
904 e1000_disable_unicast_promisc(e1000);
905 e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
906 nic_report_hw_filtering(nic, 1, -1, -1);
907 }
908 break;
909 case NIC_UNICAST_PROMISC:
910 e1000_enable_unicast_promisc(e1000);
911 enable_ra0_address_filter(e1000);
912 e1000_clear_unicast_receive_addresses(e1000);
913 nic_report_hw_filtering(nic, 1, -1, -1);
914 break;
915 default:
916 rc = ENOTSUP;
917 break;
918 }
919
920 fibril_mutex_unlock(&e1000->rx_lock);
921 return rc;
922}
923
924/** Set broadcast frames acceptance mode
925 *
926 * @param nic NIC device to update
927 * @param mode Mode to set
928 *
929 * @return EOK
930 *
931 */
932static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
933{
934 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
935 int rc = EOK;
936
937 fibril_mutex_lock(&e1000->rx_lock);
938
939 switch (mode) {
940 case NIC_BROADCAST_BLOCKED:
941 e1000_disable_broadcast_accept(e1000);
942 break;
943 case NIC_BROADCAST_ACCEPTED:
944 e1000_enable_broadcast_accept(e1000);
945 break;
946 default:
947 rc = ENOTSUP;
948 break;
949 }
950
951 fibril_mutex_unlock(&e1000->rx_lock);
952 return rc;
953}
954
955/** Check if receiving is enabled
956 *
957 * @param e1000 E1000 data structure
958 *
959 * @return true if receiving is enabled
960 *
961 */
962static bool e1000_is_rx_enabled(e1000_t *e1000)
963{
964 if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
965 return true;
966
967 return false;
968}
969
970/** Enable receiving
971 *
972 * @param e1000 E1000 data structure
973 *
974 */
975static void e1000_enable_rx(e1000_t *e1000)
976{
977 /* Set Receive Enable Bit */
978 E1000_REG_WRITE(e1000, E1000_RCTL,
979 E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
980}
981
982/** Disable receiving
983 *
984 * @param e1000 E1000 data structure
985 *
986 */
987static void e1000_disable_rx(e1000_t *e1000)
988{
989 /* Clear Receive Enable Bit */
990 E1000_REG_WRITE(e1000, E1000_RCTL,
991 E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
992}
993
994/** Set VLAN mask
995 *
996 * @param nic NIC device to update
997 * @param vlan_mask VLAN mask
998 *
999 */
1000static void e1000_on_vlan_mask_change(nic_t *nic,
1001 const nic_vlan_mask_t *vlan_mask)
1002{
1003 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1004
1005 fibril_mutex_lock(&e1000->rx_lock);
1006
1007 if (vlan_mask) {
1008 /*
1009 * Disable receiving, so that frame matching
1010 * partially written VLAN is not received.
1011 */
1012 bool rx_enabled = e1000_is_rx_enabled(e1000);
1013 if (rx_enabled)
1014 e1000_disable_rx(e1000);
1015
1016 for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
1017 uint32_t bitmap_part =
1018 ((uint32_t) vlan_mask->bitmap[i]) |
1019 (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
1020 (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
1021 (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
1022 E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
1023 }
1024
1025 e1000_enable_vlan_filter(e1000);
1026 if (rx_enabled)
1027 e1000_enable_rx(e1000);
1028 } else
1029 e1000_disable_vlan_filter(e1000);
1030
1031 fibril_mutex_unlock(&e1000->rx_lock);
1032}
1033
1034/** Set VLAN mask
1035 *
1036 * @param device E1000 device
1037 * @param tag VLAN tag
1038 *
1039 * @return EOK
1040 * @return ENOTSUP
1041 *
1042 */
1043static int e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
1044 bool strip)
1045{
1046 /* VLAN CFI bit cannot be set */
1047 if (tag & VLANTAG_CFI)
1048 return ENOTSUP;
1049
1050 /*
1051 * CTRL.VME is neccessary for both strip and add
1052 * but CTRL.VME means stripping tags on receive.
1053 */
1054 if (!strip && add)
1055 return ENOTSUP;
1056
1057 e1000_t *e1000 = DRIVER_DATA_FUN(fun);
1058
1059 e1000->vlan_tag = tag;
1060 e1000->vlan_tag_add = add;
1061
1062 fibril_mutex_lock(&e1000->ctrl_lock);
1063
1064 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1065 if (strip)
1066 ctrl |= CTRL_VME;
1067 else
1068 ctrl &= ~CTRL_VME;
1069
1070 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1071
1072 fibril_mutex_unlock(&e1000->ctrl_lock);
1073 return EOK;
1074}
1075
1076/** Fill receive descriptor with new empty buffer
1077 *
1078 * Store frame in e1000->rx_frame_phys
1079 *
1080 * @param nic NIC data stricture
1081 * @param offset Receive descriptor offset
1082 *
1083 */
1084static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
1085{
1086 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1087
1088 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1089 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1090
1091 rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
1092 rx_descriptor->length = 0;
1093 rx_descriptor->checksum = 0;
1094 rx_descriptor->status = 0;
1095 rx_descriptor->errors = 0;
1096 rx_descriptor->special = 0;
1097}
1098
1099/** Clear receive descriptor
1100 *
1101 * @param e1000 E1000 data
1102 * @param offset Receive descriptor offset
1103 *
1104 */
1105static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
1106{
1107 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1108 (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
1109
1110 rx_descriptor->length = 0;
1111 rx_descriptor->checksum = 0;
1112 rx_descriptor->status = 0;
1113 rx_descriptor->errors = 0;
1114 rx_descriptor->special = 0;
1115}
1116
1117/** Clear receive descriptor
1118 *
1119 * @param nic NIC data
1120 * @param offset Receive descriptor offset
1121 *
1122 */
1123static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
1124{
1125 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1126
1127 e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
1128 (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
1129
1130 tx_descriptor->phys_addr = 0;
1131 tx_descriptor->length = 0;
1132 tx_descriptor->checksum_offset = 0;
1133 tx_descriptor->command = 0;
1134 tx_descriptor->status = 0;
1135 tx_descriptor->checksum_start_field = 0;
1136 tx_descriptor->special = 0;
1137}
1138
1139/** Increment tail pointer for receive or transmit ring
1140 *
1141 * @param tail Old Tail
1142 * @param descriptors_count Ring length
1143 *
1144 * @return New tail
1145 *
1146 */
1147static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
1148{
1149 if (tail + 1 == descriptors_count)
1150 return 0;
1151 else
1152 return tail + 1;
1153}
1154
1155/** Receive frames
1156 *
1157 * @param nic NIC data
1158 *
1159 */
1160static void e1000_receive_frames(nic_t *nic)
1161{
1162 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1163
1164 fibril_mutex_lock(&e1000->rx_lock);
1165
1166 uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
1167 uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1168
1169 e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
1170 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1171
1172 while (rx_descriptor->status & 0x01) {
1173 uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
1174
1175 nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
1176 if (frame != NULL) {
1177 memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
1178 nic_received_frame(nic, frame);
1179 } else {
1180 ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
1181 }
1182
1183 e1000_fill_new_rx_descriptor(nic, next_tail);
1184
1185 *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1186 next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
1187
1188 rx_descriptor = (e1000_rx_descriptor_t *)
1189 (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
1190 }
1191
1192 fibril_mutex_unlock(&e1000->rx_lock);
1193}
1194
1195/** Enable E1000 interupts
1196 *
1197 * @param e1000 E1000 data structure
1198 *
1199 */
1200static void e1000_enable_interrupts(e1000_t *e1000)
1201{
1202 E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
1203}
1204
1205/** Disable E1000 interupts
1206 *
1207 * @param e1000 E1000 data structure
1208 *
1209 */
1210static void e1000_disable_interrupts(e1000_t *e1000)
1211{
1212 E1000_REG_WRITE(e1000, E1000_IMS, 0);
1213}
1214
1215/** Interrupt handler implementation
1216 *
1217 * This function is called from e1000_interrupt_handler()
1218 * and e1000_poll()
1219 *
1220 * @param nic NIC data
1221 * @param icr ICR register value
1222 *
1223 */
1224static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
1225{
1226 if (icr & ICR_RXT0)
1227 e1000_receive_frames(nic);
1228}
1229
1230/** Handle device interrupt
1231 *
1232 * @param iid IPC call id
1233 * @param icall IPC call structure
1234 * @param dev E1000 device
1235 *
1236 */
1237static void e1000_interrupt_handler(ipc_callid_t iid, ipc_call_t *icall,
1238 ddf_dev_t *dev)
1239{
1240 uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
1241 nic_t *nic = NIC_DATA_DEV(dev);
1242 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1243
1244 e1000_interrupt_handler_impl(nic, icr);
1245 e1000_enable_interrupts(e1000);
1246}
1247
1248/** Register interrupt handler for the card in the system
1249 *
1250 * Note: The global irq_reg_mutex is locked because of work with global
1251 * structure.
1252 *
1253 * @param nic Driver data
1254 *
1255 * @return IRQ capability handle if the handler was registered
1256 * @return Negative error code otherwise
1257 *
1258 */
1259inline static int e1000_register_int_handler(nic_t *nic)
1260{
1261 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1262
1263 /* Lock the mutex in whole driver while working with global structure */
1264 fibril_mutex_lock(&irq_reg_mutex);
1265
1266 e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
1267 e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
1268 e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
1269
1270 int cap = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
1271 e1000_interrupt_handler, &e1000_irq_code);
1272
1273 fibril_mutex_unlock(&irq_reg_mutex);
1274 return cap;
1275}
1276
1277/** Force receiving all frames in the receive buffer
1278 *
1279 * @param nic NIC data
1280 *
1281 */
1282static void e1000_poll(nic_t *nic)
1283{
1284 assert(nic);
1285
1286 e1000_t *e1000 = nic_get_specific(nic);
1287 assert(e1000);
1288
1289 uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
1290 e1000_interrupt_handler_impl(nic, icr);
1291}
1292
1293/** Calculates ITR register interrupt from timeval structure
1294 *
1295 * @param period Period
1296 *
1297 */
1298static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
1299{
1300 // TODO: use also tv_sec
1301 return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
1302}
1303
1304/** Set polling mode
1305 *
1306 * @param device Device to set
1307 * @param mode Mode to set
1308 * @param period Period for NIC_POLL_PERIODIC
1309 *
1310 * @return EOK if succeed
1311 * @return ENOTSUP if the mode is not supported
1312 *
1313 */
1314static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
1315 const struct timeval *period)
1316{
1317 assert(nic);
1318
1319 e1000_t *e1000 = nic_get_specific(nic);
1320 assert(e1000);
1321
1322 switch (mode) {
1323 case NIC_POLL_IMMEDIATE:
1324 E1000_REG_WRITE(e1000, E1000_ITR, 0);
1325 e1000_enable_interrupts(e1000);
1326 break;
1327 case NIC_POLL_ON_DEMAND:
1328 e1000_disable_interrupts(e1000);
1329 break;
1330 case NIC_POLL_PERIODIC:
1331 assert(period);
1332 uint16_t itr_interval = e1000_calculate_itr_interval(period);
1333 E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
1334 e1000_enable_interrupts(e1000);
1335 break;
1336 default:
1337 return ENOTSUP;
1338 }
1339
1340 return EOK;
1341}
1342
1343/** Initialize receive registers
1344 *
1345 * @param e1000 E1000 data structure
1346 *
1347 */
1348static void e1000_initialize_rx_registers(e1000_t *e1000)
1349{
1350 E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
1351 E1000_REG_WRITE(e1000, E1000_RDH, 0);
1352
1353 /* It is not posible to let HW use all descriptors */
1354 E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
1355
1356 /* Set Broadcast Enable Bit */
1357 E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
1358}
1359
1360/** Initialize receive structure
1361 *
1362 * @param nic NIC data
1363 *
1364 * @return EOK if succeed
1365 * @return Negative error code otherwise
1366 *
1367 */
1368static int e1000_initialize_rx_structure(nic_t *nic)
1369{
1370 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1371 fibril_mutex_lock(&e1000->rx_lock);
1372
1373 e1000->rx_ring_virt = AS_AREA_ANY;
1374 int rc = dmamem_map_anonymous(
1375 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
1376 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1377 &e1000->rx_ring_phys, &e1000->rx_ring_virt);
1378 if (rc != EOK)
1379 return rc;
1380
1381 E1000_REG_WRITE(e1000, E1000_RDBAH,
1382 (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
1383 E1000_REG_WRITE(e1000, E1000_RDBAL,
1384 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
1385
1386 e1000->rx_frame_phys = (uintptr_t *)
1387 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
1388 e1000->rx_frame_virt =
1389 calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
1390 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
1391 rc = ENOMEM;
1392 goto error;
1393 }
1394
1395 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1396 uintptr_t frame_phys;
1397 void *frame_virt = AS_AREA_ANY;
1398
1399 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1400 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1401 &frame_phys, &frame_virt);
1402 if (rc != EOK)
1403 goto error;
1404
1405 e1000->rx_frame_phys[i] = frame_phys;
1406 e1000->rx_frame_virt[i] = frame_virt;
1407 }
1408
1409 /* Write descriptor */
1410 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
1411 e1000_fill_new_rx_descriptor(nic, i);
1412
1413 e1000_initialize_rx_registers(e1000);
1414
1415 fibril_mutex_unlock(&e1000->rx_lock);
1416 return EOK;
1417
1418error:
1419 for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
1420 if (e1000->rx_frame_virt[i] != NULL) {
1421 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
1422 e1000->rx_frame_phys[i] = 0;
1423 e1000->rx_frame_virt[i] = NULL;
1424 }
1425 }
1426
1427 if (e1000->rx_frame_phys != NULL) {
1428 free(e1000->rx_frame_phys);
1429 e1000->rx_frame_phys = NULL;
1430 }
1431
1432 if (e1000->rx_frame_virt != NULL) {
1433 free(e1000->rx_frame_virt);
1434 e1000->rx_frame_virt = NULL;
1435 }
1436
1437 return rc;
1438}
1439
1440/** Uninitialize receive structure
1441 *
1442 * @param nic NIC data
1443 *
1444 */
1445static void e1000_uninitialize_rx_structure(nic_t *nic)
1446{
1447 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1448
1449 /* Write descriptor */
1450 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
1451 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
1452 e1000->rx_frame_phys[offset] = 0;
1453 e1000->rx_frame_virt[offset] = NULL;
1454 }
1455
1456 free(e1000->rx_frame_virt);
1457
1458 e1000->rx_frame_phys = NULL;
1459 e1000->rx_frame_virt = NULL;
1460
1461 dmamem_unmap_anonymous(e1000->rx_ring_virt);
1462}
1463
1464/** Clear receive descriptor ring
1465 *
1466 * @param e1000 E1000 data
1467 *
1468 */
1469static void e1000_clear_rx_ring(e1000_t *e1000)
1470{
1471 /* Write descriptor */
1472 for (unsigned int offset = 0;
1473 offset < E1000_RX_FRAME_COUNT;
1474 offset++)
1475 e1000_clear_rx_descriptor(e1000, offset);
1476}
1477
1478/** Initialize filters
1479 *
1480 * @param e1000 E1000 data
1481 *
1482 */
1483static void e1000_initialize_filters(e1000_t *e1000)
1484{
1485 /* Initialize address filter */
1486 e1000->unicast_ra_count = 0;
1487 e1000->multicast_ra_count = 0;
1488 e1000_clear_unicast_receive_addresses(e1000);
1489}
1490
1491/** Initialize VLAN
1492 *
1493 * @param e1000 E1000 data
1494 *
1495 */
1496static void e1000_initialize_vlan(e1000_t *e1000)
1497{
1498 e1000->vlan_tag_add = false;
1499}
1500
1501/** Fill MAC address from EEPROM to RA[0] register
1502 *
1503 * @param e1000 E1000 data
1504 *
1505 */
1506static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
1507{
1508 /* MAC address from eeprom to RA[0] */
1509 nic_address_t address;
1510 e1000_eeprom_get_address(e1000, &address);
1511 e1000_write_receive_address(e1000, 0, &address, true);
1512}
1513
1514/** Initialize other registers
1515 *
1516 * @param dev E1000 data.
1517 *
1518 * @return EOK if succeed
1519 * @return Negative error code otherwise
1520 *
1521 */
1522static void e1000_initialize_registers(e1000_t *e1000)
1523{
1524 E1000_REG_WRITE(e1000, E1000_ITR,
1525 e1000_calculate_itr_interval_from_usecs(
1526 E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
1527 E1000_REG_WRITE(e1000, E1000_FCAH, 0);
1528 E1000_REG_WRITE(e1000, E1000_FCAL, 0);
1529 E1000_REG_WRITE(e1000, E1000_FCT, 0);
1530 E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
1531 E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
1532 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
1533}
1534
1535/** Initialize transmit registers
1536 *
1537 * @param e1000 E1000 data.
1538 *
1539 */
1540static void e1000_initialize_tx_registers(e1000_t *e1000)
1541{
1542 E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
1543 E1000_REG_WRITE(e1000, E1000_TDH, 0);
1544 E1000_REG_WRITE(e1000, E1000_TDT, 0);
1545
1546 E1000_REG_WRITE(e1000, E1000_TIPG,
1547 10 << TIPG_IPGT_SHIFT |
1548 8 << TIPG_IPGR1_SHIFT |
1549 6 << TIPG_IPGR2_SHIFT);
1550
1551 E1000_REG_WRITE(e1000, E1000_TCTL,
1552 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
1553 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
1554 TCTL_PSP /* Pad Short Packets */);
1555}
1556
1557/** Initialize transmit structure
1558 *
1559 * @param e1000 E1000 data.
1560 *
1561 */
1562static int e1000_initialize_tx_structure(e1000_t *e1000)
1563{
1564 size_t i;
1565
1566 fibril_mutex_lock(&e1000->tx_lock);
1567
1568 e1000->tx_ring_phys = 0;
1569 e1000->tx_ring_virt = AS_AREA_ANY;
1570
1571 e1000->tx_frame_phys = NULL;
1572 e1000->tx_frame_virt = NULL;
1573
1574 int rc = dmamem_map_anonymous(
1575 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
1576 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
1577 &e1000->tx_ring_phys, &e1000->tx_ring_virt);
1578 if (rc != EOK)
1579 goto error;
1580
1581 memset(e1000->tx_ring_virt, 0,
1582 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
1583
1584 e1000->tx_frame_phys = (uintptr_t *)
1585 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
1586 e1000->tx_frame_virt =
1587 calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
1588
1589 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
1590 rc = ENOMEM;
1591 goto error;
1592 }
1593
1594 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1595 e1000->tx_frame_virt[i] = AS_AREA_ANY;
1596 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
1597 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
1598 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
1599 if (rc != EOK)
1600 goto error;
1601 }
1602
1603 E1000_REG_WRITE(e1000, E1000_TDBAH,
1604 (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
1605 E1000_REG_WRITE(e1000, E1000_TDBAL,
1606 (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
1607
1608 e1000_initialize_tx_registers(e1000);
1609
1610 fibril_mutex_unlock(&e1000->tx_lock);
1611 return EOK;
1612
1613error:
1614 if (e1000->tx_ring_virt != NULL) {
1615 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1616 e1000->tx_ring_virt = NULL;
1617 }
1618
1619 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
1620 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1621 if (e1000->tx_frame_virt[i] != NULL) {
1622 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1623 e1000->tx_frame_phys[i] = 0;
1624 e1000->tx_frame_virt[i] = NULL;
1625 }
1626 }
1627 }
1628
1629 if (e1000->tx_frame_phys != NULL) {
1630 free(e1000->tx_frame_phys);
1631 e1000->tx_frame_phys = NULL;
1632 }
1633
1634 if (e1000->tx_frame_virt != NULL) {
1635 free(e1000->tx_frame_virt);
1636 e1000->tx_frame_virt = NULL;
1637 }
1638
1639 return rc;
1640}
1641
1642/** Uninitialize transmit structure
1643 *
1644 * @param nic NIC data
1645 *
1646 */
1647static void e1000_uninitialize_tx_structure(e1000_t *e1000)
1648{
1649 size_t i;
1650
1651 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
1652 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
1653 e1000->tx_frame_phys[i] = 0;
1654 e1000->tx_frame_virt[i] = NULL;
1655 }
1656
1657 if (e1000->tx_frame_phys != NULL) {
1658 free(e1000->tx_frame_phys);
1659 e1000->tx_frame_phys = NULL;
1660 }
1661
1662 if (e1000->tx_frame_virt != NULL) {
1663 free(e1000->tx_frame_virt);
1664 e1000->tx_frame_virt = NULL;
1665 }
1666
1667 dmamem_unmap_anonymous(e1000->tx_ring_virt);
1668}
1669
1670/** Clear transmit descriptor ring
1671 *
1672 * @param nic NIC data
1673 *
1674 */
1675static void e1000_clear_tx_ring(nic_t *nic)
1676{
1677 /* Write descriptor */
1678 for (unsigned int offset = 0;
1679 offset < E1000_TX_FRAME_COUNT;
1680 offset++)
1681 e1000_clear_tx_descriptor(nic, offset);
1682}
1683
1684/** Enable transmit
1685 *
1686 * @param e1000 E1000 data
1687 *
1688 */
1689static void e1000_enable_tx(e1000_t *e1000)
1690{
1691 /* Set Transmit Enable Bit */
1692 E1000_REG_WRITE(e1000, E1000_TCTL,
1693 E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
1694}
1695
1696/** Disable transmit
1697 *
1698 * @param e1000 E1000 data
1699 *
1700 */
1701static void e1000_disable_tx(e1000_t *e1000)
1702{
1703 /* Clear Transmit Enable Bit */
1704 E1000_REG_WRITE(e1000, E1000_TCTL,
1705 E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
1706}
1707
1708/** Reset E1000 device
1709 *
1710 * @param e1000 The E1000 data
1711 *
1712 */
1713static int e1000_reset(nic_t *nic)
1714{
1715 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1716
1717 E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
1718
1719 /* Wait for the reset */
1720 thread_usleep(20);
1721
1722 /* check if RST_BIT cleared */
1723 if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
1724 return EINVAL;
1725
1726 e1000_initialize_registers(e1000);
1727 e1000_initialize_rx_registers(e1000);
1728 e1000_initialize_tx_registers(e1000);
1729 e1000_fill_mac_from_eeprom(e1000);
1730 e1000_initialize_filters(e1000);
1731 e1000_initialize_vlan(e1000);
1732
1733 return EOK;
1734}
1735
1736/** Activate the device to receive and transmit frames
1737 *
1738 * @param nic NIC driver data
1739 *
1740 * @return EOK if activated successfully
1741 * @return Error code otherwise
1742 *
1743 */
1744static int e1000_on_activating(nic_t *nic)
1745{
1746 assert(nic);
1747
1748 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1749
1750 fibril_mutex_lock(&e1000->rx_lock);
1751 fibril_mutex_lock(&e1000->tx_lock);
1752 fibril_mutex_lock(&e1000->ctrl_lock);
1753
1754 e1000_enable_interrupts(e1000);
1755
1756 int rc = irc_enable_interrupt(e1000->irq);
1757 if (rc != EOK) {
1758 e1000_disable_interrupts(e1000);
1759 fibril_mutex_unlock(&e1000->ctrl_lock);
1760 fibril_mutex_unlock(&e1000->tx_lock);
1761 fibril_mutex_unlock(&e1000->rx_lock);
1762 return rc;
1763 }
1764
1765 e1000_clear_rx_ring(e1000);
1766 e1000_enable_rx(e1000);
1767
1768 e1000_clear_tx_ring(nic);
1769 e1000_enable_tx(e1000);
1770
1771 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1772 ctrl |= CTRL_SLU;
1773 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1774
1775 fibril_mutex_unlock(&e1000->ctrl_lock);
1776 fibril_mutex_unlock(&e1000->tx_lock);
1777 fibril_mutex_unlock(&e1000->rx_lock);
1778
1779 return EOK;
1780}
1781
1782/** Callback for NIC_STATE_DOWN change
1783 *
1784 * @param nic NIC driver data
1785 *
1786 * @return EOK if succeed
1787 * @return Error code otherwise
1788 *
1789 */
1790static int e1000_on_down_unlocked(nic_t *nic)
1791{
1792 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1793
1794 uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
1795 ctrl &= ~CTRL_SLU;
1796 E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
1797
1798 e1000_disable_tx(e1000);
1799 e1000_disable_rx(e1000);
1800
1801 irc_disable_interrupt(e1000->irq);
1802 e1000_disable_interrupts(e1000);
1803
1804 /*
1805 * Wait for the for the end of all data
1806 * transfers to descriptors.
1807 */
1808 thread_usleep(100);
1809
1810 return EOK;
1811}
1812
1813/** Callback for NIC_STATE_DOWN change
1814 *
1815 * @param nic NIC driver data
1816 *
1817 * @return EOK if succeed
1818 * @return Error code otherwise
1819 *
1820 */
1821static int e1000_on_down(nic_t *nic)
1822{
1823 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1824
1825 fibril_mutex_lock(&e1000->rx_lock);
1826 fibril_mutex_lock(&e1000->tx_lock);
1827 fibril_mutex_lock(&e1000->ctrl_lock);
1828
1829 int rc = e1000_on_down_unlocked(nic);
1830
1831 fibril_mutex_unlock(&e1000->ctrl_lock);
1832 fibril_mutex_unlock(&e1000->tx_lock);
1833 fibril_mutex_unlock(&e1000->rx_lock);
1834
1835 return rc;
1836}
1837
1838/** Callback for NIC_STATE_STOPPED change
1839 *
1840 * @param nic NIC driver data
1841 *
1842 * @return EOK if succeed
1843 * @return Error code otherwise
1844 *
1845 */
1846static int e1000_on_stopping(nic_t *nic)
1847{
1848 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
1849
1850 fibril_mutex_lock(&e1000->rx_lock);
1851 fibril_mutex_lock(&e1000->tx_lock);
1852 fibril_mutex_lock(&e1000->ctrl_lock);
1853
1854 int rc = e1000_on_down_unlocked(nic);
1855 if (rc == EOK)
1856 rc = e1000_reset(nic);
1857
1858 fibril_mutex_unlock(&e1000->ctrl_lock);
1859 fibril_mutex_unlock(&e1000->tx_lock);
1860 fibril_mutex_unlock(&e1000->rx_lock);
1861
1862 return rc;
1863}
1864
1865/** Create driver data structure
1866 *
1867 * @return Intialized device data structure or NULL
1868 *
1869 */
1870static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
1871{
1872 nic_t *nic = nic_create_and_bind(dev);
1873 if (!nic)
1874 return NULL;
1875
1876 e1000_t *e1000 = malloc(sizeof(e1000_t));
1877 if (!e1000) {
1878 nic_unbind_and_destroy(dev);
1879 return NULL;
1880 }
1881
1882 memset(e1000, 0, sizeof(e1000_t));
1883
1884 nic_set_specific(nic, e1000);
1885 nic_set_send_frame_handler(nic, e1000_send_frame);
1886 nic_set_state_change_handlers(nic, e1000_on_activating,
1887 e1000_on_down, e1000_on_stopping);
1888 nic_set_filtering_change_handlers(nic,
1889 e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
1890 e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
1891 nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
1892
1893 fibril_mutex_initialize(&e1000->ctrl_lock);
1894 fibril_mutex_initialize(&e1000->rx_lock);
1895 fibril_mutex_initialize(&e1000->tx_lock);
1896 fibril_mutex_initialize(&e1000->eeprom_lock);
1897
1898 return e1000;
1899}
1900
1901/** Delete driver data structure
1902 *
1903 * @param data E1000 device data structure
1904 *
1905 */
1906inline static void e1000_delete_dev_data(ddf_dev_t *dev)
1907{
1908 assert(dev);
1909
1910 if (ddf_dev_data_get(dev) != NULL)
1911 nic_unbind_and_destroy(dev);
1912}
1913
1914/** Clean up the E1000 device structure.
1915 *
1916 * @param dev Device structure.
1917 *
1918 */
1919static void e1000_dev_cleanup(ddf_dev_t *dev)
1920{
1921 assert(dev);
1922
1923 e1000_delete_dev_data(dev);
1924}
1925
1926/** Fill the irq and io_addr part of device data structure
1927 *
1928 * The hw_resources must be obtained before calling this function
1929 *
1930 * @param dev Device structure
1931 * @param hw_resources Hardware resources obtained from the parent device
1932 *
1933 * @return EOK if succeed
1934 * @return Negative error code otherwise
1935 *
1936 */
1937static int e1000_fill_resource_info(ddf_dev_t *dev,
1938 const hw_res_list_parsed_t *hw_resources)
1939{
1940 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
1941
1942 if (hw_resources->irqs.count != 1)
1943 return EINVAL;
1944
1945 e1000->irq = hw_resources->irqs.irqs[0];
1946 e1000->reg_base_phys =
1947 MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
1948
1949 return EOK;
1950}
1951
1952/** Obtain information about hardware resources of the device
1953 *
1954 * The device must be connected to the parent
1955 *
1956 * @param dev Device structure
1957 *
1958 * @return EOK if succeed
1959 * @return Negative error code otherwise
1960 *
1961 */
1962static int e1000_get_resource_info(ddf_dev_t *dev)
1963{
1964 assert(dev != NULL);
1965 assert(NIC_DATA_DEV(dev) != NULL);
1966
1967 hw_res_list_parsed_t hw_res_parsed;
1968 hw_res_list_parsed_init(&hw_res_parsed);
1969
1970 /* Get hw resources form parent driver */
1971 int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
1972 if (rc != EOK)
1973 return rc;
1974
1975 /* Fill resources information to the device */
1976 rc = e1000_fill_resource_info(dev, &hw_res_parsed);
1977 hw_res_list_parsed_clean(&hw_res_parsed);
1978
1979 return rc;
1980}
1981
1982/** Initialize the E1000 device structure
1983 *
1984 * @param dev Device information
1985 *
1986 * @return EOK if succeed
1987 * @return Negative error code otherwise
1988 *
1989 */
1990static int e1000_device_initialize(ddf_dev_t *dev)
1991{
1992 /* Allocate driver data for the device. */
1993 e1000_t *e1000 = e1000_create_dev_data(dev);
1994 if (e1000 == NULL) {
1995 ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
1996 return ENOMEM;
1997 }
1998
1999 /* Obtain and fill hardware resources info */
2000 int rc = e1000_get_resource_info(dev);
2001 if (rc != EOK) {
2002 ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
2003 e1000_dev_cleanup(dev);
2004 return rc;
2005 }
2006
2007 uint16_t device_id;
2008 rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
2009 &device_id);
2010 if (rc != EOK) {
2011 ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
2012 e1000_dev_cleanup(dev);
2013 return rc;
2014 }
2015
2016 e1000_board_t board;
2017 switch (device_id) {
2018 case 0x100e:
2019 case 0x1015:
2020 case 0x1016:
2021 case 0x1017:
2022 board = E1000_82540;
2023 break;
2024 case 0x1013:
2025 case 0x1018:
2026 case 0x1078:
2027 board = E1000_82541;
2028 break;
2029 case 0x1076:
2030 case 0x1077:
2031 case 0x107c:
2032 board = E1000_82541REV2;
2033 break;
2034 case 0x100f:
2035 case 0x1011:
2036 case 0x1026:
2037 case 0x1027:
2038 case 0x1028:
2039 board = E1000_82545;
2040 break;
2041 case 0x1010:
2042 case 0x1012:
2043 case 0x101d:
2044 case 0x1079:
2045 case 0x107a:
2046 case 0x107b:
2047 board = E1000_82546;
2048 break;
2049 case 0x1019:
2050 case 0x101a:
2051 board = E1000_82547;
2052 break;
2053 case 0x10b9:
2054 board = E1000_82572;
2055 break;
2056 case 0x1096:
2057 board = E1000_80003ES2;
2058 break;
2059 default:
2060 ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
2061 device_id);
2062 e1000_dev_cleanup(dev);
2063 return ENOTSUP;
2064 }
2065
2066 switch (board) {
2067 case E1000_82540:
2068 case E1000_82541:
2069 case E1000_82541REV2:
2070 case E1000_82545:
2071 case E1000_82546:
2072 e1000->info.eerd_start = 0x01;
2073 e1000->info.eerd_done = 0x10;
2074 e1000->info.eerd_address_offset = 8;
2075 e1000->info.eerd_data_offset = 16;
2076 break;
2077 case E1000_82547:
2078 case E1000_82572:
2079 case E1000_80003ES2:
2080 e1000->info.eerd_start = 0x01;
2081 e1000->info.eerd_done = 0x02;
2082 e1000->info.eerd_address_offset = 2;
2083 e1000->info.eerd_data_offset = 16;
2084 break;
2085 }
2086
2087 return EOK;
2088}
2089
2090/** Enable the I/O ports of the device.
2091 *
2092 * @param dev E1000 device.
2093 *
2094 * @return EOK if successed
2095 * @return Negative error code otherwise
2096 *
2097 */
2098static int e1000_pio_enable(ddf_dev_t *dev)
2099{
2100 e1000_t *e1000 = DRIVER_DATA_DEV(dev);
2101
2102 int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
2103 &e1000->reg_base_virt);
2104 if (rc != EOK)
2105 return EADDRNOTAVAIL;
2106
2107 return EOK;
2108}
2109
2110/** Probe and initialize the newly added device.
2111 *
2112 * @param dev E1000 device.
2113 *
2114 */
2115int e1000_dev_add(ddf_dev_t *dev)
2116{
2117 ddf_fun_t *fun;
2118 assert(dev);
2119
2120 /* Initialize device structure for E1000 */
2121 int rc = e1000_device_initialize(dev);
2122 if (rc != EOK)
2123 return rc;
2124
2125 /* Device initialization */
2126 nic_t *nic = ddf_dev_data_get(dev);
2127 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2128
2129 /* Map registers */
2130 rc = e1000_pio_enable(dev);
2131 if (rc != EOK)
2132 goto err_destroy;
2133
2134 e1000_initialize_registers(e1000);
2135 rc = e1000_initialize_tx_structure(e1000);
2136 if (rc != EOK)
2137 goto err_pio;
2138
2139 fibril_mutex_lock(&e1000->rx_lock);
2140
2141 e1000_fill_mac_from_eeprom(e1000);
2142 e1000_initialize_filters(e1000);
2143
2144 fibril_mutex_unlock(&e1000->rx_lock);
2145
2146 e1000_initialize_vlan(e1000);
2147
2148 fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
2149 if (fun == NULL)
2150 goto err_tx_structure;
2151 nic_set_ddf_fun(nic, fun);
2152 ddf_fun_set_ops(fun, &e1000_dev_ops);
2153
2154 int irq_cap = e1000_register_int_handler(nic);
2155 if (irq_cap < 0) {
2156 rc = irq_cap;
2157 goto err_fun_create;
2158 }
2159
2160 rc = e1000_initialize_rx_structure(nic);
2161 if (rc != EOK)
2162 goto err_irq;
2163
2164 nic_address_t e1000_address;
2165 e1000_get_address(e1000, &e1000_address);
2166 rc = nic_report_address(nic, &e1000_address);
2167 if (rc != EOK)
2168 goto err_rx_structure;
2169
2170 struct timeval period;
2171 period.tv_sec = 0;
2172 period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
2173 rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
2174 if (rc != EOK)
2175 goto err_rx_structure;
2176
2177 rc = ddf_fun_bind(fun);
2178 if (rc != EOK)
2179 goto err_fun_bind;
2180
2181 rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
2182 if (rc != EOK)
2183 goto err_add_to_cat;
2184
2185 return EOK;
2186
2187err_add_to_cat:
2188 ddf_fun_unbind(fun);
2189err_fun_bind:
2190err_rx_structure:
2191 e1000_uninitialize_rx_structure(nic);
2192err_irq:
2193 unregister_interrupt_handler(dev, irq_cap);
2194err_fun_create:
2195 ddf_fun_destroy(fun);
2196 nic_set_ddf_fun(nic, NULL);
2197err_tx_structure:
2198 e1000_uninitialize_tx_structure(e1000);
2199err_pio:
2200 // TODO: e1000_pio_disable(dev);
2201err_destroy:
2202 e1000_dev_cleanup(dev);
2203 return rc;
2204}
2205
2206/** Read 16-bit value from EEPROM of E1000 adapter
2207 *
2208 * Read using the EERD register.
2209 *
2210 * @param device E1000 device
2211 * @param eeprom_address 8-bit EEPROM address
2212 *
2213 * @return 16-bit value from EEPROM
2214 *
2215 */
2216static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
2217{
2218 fibril_mutex_lock(&e1000->eeprom_lock);
2219
2220 /* Write address and START bit to EERD register */
2221 uint32_t write_data = e1000->info.eerd_start |
2222 (((uint32_t) eeprom_address) <<
2223 e1000->info.eerd_address_offset);
2224 E1000_REG_WRITE(e1000, E1000_EERD, write_data);
2225
2226 uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
2227 while ((eerd & e1000->info.eerd_done) == 0) {
2228 thread_usleep(1);
2229 eerd = E1000_REG_READ(e1000, E1000_EERD);
2230 }
2231
2232 fibril_mutex_unlock(&e1000->eeprom_lock);
2233
2234 return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
2235}
2236
2237/** Get MAC address of the E1000 adapter
2238 *
2239 * @param device E1000 device
2240 * @param address Place to store the address
2241 * @param max_len Maximal addresss length to store
2242 *
2243 * @return EOK if succeed
2244 * @return Negative error code otherwise
2245 *
2246 */
2247static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
2248{
2249 fibril_mutex_lock(&e1000->rx_lock);
2250
2251 uint8_t *mac0_dest = (uint8_t *) address->address;
2252 uint8_t *mac1_dest = (uint8_t *) address->address + 1;
2253 uint8_t *mac2_dest = (uint8_t *) address->address + 2;
2254 uint8_t *mac3_dest = (uint8_t *) address->address + 3;
2255 uint8_t *mac4_dest = (uint8_t *) address->address + 4;
2256 uint8_t *mac5_dest = (uint8_t *) address->address + 5;
2257
2258 uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
2259 uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
2260
2261 *mac0_dest = (uint8_t) ral;
2262 *mac1_dest = (uint8_t) (ral >> 8);
2263 *mac2_dest = (uint8_t) (ral >> 16);
2264 *mac3_dest = (uint8_t) (ral >> 24);
2265 *mac4_dest = (uint8_t) rah;
2266 *mac5_dest = (uint8_t) (rah >> 8);
2267
2268 fibril_mutex_unlock(&e1000->rx_lock);
2269 return EOK;
2270};
2271
2272/** Set card MAC address
2273 *
2274 * @param device E1000 device
2275 * @param address Address
2276 *
2277 * @return EOK if succeed
2278 * @return Negative error code otherwise
2279 */
2280static int e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
2281{
2282 nic_t *nic = NIC_DATA_FUN(fun);
2283 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2284
2285 fibril_mutex_lock(&e1000->rx_lock);
2286 fibril_mutex_lock(&e1000->tx_lock);
2287
2288 int rc = nic_report_address(nic, addr);
2289 if (rc == EOK)
2290 e1000_write_receive_address(e1000, 0, addr, false);
2291
2292 fibril_mutex_unlock(&e1000->tx_lock);
2293 fibril_mutex_unlock(&e1000->rx_lock);
2294
2295 return rc;
2296}
2297
2298static void e1000_eeprom_get_address(e1000_t *e1000,
2299 nic_address_t *address)
2300{
2301 uint16_t *mac0_dest = (uint16_t *) address->address;
2302 uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
2303 uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
2304
2305 *mac0_dest = e1000_eeprom_read(e1000, 0);
2306 *mac2_dest = e1000_eeprom_read(e1000, 1);
2307 *mac4_dest = e1000_eeprom_read(e1000, 2);
2308}
2309
2310/** Send frame
2311 *
2312 * @param nic NIC driver data structure
2313 * @param data Frame data
2314 * @param size Frame size in bytes
2315 *
2316 * @return EOK if succeed
2317 * @return Error code in the case of error
2318 *
2319 */
2320static void e1000_send_frame(nic_t *nic, void *data, size_t size)
2321{
2322 assert(nic);
2323
2324 e1000_t *e1000 = DRIVER_DATA_NIC(nic);
2325 fibril_mutex_lock(&e1000->tx_lock);
2326
2327 uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
2328 e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
2329 (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
2330
2331 bool descriptor_available = false;
2332
2333 /* Descriptor never used */
2334 if (tx_descriptor_addr->length == 0)
2335 descriptor_available = true;
2336
2337 /* Descriptor done */
2338 if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
2339 descriptor_available = true;
2340
2341 if (!descriptor_available) {
2342 /* Frame lost */
2343 fibril_mutex_unlock(&e1000->tx_lock);
2344 return;
2345 }
2346
2347 memcpy(e1000->tx_frame_virt[tdt], data, size);
2348
2349 tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
2350 tx_descriptor_addr->length = size;
2351
2352 /*
2353 * Report status to STATUS.DD (descriptor done),
2354 * add ethernet CRC, end of packet.
2355 */
2356 tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
2357 TXDESCRIPTOR_COMMAND_IFCS |
2358 TXDESCRIPTOR_COMMAND_EOP;
2359
2360 tx_descriptor_addr->checksum_offset = 0;
2361 tx_descriptor_addr->status = 0;
2362 if (e1000->vlan_tag_add) {
2363 tx_descriptor_addr->special = e1000->vlan_tag;
2364 tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
2365 } else
2366 tx_descriptor_addr->special = 0;
2367
2368 tx_descriptor_addr->checksum_start_field = 0;
2369
2370 tdt++;
2371 if (tdt == E1000_TX_FRAME_COUNT)
2372 tdt = 0;
2373
2374 E1000_REG_WRITE(e1000, E1000_TDT, tdt);
2375
2376 fibril_mutex_unlock(&e1000->tx_lock);
2377}
2378
2379int main(void)
2380{
2381 printf("%s: HelenOS E1000 network adapter driver\n", NAME);
2382
2383 if (nic_driver_init(NAME) != EOK)
2384 return 1;
2385
2386 nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
2387 &e1000_nic_iface);
2388
2389 ddf_log_init(NAME);
2390 return ddf_driver_main(&e1000_driver);
2391}
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