| [bf84871] | 1 | /*
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| 2 | * Copyright (c) 2011 Zdenek Bouska
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [1df224c] | 29 | /** @file e1k.c
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| 30 | *
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| 31 | * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
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| [bf84871] | 32 | *
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| 33 | */
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| 34 |
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| [f300523] | 35 | #include <async.h>
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| [bf84871] | 36 | #include <assert.h>
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| 37 | #include <stdio.h>
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| 38 | #include <errno.h>
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| 39 | #include <adt/list.h>
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| 40 | #include <align.h>
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| 41 | #include <byteorder.h>
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| 42 | #include <as.h>
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| [869d936] | 43 | #include <ddi.h>
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| [77c2b02] | 44 | #include <ddf/log.h>
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| [bf84871] | 45 | #include <ddf/interrupt.h>
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| [d51838f] | 46 | #include <device/hw_res.h>
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| [bf84871] | 47 | #include <device/hw_res_parsed.h>
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| [99e8fb7b] | 48 | #include <pci_dev_iface.h>
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| [bf84871] | 49 | #include <nic.h>
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| 50 | #include <ops/nic.h>
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| [1df224c] | 51 | #include "e1k.h"
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| [bf84871] | 52 |
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| [1df224c] | 53 | #define NAME "e1k"
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| [bf84871] | 54 |
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| [9916841] | 55 | #define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
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| [bf84871] | 56 |
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| [ee7f78a] | 57 | /* Must be power of 8 */
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| 58 | #define E1000_RX_FRAME_COUNT 128
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| 59 | #define E1000_TX_FRAME_COUNT 128
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| [bf84871] | 60 |
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| [1df224c] | 61 | #define E1000_RECEIVE_ADDRESS 16
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| [bf84871] | 62 |
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| [1bc35b5] | 63 | /** Maximum sending frame size */
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| [6d8455d] | 64 | #define E1000_MAX_SEND_FRAME_SIZE 2048
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| [321052f7] | 65 | /** Maximum receiving frame size */
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| [1bc35b5] | 66 | #define E1000_MAX_RECEIVE_FRAME_SIZE 2048
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| [bf84871] | 67 |
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| 68 | /** nic_driver_data_t* -> e1000_t* cast */
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| [c4be33a] | 69 | #define DRIVER_DATA_NIC(nic) \
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| 70 | ((e1000_t *) nic_get_specific(nic))
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| [1df224c] | 71 |
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| [56fd7cf] | 72 | /** ddf_fun_t * -> nic_driver_data_t* cast */
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| 73 | #define NIC_DATA_FUN(fun) \
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| [7eb6c96] | 74 | ((nic_t *) ddf_dev_data_get(ddf_fun_get_dev(fun)))
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| [56fd7cf] | 75 |
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| 76 | /** ddf_dev_t * -> nic_driver_data_t* cast */
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| [1df224c] | 77 | #define NIC_DATA_DEV(dev) \
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| [56fd7cf] | 78 | ((nic_t *) ddf_dev_data_get(dev))
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| [1df224c] | 79 |
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| [56fd7cf] | 80 | /** ddf_dev_t * -> e1000_t* cast */
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| [1df224c] | 81 | #define DRIVER_DATA_DEV(dev) \
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| 82 | (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
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| [bf84871] | 83 |
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| [56fd7cf] | 84 | /** ddf_fun_t * -> e1000_t* cast */
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| 85 | #define DRIVER_DATA_FUN(fun) \
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| 86 | (DRIVER_DATA_NIC(NIC_DATA_FUN(fun)))
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| 87 |
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| [1df224c] | 88 | /** Cast pointer to uint64_t
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| 89 | *
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| 90 | * @param ptr Pointer to cast
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| 91 | *
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| 92 | * @return The uint64_t pointer representation.
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| [bf84871] | 93 | *
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| 94 | */
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| [1df224c] | 95 | #define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
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| [bf84871] | 96 |
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| 97 | /** Cast the memaddr part to the void*
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| 98 | *
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| [1df224c] | 99 | * @param memaddr The memaddr value
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| 100 | *
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| [bf84871] | 101 | */
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| [1df224c] | 102 | #define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
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| 103 |
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| [c4be33a] | 104 | #define E1000_REG_BASE(e1000) \
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| 105 | ((e1000)->reg_base_virt)
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| [bf84871] | 106 |
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| [c4be33a] | 107 | #define E1000_REG_ADDR(e1000, reg) \
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| 108 | ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
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| [bf84871] | 109 |
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| [c4be33a] | 110 | #define E1000_REG_READ(e1000, reg) \
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| 111 | (pio_read_32(E1000_REG_ADDR(e1000, reg)))
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| [1df224c] | 112 |
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| [c4be33a] | 113 | #define E1000_REG_WRITE(e1000, reg, value) \
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| 114 | (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
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| [bf84871] | 115 |
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| 116 | /** E1000 device data */
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| [c4be33a] | 117 | typedef struct {
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| [d51838f] | 118 | /** DDF device */
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| 119 | ddf_dev_t *dev;
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| 120 | /** Parent session */
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| 121 | async_sess_t *parent_sess;
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| [77c2b02] | 122 | /** Device configuration */
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| 123 | e1000_info_t info;
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| 124 |
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| [bf84871] | 125 | /** Physical registers base address */
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| [c4be33a] | 126 | void *reg_base_phys;
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| [bf84871] | 127 | /** Virtual registers base address */
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| [c4be33a] | 128 | void *reg_base_virt;
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| 129 |
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| 130 | /** Physical tx ring address */
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| [8442d10] | 131 | uintptr_t tx_ring_phys;
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| [c4be33a] | 132 | /** Virtual tx ring address */
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| 133 | void *tx_ring_virt;
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| 134 |
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| [6d8455d] | 135 | /** Ring of TX frames, physical address */
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| [8442d10] | 136 | uintptr_t *tx_frame_phys;
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| [6d8455d] | 137 | /** Ring of TX frames, virtual address */
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| 138 | void **tx_frame_virt;
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| [c4be33a] | 139 |
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| 140 | /** Physical rx ring address */
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| [8442d10] | 141 | uintptr_t rx_ring_phys;
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| [c4be33a] | 142 | /** Virtual rx ring address */
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| 143 | void *rx_ring_virt;
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| 144 |
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| [1bc35b5] | 145 | /** Ring of RX frames, physical address */
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| [8442d10] | 146 | uintptr_t *rx_frame_phys;
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| [1bc35b5] | 147 | /** Ring of RX frames, virtual address */
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| 148 | void **rx_frame_virt;
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| [c4be33a] | 149 |
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| [bf84871] | 150 | /** VLAN tag */
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| 151 | uint16_t vlan_tag;
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| [c4be33a] | 152 |
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| [1bc35b5] | 153 | /** Add VLAN tag to frame */
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| [1df224c] | 154 | bool vlan_tag_add;
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| [c4be33a] | 155 |
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| [bf84871] | 156 | /** Used unicast Receive Address count */
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| 157 | unsigned int unicast_ra_count;
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| [c4be33a] | 158 |
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| [1df224c] | 159 | /** Used milticast Receive addrress count */
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| [bf84871] | 160 | unsigned int multicast_ra_count;
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| [c4be33a] | 161 |
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| [bf84871] | 162 | /** The irq assigned */
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| 163 | int irq;
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| [c4be33a] | 164 |
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| [bf84871] | 165 | /** Lock for CTRL register */
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| 166 | fibril_mutex_t ctrl_lock;
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| [c4be33a] | 167 |
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| [bf84871] | 168 | /** Lock for receiver */
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| 169 | fibril_mutex_t rx_lock;
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| [c4be33a] | 170 |
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| [bf84871] | 171 | /** Lock for transmitter */
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| 172 | fibril_mutex_t tx_lock;
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| [c4be33a] | 173 |
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| [bf84871] | 174 | /** Lock for EEPROM access */
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| 175 | fibril_mutex_t eeprom_lock;
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| 176 | } e1000_t;
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| 177 |
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| 178 | /** Global mutex for work with shared irq structure */
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| 179 | FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
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| 180 |
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| [5a6cc679] | 181 | static errno_t e1000_get_address(e1000_t *, nic_address_t *);
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| [1df224c] | 182 | static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
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| [5a6cc679] | 183 | static errno_t e1000_set_addr(ddf_fun_t *, const nic_address_t *);
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| [bf84871] | 184 |
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| [5a6cc679] | 185 | static errno_t e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
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| 186 | static errno_t e1000_defective_set_mode(ddf_fun_t *, uint32_t);
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| [bf84871] | 187 |
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| [5a6cc679] | 188 | static errno_t e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
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| 189 | static errno_t e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
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| 190 | static errno_t e1000_get_operation_mode(ddf_fun_t *, int *,
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| [1df224c] | 191 | nic_channel_mode_t *, nic_role_t *);
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| [5a6cc679] | 192 | static errno_t e1000_set_operation_mode(ddf_fun_t *, int,
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| [1df224c] | 193 | nic_channel_mode_t, nic_role_t);
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| [5a6cc679] | 194 | static errno_t e1000_autoneg_enable(ddf_fun_t *, uint32_t);
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| 195 | static errno_t e1000_autoneg_disable(ddf_fun_t *);
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| 196 | static errno_t e1000_autoneg_restart(ddf_fun_t *);
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| [bf84871] | 197 |
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| [5a6cc679] | 198 | static errno_t e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
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| [bf84871] | 199 |
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| 200 | /** Network interface options for E1000 card driver */
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| 201 | static nic_iface_t e1000_nic_iface;
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| 202 |
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| 203 | /** Network interface options for E1000 card driver */
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| 204 | static nic_iface_t e1000_nic_iface = {
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| 205 | .set_address = &e1000_set_addr,
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| 206 | .get_device_info = &e1000_get_device_info,
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| 207 | .get_cable_state = &e1000_get_cable_state,
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| 208 | .get_operation_mode = &e1000_get_operation_mode,
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| 209 | .set_operation_mode = &e1000_set_operation_mode,
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| 210 | .autoneg_enable = &e1000_autoneg_enable,
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| 211 | .autoneg_disable = &e1000_autoneg_disable,
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| 212 | .autoneg_restart = &e1000_autoneg_restart,
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| 213 | .vlan_set_tag = &e1000_vlan_set_tag,
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| 214 | .defective_get_mode = &e1000_defective_get_mode,
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| 215 | .defective_set_mode = &e1000_defective_set_mode,
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| 216 | };
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| 217 |
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| 218 | /** Basic device operations for E1000 driver */
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| 219 | static ddf_dev_ops_t e1000_dev_ops;
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| 220 |
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| [5a6cc679] | 221 | static errno_t e1000_dev_add(ddf_dev_t *);
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| [bf84871] | 222 |
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| 223 | /** Basic driver operations for E1000 driver */
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| 224 | static driver_ops_t e1000_driver_ops = {
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| [9916841] | 225 | .dev_add = e1000_dev_add
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| [bf84871] | 226 | };
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| 227 |
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| 228 | /** Driver structure for E1000 driver */
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| 229 | static driver_t e1000_driver = {
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| 230 | .name = NAME,
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| 231 | .driver_ops = &e1000_driver_ops
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| 232 | };
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| 233 |
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| 234 | /* The default implementation callbacks */
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| [5a6cc679] | 235 | static errno_t e1000_on_activating(nic_t *);
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| 236 | static errno_t e1000_on_stopping(nic_t *);
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| [6d8455d] | 237 | static void e1000_send_frame(nic_t *, void *, size_t);
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| [bf84871] | 238 |
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| [ec52752] | 239 | /** PIO ranges used in the IRQ code. */
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| 240 | irq_pio_range_t e1000_irq_pio_ranges[] = {
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| 241 | {
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| 242 | .base = 0,
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| 243 | .size = PAGE_SIZE, /* XXX */
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| 244 | }
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| 245 | };
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| 246 |
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| [bf84871] | 247 | /** Commands to deal with interrupt
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| 248 | *
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| 249 | */
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| 250 | irq_cmd_t e1000_irq_commands[] = {
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| [1df224c] | 251 | {
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| 252 | /* Get the interrupt status */
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| 253 | .cmd = CMD_PIO_READ_32,
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| 254 | .addr = NULL,
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| 255 | .dstarg = 2
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| 256 | },
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| 257 | {
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| 258 | .cmd = CMD_PREDICATE,
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| 259 | .value = 2,
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| 260 | .srcarg = 2
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| 261 | },
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| 262 | {
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| 263 | /* Disable interrupts until interrupt routine is finished */
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| 264 | .cmd = CMD_PIO_WRITE_32,
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| 265 | .addr = NULL,
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| [c4be33a] | 266 | .value = 0xffffffff
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| [1df224c] | 267 | },
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| 268 | {
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| 269 | .cmd = CMD_ACCEPT
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| 270 | }
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| [bf84871] | 271 | };
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| 272 |
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| 273 | /** Interrupt code definition */
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| 274 | irq_code_t e1000_irq_code = {
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| [ec52752] | 275 | .rangecount = sizeof(e1000_irq_pio_ranges) /
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| 276 | sizeof(irq_pio_range_t),
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| 277 | .ranges = e1000_irq_pio_ranges,
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| [1df224c] | 278 | .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
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| [bf84871] | 279 | .cmds = e1000_irq_commands
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| 280 | };
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| 281 |
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| 282 | /** Get the device information
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| 283 | *
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| [1df224c] | 284 | * @param dev NIC device
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| 285 | * @param info Information to fill
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| 286 | *
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| 287 | * @return EOK
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| 288 | *
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| [bf84871] | 289 | */
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| [5a6cc679] | 290 | static errno_t e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
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| [bf84871] | 291 | {
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| 292 | assert(dev);
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| 293 | assert(info);
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| [1df224c] | 294 |
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| [acdb5bac] | 295 | memset(info, 0, sizeof(nic_device_info_t));
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| [1df224c] | 296 |
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| 297 | info->vendor_id = 0x8086;
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| 298 | str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
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| 299 | "Intel Corporation");
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| 300 | str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
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| 301 | "Intel Pro");
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| 302 |
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| [bf84871] | 303 | info->ethernet_support[ETH_10M] = ETH_10BASE_T;
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| 304 | info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
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| 305 | info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
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| [1df224c] | 306 |
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| [bf84871] | 307 | return EOK;
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| 308 | }
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| 309 |
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| 310 | /** Check the cable state
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| 311 | *
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| [1df224c] | 312 | * @param[in] dev device
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| 313 | * @param[out] state state to fill
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| 314 | *
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| 315 | * @return EOK
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| 316 | *
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| [bf84871] | 317 | */
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| [5a6cc679] | 318 | static errno_t e1000_get_cable_state(ddf_fun_t *fun, nic_cable_state_t *state)
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| [bf84871] | 319 | {
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| [56fd7cf] | 320 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
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| [c4be33a] | 321 | if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
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| [bf84871] | 322 | *state = NIC_CS_PLUGGED;
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| [1df224c] | 323 | else
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| [bf84871] | 324 | *state = NIC_CS_UNPLUGGED;
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| [1df224c] | 325 |
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| [bf84871] | 326 | return EOK;
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| 327 | }
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| 328 |
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| [1df224c] | 329 | static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
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| 330 | {
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| [bf84871] | 331 | return useconds * 4;
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| 332 | }
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| 333 |
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| 334 | /** Get operation mode of the device
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| [1df224c] | 335 | *
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| [bf84871] | 336 | */
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| [5a6cc679] | 337 | static errno_t e1000_get_operation_mode(ddf_fun_t *fun, int *speed,
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| [bf84871] | 338 | nic_channel_mode_t *duplex, nic_role_t *role)
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| 339 | {
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| [56fd7cf] | 340 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
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| [c4be33a] | 341 | uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
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| [1df224c] | 342 |
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|---|
| 343 | if (status & STATUS_FD)
|
|---|
| [bf84871] | 344 | *duplex = NIC_CM_FULL_DUPLEX;
|
|---|
| [1df224c] | 345 | else
|
|---|
| [bf84871] | 346 | *duplex = NIC_CM_HALF_DUPLEX;
|
|---|
| [1df224c] | 347 |
|
|---|
| 348 | uint32_t speed_bits =
|
|---|
| 349 | (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
|
|---|
| 350 |
|
|---|
| 351 | if (speed_bits == STATUS_SPEED_10)
|
|---|
| [bf84871] | 352 | *speed = 10;
|
|---|
| [1df224c] | 353 | else if (speed_bits == STATUS_SPEED_100)
|
|---|
| [bf84871] | 354 | *speed = 100;
|
|---|
| [1df224c] | 355 | else if ((speed_bits == STATUS_SPEED_1000A) ||
|
|---|
| 356 | (speed_bits == STATUS_SPEED_1000B))
|
|---|
| [bf84871] | 357 | *speed = 1000;
|
|---|
| [1df224c] | 358 |
|
|---|
| [bf84871] | 359 | *role = NIC_ROLE_UNKNOWN;
|
|---|
| 360 | return EOK;
|
|---|
| 361 | }
|
|---|
| 362 |
|
|---|
| [c4be33a] | 363 | static void e1000_link_restart(e1000_t *e1000)
|
|---|
| [bf84871] | 364 | {
|
|---|
| [c4be33a] | 365 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 366 |
|
|---|
| [c4be33a] | 367 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [bf84871] | 368 |
|
|---|
| 369 | if (ctrl & CTRL_SLU) {
|
|---|
| 370 | ctrl &= ~(CTRL_SLU);
|
|---|
| [8974294] | 371 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [c4be33a] | 372 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [8974294] | 373 |
|
|---|
| [f300523] | 374 | async_usleep(10);
|
|---|
| [8974294] | 375 |
|
|---|
| [c4be33a] | 376 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [8974294] | 377 | ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [bf84871] | 378 | ctrl |= CTRL_SLU;
|
|---|
| [8974294] | 379 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [bf84871] | 380 | }
|
|---|
| [1df224c] | 381 |
|
|---|
| [c4be33a] | 382 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [bf84871] | 383 | }
|
|---|
| 384 |
|
|---|
| 385 | /** Set operation mode of the device
|
|---|
| 386 | *
|
|---|
| 387 | */
|
|---|
| [5a6cc679] | 388 | static errno_t e1000_set_operation_mode(ddf_fun_t *fun, int speed,
|
|---|
| [bf84871] | 389 | nic_channel_mode_t duplex, nic_role_t role)
|
|---|
| 390 | {
|
|---|
| [1df224c] | 391 | if ((speed != 10) && (speed != 100) && (speed != 1000))
|
|---|
| [bf84871] | 392 | return EINVAL;
|
|---|
| [1df224c] | 393 |
|
|---|
| 394 | if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
|
|---|
| [bf84871] | 395 | return EINVAL;
|
|---|
| [1df224c] | 396 |
|
|---|
| [56fd7cf] | 397 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [1df224c] | 398 |
|
|---|
| [c4be33a] | 399 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| 400 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [1df224c] | 401 |
|
|---|
| [bf84871] | 402 | ctrl |= CTRL_FRCSPD;
|
|---|
| 403 | ctrl |= CTRL_FRCDPLX;
|
|---|
| 404 | ctrl &= ~(CTRL_ASDE);
|
|---|
| [1df224c] | 405 |
|
|---|
| 406 | if (duplex == NIC_CM_FULL_DUPLEX)
|
|---|
| [bf84871] | 407 | ctrl |= CTRL_FD;
|
|---|
| [1df224c] | 408 | else
|
|---|
| [bf84871] | 409 | ctrl &= ~(CTRL_FD);
|
|---|
| 410 |
|
|---|
| 411 | ctrl &= ~(CTRL_SPEED_MASK);
|
|---|
| [1df224c] | 412 | if (speed == 1000)
|
|---|
| [bf84871] | 413 | ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
|
|---|
| [1df224c] | 414 | else if (speed == 100)
|
|---|
| [bf84871] | 415 | ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
|
|---|
| [1df224c] | 416 | else
|
|---|
| [bf84871] | 417 | ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
|
|---|
| [1df224c] | 418 |
|
|---|
| [c4be33a] | 419 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [1df224c] | 420 |
|
|---|
| [c4be33a] | 421 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 422 |
|
|---|
| [c4be33a] | 423 | e1000_link_restart(e1000);
|
|---|
| [1df224c] | 424 |
|
|---|
| [bf84871] | 425 | return EOK;
|
|---|
| 426 | }
|
|---|
| 427 |
|
|---|
| [1df224c] | 428 | /** Enable auto-negotiation
|
|---|
| 429 | *
|
|---|
| 430 | * @param dev Device to update
|
|---|
| 431 | * @param advertisement Ignored on E1000
|
|---|
| 432 | *
|
|---|
| 433 | * @return EOK if advertisement mode set successfully
|
|---|
| [bf84871] | 434 | *
|
|---|
| 435 | */
|
|---|
| [5a6cc679] | 436 | static errno_t e1000_autoneg_enable(ddf_fun_t *fun, uint32_t advertisement)
|
|---|
| [bf84871] | 437 | {
|
|---|
| [56fd7cf] | 438 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [1df224c] | 439 |
|
|---|
| [c4be33a] | 440 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 441 |
|
|---|
| [c4be33a] | 442 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [1df224c] | 443 |
|
|---|
| [bf84871] | 444 | ctrl &= ~(CTRL_FRCSPD);
|
|---|
| 445 | ctrl &= ~(CTRL_FRCDPLX);
|
|---|
| 446 | ctrl |= CTRL_ASDE;
|
|---|
| [1df224c] | 447 |
|
|---|
| [c4be33a] | 448 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [1df224c] | 449 |
|
|---|
| [c4be33a] | 450 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 451 |
|
|---|
| [c4be33a] | 452 | e1000_link_restart(e1000);
|
|---|
| [1df224c] | 453 |
|
|---|
| [bf84871] | 454 | return EOK;
|
|---|
| 455 | }
|
|---|
| 456 |
|
|---|
| [1df224c] | 457 | /** Disable auto-negotiation
|
|---|
| 458 | *
|
|---|
| 459 | * @param dev Device to update
|
|---|
| 460 | *
|
|---|
| 461 | * @return EOK
|
|---|
| [bf84871] | 462 | *
|
|---|
| 463 | */
|
|---|
| [5a6cc679] | 464 | static errno_t e1000_autoneg_disable(ddf_fun_t *fun)
|
|---|
| [bf84871] | 465 | {
|
|---|
| [56fd7cf] | 466 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [1df224c] | 467 |
|
|---|
| [c4be33a] | 468 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 469 |
|
|---|
| [c4be33a] | 470 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [1df224c] | 471 |
|
|---|
| [bf84871] | 472 | ctrl |= CTRL_FRCSPD;
|
|---|
| 473 | ctrl |= CTRL_FRCDPLX;
|
|---|
| 474 | ctrl &= ~(CTRL_ASDE);
|
|---|
| [1df224c] | 475 |
|
|---|
| [c4be33a] | 476 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [1df224c] | 477 |
|
|---|
| [c4be33a] | 478 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 479 |
|
|---|
| [c4be33a] | 480 | e1000_link_restart(e1000);
|
|---|
| [1df224c] | 481 |
|
|---|
| [bf84871] | 482 | return EOK;
|
|---|
| 483 | }
|
|---|
| 484 |
|
|---|
| [1df224c] | 485 | /** Restart auto-negotiation
|
|---|
| 486 | *
|
|---|
| 487 | * @param dev Device to update
|
|---|
| 488 | *
|
|---|
| 489 | * @return EOK if advertisement mode set successfully
|
|---|
| [bf84871] | 490 | *
|
|---|
| 491 | */
|
|---|
| [5a6cc679] | 492 | static errno_t e1000_autoneg_restart(ddf_fun_t *dev)
|
|---|
| [bf84871] | 493 | {
|
|---|
| 494 | return e1000_autoneg_enable(dev, 0);
|
|---|
| 495 | }
|
|---|
| 496 |
|
|---|
| [1bc35b5] | 497 | /** Get state of acceptance of weird frames
|
|---|
| [bf84871] | 498 | *
|
|---|
| [1df224c] | 499 | * @param device Device to check
|
|---|
| 500 | * @param[out] mode Current mode
|
|---|
| 501 | *
|
|---|
| [bf84871] | 502 | */
|
|---|
| [5a6cc679] | 503 | static errno_t e1000_defective_get_mode(ddf_fun_t *fun, uint32_t *mode)
|
|---|
| [bf84871] | 504 | {
|
|---|
| [56fd7cf] | 505 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [1df224c] | 506 |
|
|---|
| [bf84871] | 507 | *mode = 0;
|
|---|
| [c4be33a] | 508 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [1df224c] | 509 | if (rctl & RCTL_SBP)
|
|---|
| [bf84871] | 510 | *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
|
|---|
| [1df224c] | 511 |
|
|---|
| [bf84871] | 512 | return EOK;
|
|---|
| 513 | };
|
|---|
| 514 |
|
|---|
| [1bc35b5] | 515 | /** Set acceptance of weird frames
|
|---|
| [bf84871] | 516 | *
|
|---|
| [1df224c] | 517 | * @param device Device to update
|
|---|
| 518 | * @param mode Mode to set
|
|---|
| 519 | *
|
|---|
| 520 | * @return ENOTSUP if the mode is not supported
|
|---|
| 521 | * @return EOK of mode was set
|
|---|
| 522 | *
|
|---|
| [bf84871] | 523 | */
|
|---|
| [5a6cc679] | 524 | static errno_t e1000_defective_set_mode(ddf_fun_t *fun, uint32_t mode)
|
|---|
| [bf84871] | 525 | {
|
|---|
| [56fd7cf] | 526 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [5a6cc679] | 527 | errno_t rc = EOK;
|
|---|
| [1df224c] | 528 |
|
|---|
| [c4be33a] | 529 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 530 |
|
|---|
| [c4be33a] | 531 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 532 | bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
|
|---|
| 533 | bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
|
|---|
| [1df224c] | 534 |
|
|---|
| 535 | if (short_mode && bad_mode)
|
|---|
| [bf84871] | 536 | rctl |= RCTL_SBP;
|
|---|
| [1df224c] | 537 | else if ((!short_mode) && (!bad_mode))
|
|---|
| [bf84871] | 538 | rctl &= ~RCTL_SBP;
|
|---|
| [1df224c] | 539 | else
|
|---|
| [bf84871] | 540 | rc = ENOTSUP;
|
|---|
| [1df224c] | 541 |
|
|---|
| [c4be33a] | 542 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [1df224c] | 543 |
|
|---|
| [c4be33a] | 544 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 545 | return rc;
|
|---|
| 546 | };
|
|---|
| 547 |
|
|---|
| 548 | /** Write receive address to RA registr
|
|---|
| 549 | *
|
|---|
| [c4be33a] | 550 | * @param e1000 E1000 data structure
|
|---|
| [1df224c] | 551 | * @param position RA register position
|
|---|
| 552 | * @param address Ethernet address
|
|---|
| 553 | * @param set_av_bit Set the Addtess Valid bit
|
|---|
| 554 | *
|
|---|
| [bf84871] | 555 | */
|
|---|
| [c4be33a] | 556 | static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
|
|---|
| 557 | const nic_address_t * address, bool set_av_bit)
|
|---|
| [1df224c] | 558 | {
|
|---|
| 559 | uint8_t *mac0 = (uint8_t *) address->address;
|
|---|
| 560 | uint8_t *mac1 = (uint8_t *) address->address + 1;
|
|---|
| 561 | uint8_t *mac2 = (uint8_t *) address->address + 2;
|
|---|
| 562 | uint8_t *mac3 = (uint8_t *) address->address + 3;
|
|---|
| 563 | uint8_t *mac4 = (uint8_t *) address->address + 4;
|
|---|
| 564 | uint8_t *mac5 = (uint8_t *) address->address + 5;
|
|---|
| 565 |
|
|---|
| [bf84871] | 566 | uint32_t rah;
|
|---|
| 567 | uint32_t ral;
|
|---|
| [1df224c] | 568 |
|
|---|
| [bf84871] | 569 | ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
|
|---|
| 570 | rah = ((*mac5) << 8) | ((*mac4));
|
|---|
| [1df224c] | 571 |
|
|---|
| 572 | if (set_av_bit)
|
|---|
| [bf84871] | 573 | rah |= RAH_AV;
|
|---|
| [1df224c] | 574 | else
|
|---|
| [c4be33a] | 575 | rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
|
|---|
| [1df224c] | 576 |
|
|---|
| [c4be33a] | 577 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
|
|---|
| 578 | E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
|
|---|
| [bf84871] | 579 | }
|
|---|
| 580 |
|
|---|
| 581 | /** Disable receive address in RA registr
|
|---|
| 582 | *
|
|---|
| [1df224c] | 583 | * Clear Address Valid bit
|
|---|
| 584 | *
|
|---|
| [c4be33a] | 585 | * @param e1000 E1000 data structure
|
|---|
| 586 | * @param position RA register position
|
|---|
| [1df224c] | 587 | *
|
|---|
| [bf84871] | 588 | */
|
|---|
| [c4be33a] | 589 | static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
|
|---|
| [bf84871] | 590 | {
|
|---|
| [c4be33a] | 591 | uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
|
|---|
| [bf84871] | 592 | rah = rah & ~RAH_AV;
|
|---|
| [c4be33a] | 593 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
|
|---|
| [bf84871] | 594 | }
|
|---|
| 595 |
|
|---|
| [1df224c] | 596 | /** Clear all unicast addresses from RA registers
|
|---|
| 597 | *
|
|---|
| [c4be33a] | 598 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 599 | *
|
|---|
| 600 | */
|
|---|
| [c4be33a] | 601 | static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
|
|---|
| [bf84871] | 602 | {
|
|---|
| [1df224c] | 603 | for (unsigned int ra_num = 1;
|
|---|
| [c4be33a] | 604 | ra_num <= e1000->unicast_ra_count;
|
|---|
| [1df224c] | 605 | ra_num++)
|
|---|
| [c4be33a] | 606 | e1000_disable_receive_address(e1000, ra_num);
|
|---|
| [1df224c] | 607 |
|
|---|
| [c4be33a] | 608 | e1000->unicast_ra_count = 0;
|
|---|
| [bf84871] | 609 | }
|
|---|
| 610 |
|
|---|
| [1df224c] | 611 | /** Clear all multicast addresses from RA registers
|
|---|
| 612 | *
|
|---|
| [c4be33a] | 613 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 614 | *
|
|---|
| 615 | */
|
|---|
| [c4be33a] | 616 | static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
|
|---|
| [bf84871] | 617 | {
|
|---|
| [1df224c] | 618 | unsigned int first_multicast_ra_num =
|
|---|
| [c4be33a] | 619 | E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
|
|---|
| [1df224c] | 620 |
|
|---|
| 621 | for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
|
|---|
| 622 | ra_num >= first_multicast_ra_num;
|
|---|
| 623 | ra_num--)
|
|---|
| [c4be33a] | 624 | e1000_disable_receive_address(e1000, ra_num);
|
|---|
| [1df224c] | 625 |
|
|---|
| [c4be33a] | 626 | e1000->multicast_ra_count = 0;
|
|---|
| [bf84871] | 627 | }
|
|---|
| 628 |
|
|---|
| [1df224c] | 629 | /** Return receive address filter positions count usable for unicast
|
|---|
| 630 | *
|
|---|
| [c4be33a] | 631 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 632 | *
|
|---|
| 633 | * @return receive address filter positions count usable for unicast
|
|---|
| [1df224c] | 634 | *
|
|---|
| [bf84871] | 635 | */
|
|---|
| [c4be33a] | 636 | static unsigned int get_free_unicast_address_count(e1000_t *e1000)
|
|---|
| [bf84871] | 637 | {
|
|---|
| [c4be33a] | 638 | return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
|
|---|
| [bf84871] | 639 | }
|
|---|
| 640 |
|
|---|
| [1df224c] | 641 | /** Return receive address filter positions count usable for multicast
|
|---|
| 642 | *
|
|---|
| [c4be33a] | 643 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 644 | *
|
|---|
| 645 | * @return receive address filter positions count usable for multicast
|
|---|
| [1df224c] | 646 | *
|
|---|
| [bf84871] | 647 | */
|
|---|
| [c4be33a] | 648 | static unsigned int get_free_multicast_address_count(e1000_t *e1000)
|
|---|
| [bf84871] | 649 | {
|
|---|
| [c4be33a] | 650 | return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
|
|---|
| [bf84871] | 651 | }
|
|---|
| 652 |
|
|---|
| [1df224c] | 653 | /** Write unicast receive addresses to receive address filter registers
|
|---|
| 654 | *
|
|---|
| [c4be33a] | 655 | * @param e1000 E1000 data structure
|
|---|
| 656 | * @param addr Pointer to address array
|
|---|
| 657 | * @param addr_cnt Address array count
|
|---|
| [bf84871] | 658 | *
|
|---|
| 659 | */
|
|---|
| [c4be33a] | 660 | static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
|
|---|
| [1df224c] | 661 | const nic_address_t *addr, size_t addr_cnt)
|
|---|
| [bf84871] | 662 | {
|
|---|
| [c4be33a] | 663 | assert(addr_cnt <= get_free_unicast_address_count(e1000));
|
|---|
| [1df224c] | 664 |
|
|---|
| 665 | nic_address_t *addr_iterator = (nic_address_t *) addr;
|
|---|
| 666 |
|
|---|
| 667 | /* ra_num = 0 is primary address */
|
|---|
| 668 | for (unsigned int ra_num = 1;
|
|---|
| 669 | ra_num <= addr_cnt;
|
|---|
| 670 | ra_num++) {
|
|---|
| [c4be33a] | 671 | e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
|
|---|
| [bf84871] | 672 | addr_iterator++;
|
|---|
| 673 | }
|
|---|
| 674 | }
|
|---|
| 675 |
|
|---|
| [1df224c] | 676 | /** Write multicast receive addresses to receive address filter registers
|
|---|
| 677 | *
|
|---|
| [c4be33a] | 678 | * @param e1000 E1000 data structure
|
|---|
| 679 | * @param addr Pointer to address array
|
|---|
| 680 | * @param addr_cnt Address array count
|
|---|
| [bf84871] | 681 | *
|
|---|
| 682 | */
|
|---|
| [c4be33a] | 683 | static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
|
|---|
| [1df224c] | 684 | const nic_address_t *addr, size_t addr_cnt)
|
|---|
| [bf84871] | 685 | {
|
|---|
| [c4be33a] | 686 | assert(addr_cnt <= get_free_multicast_address_count(e1000));
|
|---|
| [1df224c] | 687 |
|
|---|
| 688 | nic_address_t *addr_iterator = (nic_address_t *) addr;
|
|---|
| 689 |
|
|---|
| [bf84871] | 690 | unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
|
|---|
| [1df224c] | 691 | for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
|
|---|
| 692 | ra_num >= first_multicast_ra_num;
|
|---|
| [9916841] | 693 | ra_num--) {
|
|---|
| [c4be33a] | 694 | e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
|
|---|
| [bf84871] | 695 | addr_iterator++;
|
|---|
| 696 | }
|
|---|
| 697 | }
|
|---|
| 698 |
|
|---|
| [1bc35b5] | 699 | /** Disable receiving frames for default address
|
|---|
| [1df224c] | 700 | *
|
|---|
| [c4be33a] | 701 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 702 | *
|
|---|
| 703 | */
|
|---|
| [c4be33a] | 704 | static void disable_ra0_address_filter(e1000_t *e1000)
|
|---|
| [bf84871] | 705 | {
|
|---|
| [c4be33a] | 706 | uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
|---|
| [bf84871] | 707 | rah0 = rah0 & ~RAH_AV;
|
|---|
| [c4be33a] | 708 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
|
|---|
| [bf84871] | 709 | }
|
|---|
| 710 |
|
|---|
| [1bc35b5] | 711 | /** Enable receiving frames for default address
|
|---|
| [1df224c] | 712 | *
|
|---|
| [c4be33a] | 713 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 714 | *
|
|---|
| 715 | */
|
|---|
| [c4be33a] | 716 | static void enable_ra0_address_filter(e1000_t *e1000)
|
|---|
| [bf84871] | 717 | {
|
|---|
| [c4be33a] | 718 | uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
|---|
| [bf84871] | 719 | rah0 = rah0 | RAH_AV;
|
|---|
| [c4be33a] | 720 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
|
|---|
| [bf84871] | 721 | }
|
|---|
| 722 |
|
|---|
| [1df224c] | 723 | /** Disable unicast promiscuous mode
|
|---|
| 724 | *
|
|---|
| [c4be33a] | 725 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 726 | *
|
|---|
| 727 | */
|
|---|
| [c4be33a] | 728 | static void e1000_disable_unicast_promisc(e1000_t *e1000)
|
|---|
| [bf84871] | 729 | {
|
|---|
| [c4be33a] | 730 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 731 | rctl = rctl & ~RCTL_UPE;
|
|---|
| [c4be33a] | 732 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 733 | }
|
|---|
| 734 |
|
|---|
| [1df224c] | 735 | /** Enable unicast promiscuous mode
|
|---|
| 736 | *
|
|---|
| [c4be33a] | 737 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 738 | *
|
|---|
| 739 | */
|
|---|
| [c4be33a] | 740 | static void e1000_enable_unicast_promisc(e1000_t *e1000)
|
|---|
| [bf84871] | 741 | {
|
|---|
| [c4be33a] | 742 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 743 | rctl = rctl | RCTL_UPE;
|
|---|
| [c4be33a] | 744 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 745 | }
|
|---|
| 746 |
|
|---|
| [1df224c] | 747 | /** Disable multicast promiscuous mode
|
|---|
| 748 | *
|
|---|
| [c4be33a] | 749 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 750 | *
|
|---|
| 751 | */
|
|---|
| [c4be33a] | 752 | static void e1000_disable_multicast_promisc(e1000_t *e1000)
|
|---|
| [bf84871] | 753 | {
|
|---|
| [c4be33a] | 754 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 755 | rctl = rctl & ~RCTL_MPE;
|
|---|
| [c4be33a] | 756 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 757 | }
|
|---|
| 758 |
|
|---|
| [1df224c] | 759 | /** Enable multicast promiscuous mode
|
|---|
| 760 | *
|
|---|
| [c4be33a] | 761 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 762 | *
|
|---|
| 763 | */
|
|---|
| [c4be33a] | 764 | static void e1000_enable_multicast_promisc(e1000_t *e1000)
|
|---|
| [bf84871] | 765 | {
|
|---|
| [c4be33a] | 766 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 767 | rctl = rctl | RCTL_MPE;
|
|---|
| [c4be33a] | 768 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 769 | }
|
|---|
| 770 |
|
|---|
| [1bc35b5] | 771 | /** Enable accepting of broadcast frames
|
|---|
| [1df224c] | 772 | *
|
|---|
| [c4be33a] | 773 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 774 | *
|
|---|
| 775 | */
|
|---|
| [c4be33a] | 776 | static void e1000_enable_broadcast_accept(e1000_t *e1000)
|
|---|
| [bf84871] | 777 | {
|
|---|
| [c4be33a] | 778 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 779 | rctl = rctl | RCTL_BAM;
|
|---|
| [c4be33a] | 780 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 781 | }
|
|---|
| 782 |
|
|---|
| [1bc35b5] | 783 | /** Disable accepting of broadcast frames
|
|---|
| [1df224c] | 784 | *
|
|---|
| [c4be33a] | 785 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 786 | *
|
|---|
| 787 | */
|
|---|
| [c4be33a] | 788 | static void e1000_disable_broadcast_accept(e1000_t *e1000)
|
|---|
| [bf84871] | 789 | {
|
|---|
| [c4be33a] | 790 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 791 | rctl = rctl & ~RCTL_BAM;
|
|---|
| [c4be33a] | 792 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 793 | }
|
|---|
| 794 |
|
|---|
| [1df224c] | 795 | /** Enable VLAN filtering according to VFTA registers
|
|---|
| 796 | *
|
|---|
| [c4be33a] | 797 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 798 | *
|
|---|
| 799 | */
|
|---|
| [c4be33a] | 800 | static void e1000_enable_vlan_filter(e1000_t *e1000)
|
|---|
| [bf84871] | 801 | {
|
|---|
| [c4be33a] | 802 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 803 | rctl = rctl | RCTL_VFE;
|
|---|
| [c4be33a] | 804 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 805 | }
|
|---|
| 806 |
|
|---|
| [1df224c] | 807 | /** Disable VLAN filtering
|
|---|
| 808 | *
|
|---|
| [c4be33a] | 809 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 810 | *
|
|---|
| 811 | */
|
|---|
| [c4be33a] | 812 | static void e1000_disable_vlan_filter(e1000_t *e1000)
|
|---|
| [bf84871] | 813 | {
|
|---|
| [c4be33a] | 814 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
|---|
| [bf84871] | 815 | rctl = rctl & ~RCTL_VFE;
|
|---|
| [c4be33a] | 816 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
|---|
| [bf84871] | 817 | }
|
|---|
| 818 |
|
|---|
| [1bc35b5] | 819 | /** Set multicast frames acceptance mode
|
|---|
| [bf84871] | 820 | *
|
|---|
| [c4be33a] | 821 | * @param nic NIC device to update
|
|---|
| [1df224c] | 822 | * @param mode Mode to set
|
|---|
| 823 | * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
|
|---|
| 824 | * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
|
|---|
| 825 | *
|
|---|
| 826 | * @return EOK
|
|---|
| [bf84871] | 827 | *
|
|---|
| 828 | */
|
|---|
| [5a6cc679] | 829 | static errno_t e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
|
|---|
| [c4be33a] | 830 | const nic_address_t *addr, size_t addr_cnt)
|
|---|
| [bf84871] | 831 | {
|
|---|
| [c4be33a] | 832 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [5a6cc679] | 833 | errno_t rc = EOK;
|
|---|
| [1df224c] | 834 |
|
|---|
| [c4be33a] | 835 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 836 |
|
|---|
| [bf84871] | 837 | switch (mode) {
|
|---|
| 838 | case NIC_MULTICAST_BLOCKED:
|
|---|
| [c4be33a] | 839 | e1000_clear_multicast_receive_addresses(e1000);
|
|---|
| 840 | e1000_disable_multicast_promisc(e1000);
|
|---|
| 841 | nic_report_hw_filtering(nic, -1, 1, -1);
|
|---|
| [bf84871] | 842 | break;
|
|---|
| 843 | case NIC_MULTICAST_LIST:
|
|---|
| [c4be33a] | 844 | e1000_clear_multicast_receive_addresses(e1000);
|
|---|
| 845 | if (addr_cnt > get_free_multicast_address_count(e1000)) {
|
|---|
| [1df224c] | 846 | /*
|
|---|
| 847 | * Future work: fill MTA table
|
|---|
| 848 | * Not strictly neccessary, it only saves some compares
|
|---|
| 849 | * in the NIC library.
|
|---|
| 850 | */
|
|---|
| [c4be33a] | 851 | e1000_enable_multicast_promisc(e1000);
|
|---|
| 852 | nic_report_hw_filtering(nic, -1, 0, -1);
|
|---|
| [bf84871] | 853 | } else {
|
|---|
| [c4be33a] | 854 | e1000_disable_multicast_promisc(e1000);
|
|---|
| 855 | e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
|
|---|
| 856 | nic_report_hw_filtering(nic, -1, 1, -1);
|
|---|
| [bf84871] | 857 | }
|
|---|
| 858 | break;
|
|---|
| 859 | case NIC_MULTICAST_PROMISC:
|
|---|
| [c4be33a] | 860 | e1000_enable_multicast_promisc(e1000);
|
|---|
| 861 | e1000_clear_multicast_receive_addresses(e1000);
|
|---|
| 862 | nic_report_hw_filtering(nic, -1, 1, -1);
|
|---|
| [bf84871] | 863 | break;
|
|---|
| 864 | default:
|
|---|
| 865 | rc = ENOTSUP;
|
|---|
| 866 | break;
|
|---|
| 867 | }
|
|---|
| [1df224c] | 868 |
|
|---|
| [c4be33a] | 869 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 870 | return rc;
|
|---|
| 871 | }
|
|---|
| [1df224c] | 872 |
|
|---|
| [1bc35b5] | 873 | /** Set unicast frames acceptance mode
|
|---|
| [bf84871] | 874 | *
|
|---|
| [c4be33a] | 875 | * @param nic NIC device to update
|
|---|
| [1df224c] | 876 | * @param mode Mode to set
|
|---|
| 877 | * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
|
|---|
| 878 | * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
|
|---|
| 879 | *
|
|---|
| 880 | * @return EOK
|
|---|
| [bf84871] | 881 | *
|
|---|
| 882 | */
|
|---|
| [5a6cc679] | 883 | static errno_t e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
|
|---|
| [c4be33a] | 884 | const nic_address_t *addr, size_t addr_cnt)
|
|---|
| [bf84871] | 885 | {
|
|---|
| [c4be33a] | 886 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [5a6cc679] | 887 | errno_t rc = EOK;
|
|---|
| [1df224c] | 888 |
|
|---|
| [c4be33a] | 889 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 890 |
|
|---|
| [bf84871] | 891 | switch (mode) {
|
|---|
| 892 | case NIC_UNICAST_BLOCKED:
|
|---|
| [c4be33a] | 893 | disable_ra0_address_filter(e1000);
|
|---|
| 894 | e1000_clear_unicast_receive_addresses(e1000);
|
|---|
| 895 | e1000_disable_unicast_promisc(e1000);
|
|---|
| 896 | nic_report_hw_filtering(nic, 1, -1, -1);
|
|---|
| [bf84871] | 897 | break;
|
|---|
| 898 | case NIC_UNICAST_DEFAULT:
|
|---|
| [c4be33a] | 899 | enable_ra0_address_filter(e1000);
|
|---|
| 900 | e1000_clear_unicast_receive_addresses(e1000);
|
|---|
| 901 | e1000_disable_unicast_promisc(e1000);
|
|---|
| 902 | nic_report_hw_filtering(nic, 1, -1, -1);
|
|---|
| [bf84871] | 903 | break;
|
|---|
| 904 | case NIC_UNICAST_LIST:
|
|---|
| [c4be33a] | 905 | enable_ra0_address_filter(e1000);
|
|---|
| 906 | e1000_clear_unicast_receive_addresses(e1000);
|
|---|
| 907 | if (addr_cnt > get_free_unicast_address_count(e1000)) {
|
|---|
| 908 | e1000_enable_unicast_promisc(e1000);
|
|---|
| 909 | nic_report_hw_filtering(nic, 0, -1, -1);
|
|---|
| [bf84871] | 910 | } else {
|
|---|
| [c4be33a] | 911 | e1000_disable_unicast_promisc(e1000);
|
|---|
| 912 | e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
|
|---|
| 913 | nic_report_hw_filtering(nic, 1, -1, -1);
|
|---|
| [bf84871] | 914 | }
|
|---|
| 915 | break;
|
|---|
| 916 | case NIC_UNICAST_PROMISC:
|
|---|
| [c4be33a] | 917 | e1000_enable_unicast_promisc(e1000);
|
|---|
| 918 | enable_ra0_address_filter(e1000);
|
|---|
| 919 | e1000_clear_unicast_receive_addresses(e1000);
|
|---|
| 920 | nic_report_hw_filtering(nic, 1, -1, -1);
|
|---|
| [bf84871] | 921 | break;
|
|---|
| 922 | default:
|
|---|
| 923 | rc = ENOTSUP;
|
|---|
| 924 | break;
|
|---|
| 925 | }
|
|---|
| [1df224c] | 926 |
|
|---|
| [c4be33a] | 927 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 928 | return rc;
|
|---|
| 929 | }
|
|---|
| 930 |
|
|---|
| [1bc35b5] | 931 | /** Set broadcast frames acceptance mode
|
|---|
| [bf84871] | 932 | *
|
|---|
| [c4be33a] | 933 | * @param nic NIC device to update
|
|---|
| 934 | * @param mode Mode to set
|
|---|
| [1df224c] | 935 | *
|
|---|
| 936 | * @return EOK
|
|---|
| [bf84871] | 937 | *
|
|---|
| 938 | */
|
|---|
| [5a6cc679] | 939 | static errno_t e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
|
|---|
| [bf84871] | 940 | {
|
|---|
| [c4be33a] | 941 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [5a6cc679] | 942 | errno_t rc = EOK;
|
|---|
| [1df224c] | 943 |
|
|---|
| [c4be33a] | 944 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 945 |
|
|---|
| [bf84871] | 946 | switch (mode) {
|
|---|
| 947 | case NIC_BROADCAST_BLOCKED:
|
|---|
| [c4be33a] | 948 | e1000_disable_broadcast_accept(e1000);
|
|---|
| [bf84871] | 949 | break;
|
|---|
| 950 | case NIC_BROADCAST_ACCEPTED:
|
|---|
| [c4be33a] | 951 | e1000_enable_broadcast_accept(e1000);
|
|---|
| [bf84871] | 952 | break;
|
|---|
| 953 | default:
|
|---|
| 954 | rc = ENOTSUP;
|
|---|
| 955 | break;
|
|---|
| 956 | }
|
|---|
| [1df224c] | 957 |
|
|---|
| [c4be33a] | 958 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 959 | return rc;
|
|---|
| 960 | }
|
|---|
| 961 |
|
|---|
| [1df224c] | 962 | /** Check if receiving is enabled
|
|---|
| 963 | *
|
|---|
| [c4be33a] | 964 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 965 | *
|
|---|
| 966 | * @return true if receiving is enabled
|
|---|
| [1df224c] | 967 | *
|
|---|
| [bf84871] | 968 | */
|
|---|
| [c4be33a] | 969 | static bool e1000_is_rx_enabled(e1000_t *e1000)
|
|---|
| [bf84871] | 970 | {
|
|---|
| [c4be33a] | 971 | if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
|
|---|
| [bf84871] | 972 | return true;
|
|---|
| [1df224c] | 973 |
|
|---|
| 974 | return false;
|
|---|
| [bf84871] | 975 | }
|
|---|
| 976 |
|
|---|
| [1df224c] | 977 | /** Enable receiving
|
|---|
| 978 | *
|
|---|
| [c4be33a] | 979 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 980 | *
|
|---|
| 981 | */
|
|---|
| [c4be33a] | 982 | static void e1000_enable_rx(e1000_t *e1000)
|
|---|
| [bf84871] | 983 | {
|
|---|
| [1df224c] | 984 | /* Set Receive Enable Bit */
|
|---|
| [c4be33a] | 985 | E1000_REG_WRITE(e1000, E1000_RCTL,
|
|---|
| 986 | E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
|
|---|
| [bf84871] | 987 | }
|
|---|
| 988 |
|
|---|
| [1df224c] | 989 | /** Disable receiving
|
|---|
| 990 | *
|
|---|
| [c4be33a] | 991 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 992 | *
|
|---|
| 993 | */
|
|---|
| [c4be33a] | 994 | static void e1000_disable_rx(e1000_t *e1000)
|
|---|
| [bf84871] | 995 | {
|
|---|
| [1df224c] | 996 | /* Clear Receive Enable Bit */
|
|---|
| [c4be33a] | 997 | E1000_REG_WRITE(e1000, E1000_RCTL,
|
|---|
| 998 | E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
|
|---|
| [bf84871] | 999 | }
|
|---|
| 1000 |
|
|---|
| 1001 | /** Set VLAN mask
|
|---|
| 1002 | *
|
|---|
| [c4be33a] | 1003 | * @param nic NIC device to update
|
|---|
| [1df224c] | 1004 | * @param vlan_mask VLAN mask
|
|---|
| 1005 | *
|
|---|
| [bf84871] | 1006 | */
|
|---|
| [c4be33a] | 1007 | static void e1000_on_vlan_mask_change(nic_t *nic,
|
|---|
| 1008 | const nic_vlan_mask_t *vlan_mask)
|
|---|
| [bf84871] | 1009 | {
|
|---|
| [c4be33a] | 1010 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1011 |
|
|---|
| [c4be33a] | 1012 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 1013 |
|
|---|
| [bf84871] | 1014 | if (vlan_mask) {
|
|---|
| [1df224c] | 1015 | /*
|
|---|
| [1bc35b5] | 1016 | * Disable receiving, so that frame matching
|
|---|
| [1df224c] | 1017 | * partially written VLAN is not received.
|
|---|
| 1018 | */
|
|---|
| [c4be33a] | 1019 | bool rx_enabled = e1000_is_rx_enabled(e1000);
|
|---|
| [1df224c] | 1020 | if (rx_enabled)
|
|---|
| [c4be33a] | 1021 | e1000_disable_rx(e1000);
|
|---|
| [1df224c] | 1022 |
|
|---|
| 1023 | for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
|
|---|
| 1024 | uint32_t bitmap_part =
|
|---|
| 1025 | ((uint32_t) vlan_mask->bitmap[i]) |
|
|---|
| 1026 | (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
|
|---|
| 1027 | (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
|
|---|
| 1028 | (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
|
|---|
| [c4be33a] | 1029 | E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
|
|---|
| [bf84871] | 1030 | }
|
|---|
| [1df224c] | 1031 |
|
|---|
| [c4be33a] | 1032 | e1000_enable_vlan_filter(e1000);
|
|---|
| [1df224c] | 1033 | if (rx_enabled)
|
|---|
| [c4be33a] | 1034 | e1000_enable_rx(e1000);
|
|---|
| [1df224c] | 1035 | } else
|
|---|
| [c4be33a] | 1036 | e1000_disable_vlan_filter(e1000);
|
|---|
| [bf84871] | 1037 |
|
|---|
| [c4be33a] | 1038 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1039 | }
|
|---|
| 1040 |
|
|---|
| 1041 | /** Set VLAN mask
|
|---|
| 1042 | *
|
|---|
| [1df224c] | 1043 | * @param device E1000 device
|
|---|
| 1044 | * @param tag VLAN tag
|
|---|
| 1045 | *
|
|---|
| 1046 | * @return EOK
|
|---|
| 1047 | * @return ENOTSUP
|
|---|
| [bf84871] | 1048 | *
|
|---|
| 1049 | */
|
|---|
| [5a6cc679] | 1050 | static errno_t e1000_vlan_set_tag(ddf_fun_t *fun, uint16_t tag, bool add,
|
|---|
| [1df224c] | 1051 | bool strip)
|
|---|
| [bf84871] | 1052 | {
|
|---|
| [1df224c] | 1053 | /* VLAN CFI bit cannot be set */
|
|---|
| 1054 | if (tag & VLANTAG_CFI)
|
|---|
| [bf84871] | 1055 | return ENOTSUP;
|
|---|
| [1df224c] | 1056 |
|
|---|
| 1057 | /*
|
|---|
| 1058 | * CTRL.VME is neccessary for both strip and add
|
|---|
| 1059 | * but CTRL.VME means stripping tags on receive.
|
|---|
| 1060 | */
|
|---|
| 1061 | if (!strip && add)
|
|---|
| [bf84871] | 1062 | return ENOTSUP;
|
|---|
| 1063 |
|
|---|
| [56fd7cf] | 1064 | e1000_t *e1000 = DRIVER_DATA_FUN(fun);
|
|---|
| [1df224c] | 1065 |
|
|---|
| [c4be33a] | 1066 | e1000->vlan_tag = tag;
|
|---|
| 1067 | e1000->vlan_tag_add = add;
|
|---|
| [1df224c] | 1068 |
|
|---|
| [c4be33a] | 1069 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 1070 |
|
|---|
| [c4be33a] | 1071 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [1df224c] | 1072 | if (strip)
|
|---|
| [bf84871] | 1073 | ctrl |= CTRL_VME;
|
|---|
| [1df224c] | 1074 | else
|
|---|
| [bf84871] | 1075 | ctrl &= ~CTRL_VME;
|
|---|
| [1df224c] | 1076 |
|
|---|
| [c4be33a] | 1077 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [1df224c] | 1078 |
|
|---|
| [c4be33a] | 1079 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| [bf84871] | 1080 | return EOK;
|
|---|
| 1081 | }
|
|---|
| [1df224c] | 1082 |
|
|---|
| [1bc35b5] | 1083 | /** Fill receive descriptor with new empty buffer
|
|---|
| [bf84871] | 1084 | *
|
|---|
| [1bc35b5] | 1085 | * Store frame in e1000->rx_frame_phys
|
|---|
| [1df224c] | 1086 | *
|
|---|
| [c4be33a] | 1087 | * @param nic NIC data stricture
|
|---|
| 1088 | * @param offset Receive descriptor offset
|
|---|
| [1df224c] | 1089 | *
|
|---|
| [bf84871] | 1090 | */
|
|---|
| [c4be33a] | 1091 | static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
|
|---|
| [bf84871] | 1092 | {
|
|---|
| [c4be33a] | 1093 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1094 |
|
|---|
| [c4be33a] | 1095 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
|---|
| 1096 | (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
|
|---|
| [1df224c] | 1097 |
|
|---|
| [1bc35b5] | 1098 | rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
|
|---|
| [bf84871] | 1099 | rx_descriptor->length = 0;
|
|---|
| 1100 | rx_descriptor->checksum = 0;
|
|---|
| 1101 | rx_descriptor->status = 0;
|
|---|
| 1102 | rx_descriptor->errors = 0;
|
|---|
| 1103 | rx_descriptor->special = 0;
|
|---|
| 1104 | }
|
|---|
| 1105 |
|
|---|
| 1106 | /** Clear receive descriptor
|
|---|
| 1107 | *
|
|---|
| [c4be33a] | 1108 | * @param e1000 E1000 data
|
|---|
| 1109 | * @param offset Receive descriptor offset
|
|---|
| [1df224c] | 1110 | *
|
|---|
| [bf84871] | 1111 | */
|
|---|
| [c4be33a] | 1112 | static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
|
|---|
| [1df224c] | 1113 | {
|
|---|
| 1114 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
|---|
| [c4be33a] | 1115 | (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
|
|---|
| [1df224c] | 1116 |
|
|---|
| [bf84871] | 1117 | rx_descriptor->length = 0;
|
|---|
| 1118 | rx_descriptor->checksum = 0;
|
|---|
| 1119 | rx_descriptor->status = 0;
|
|---|
| 1120 | rx_descriptor->errors = 0;
|
|---|
| 1121 | rx_descriptor->special = 0;
|
|---|
| 1122 | }
|
|---|
| 1123 |
|
|---|
| 1124 | /** Clear receive descriptor
|
|---|
| 1125 | *
|
|---|
| [c4be33a] | 1126 | * @param nic NIC data
|
|---|
| 1127 | * @param offset Receive descriptor offset
|
|---|
| [1df224c] | 1128 | *
|
|---|
| [bf84871] | 1129 | */
|
|---|
| [c4be33a] | 1130 | static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
|
|---|
| [bf84871] | 1131 | {
|
|---|
| [c4be33a] | 1132 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1133 |
|
|---|
| [c4be33a] | 1134 | e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
|
|---|
| 1135 | (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
|
|---|
| [bf84871] | 1136 |
|
|---|
| 1137 | tx_descriptor->phys_addr = 0;
|
|---|
| 1138 | tx_descriptor->length = 0;
|
|---|
| 1139 | tx_descriptor->checksum_offset = 0;
|
|---|
| 1140 | tx_descriptor->command = 0;
|
|---|
| 1141 | tx_descriptor->status = 0;
|
|---|
| 1142 | tx_descriptor->checksum_start_field = 0;
|
|---|
| 1143 | tx_descriptor->special = 0;
|
|---|
| 1144 | }
|
|---|
| 1145 |
|
|---|
| 1146 | /** Increment tail pointer for receive or transmit ring
|
|---|
| 1147 | *
|
|---|
| [1df224c] | 1148 | * @param tail Old Tail
|
|---|
| 1149 | * @param descriptors_count Ring length
|
|---|
| 1150 | *
|
|---|
| 1151 | * @return New tail
|
|---|
| [bf84871] | 1152 | *
|
|---|
| 1153 | */
|
|---|
| 1154 | static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
|
|---|
| 1155 | {
|
|---|
| [1df224c] | 1156 | if (tail + 1 == descriptors_count)
|
|---|
| [bf84871] | 1157 | return 0;
|
|---|
| [1df224c] | 1158 | else
|
|---|
| [bf84871] | 1159 | return tail + 1;
|
|---|
| 1160 | }
|
|---|
| 1161 |
|
|---|
| [1bc35b5] | 1162 | /** Receive frames
|
|---|
| [1df224c] | 1163 | *
|
|---|
| [c4be33a] | 1164 | * @param nic NIC data
|
|---|
| [1df224c] | 1165 | *
|
|---|
| [bf84871] | 1166 | */
|
|---|
| [1bc35b5] | 1167 | static void e1000_receive_frames(nic_t *nic)
|
|---|
| [bf84871] | 1168 | {
|
|---|
| [c4be33a] | 1169 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1170 |
|
|---|
| [c4be33a] | 1171 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1172 |
|
|---|
| [c4be33a] | 1173 | uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
|
|---|
| [1bc35b5] | 1174 | uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
|---|
| [bf84871] | 1175 |
|
|---|
| [1df224c] | 1176 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
|---|
| [c4be33a] | 1177 | (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
|
|---|
| [1df224c] | 1178 |
|
|---|
| 1179 | while (rx_descriptor->status & 0x01) {
|
|---|
| [1bc35b5] | 1180 | uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
|
|---|
| [1df224c] | 1181 |
|
|---|
| [1bc35b5] | 1182 | nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
|
|---|
| 1183 | if (frame != NULL) {
|
|---|
| 1184 | memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
|
|---|
| 1185 | nic_received_frame(nic, frame);
|
|---|
| 1186 | } else {
|
|---|
| 1187 | ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
|
|---|
| 1188 | }
|
|---|
| [1df224c] | 1189 |
|
|---|
| [c4be33a] | 1190 | e1000_fill_new_rx_descriptor(nic, next_tail);
|
|---|
| [1df224c] | 1191 |
|
|---|
| [1bc35b5] | 1192 | *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
|---|
| 1193 | next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
|---|
| [1df224c] | 1194 |
|
|---|
| 1195 | rx_descriptor = (e1000_rx_descriptor_t *)
|
|---|
| [c4be33a] | 1196 | (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
|
|---|
| [bf84871] | 1197 | }
|
|---|
| 1198 |
|
|---|
| [c4be33a] | 1199 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1200 | }
|
|---|
| 1201 |
|
|---|
| [1df224c] | 1202 | /** Enable E1000 interupts
|
|---|
| 1203 | *
|
|---|
| [c4be33a] | 1204 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 1205 | *
|
|---|
| 1206 | */
|
|---|
| [c4be33a] | 1207 | static void e1000_enable_interrupts(e1000_t *e1000)
|
|---|
| [bf84871] | 1208 | {
|
|---|
| [c4be33a] | 1209 | E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
|
|---|
| [bf84871] | 1210 | }
|
|---|
| 1211 |
|
|---|
| [1df224c] | 1212 | /** Disable E1000 interupts
|
|---|
| 1213 | *
|
|---|
| [c4be33a] | 1214 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 1215 | *
|
|---|
| 1216 | */
|
|---|
| [c4be33a] | 1217 | static void e1000_disable_interrupts(e1000_t *e1000)
|
|---|
| [bf84871] | 1218 | {
|
|---|
| [c4be33a] | 1219 | E1000_REG_WRITE(e1000, E1000_IMS, 0);
|
|---|
| [bf84871] | 1220 | }
|
|---|
| 1221 |
|
|---|
| 1222 | /** Interrupt handler implementation
|
|---|
| 1223 | *
|
|---|
| [1df224c] | 1224 | * This function is called from e1000_interrupt_handler()
|
|---|
| 1225 | * and e1000_poll()
|
|---|
| 1226 | *
|
|---|
| [c4be33a] | 1227 | * @param nic NIC data
|
|---|
| 1228 | * @param icr ICR register value
|
|---|
| [1df224c] | 1229 | *
|
|---|
| [bf84871] | 1230 | */
|
|---|
| [c4be33a] | 1231 | static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
|
|---|
| [1df224c] | 1232 | {
|
|---|
| 1233 | if (icr & ICR_RXT0)
|
|---|
| [1bc35b5] | 1234 | e1000_receive_frames(nic);
|
|---|
| [bf84871] | 1235 | }
|
|---|
| 1236 |
|
|---|
| 1237 | /** Handle device interrupt
|
|---|
| 1238 | *
|
|---|
| [1df224c] | 1239 | * @param icall IPC call structure
|
|---|
| [8820544] | 1240 | * @param dev E1000 device
|
|---|
| [1df224c] | 1241 | *
|
|---|
| [bf84871] | 1242 | */
|
|---|
| [01c3bb4] | 1243 | static void e1000_interrupt_handler(ipc_call_t *icall,
|
|---|
| [8820544] | 1244 | ddf_dev_t *dev)
|
|---|
| [bf84871] | 1245 | {
|
|---|
| 1246 | uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
|
|---|
| [c4be33a] | 1247 | nic_t *nic = NIC_DATA_DEV(dev);
|
|---|
| 1248 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [bf84871] | 1249 |
|
|---|
| [c4be33a] | 1250 | e1000_interrupt_handler_impl(nic, icr);
|
|---|
| 1251 | e1000_enable_interrupts(e1000);
|
|---|
| [1df224c] | 1252 | }
|
|---|
| [bf84871] | 1253 |
|
|---|
| 1254 | /** Register interrupt handler for the card in the system
|
|---|
| 1255 | *
|
|---|
| [1df224c] | 1256 | * Note: The global irq_reg_mutex is locked because of work with global
|
|---|
| 1257 | * structure.
|
|---|
| 1258 | *
|
|---|
| [c4be33a] | 1259 | * @param nic Driver data
|
|---|
| [1df224c] | 1260 | *
|
|---|
| [071a1ddb] | 1261 | * @param[out] handle IRQ capability handle if the handler was registered
|
|---|
| 1262 | *
|
|---|
| [cde999a] | 1263 | * @return An error code otherwise
|
|---|
| [bf84871] | 1264 | *
|
|---|
| 1265 | */
|
|---|
| [5a6cc679] | 1266 | inline static errno_t e1000_register_int_handler(nic_t *nic, cap_handle_t *handle)
|
|---|
| [bf84871] | 1267 | {
|
|---|
| [c4be33a] | 1268 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1269 |
|
|---|
| [bf84871] | 1270 | /* Lock the mutex in whole driver while working with global structure */
|
|---|
| 1271 | fibril_mutex_lock(&irq_reg_mutex);
|
|---|
| [1df224c] | 1272 |
|
|---|
| [ec52752] | 1273 | e1000_irq_code.ranges[0].base = (uintptr_t) e1000->reg_base_phys;
|
|---|
| 1274 | e1000_irq_code.cmds[0].addr = e1000->reg_base_phys + E1000_ICR;
|
|---|
| 1275 | e1000_irq_code.cmds[2].addr = e1000->reg_base_phys + E1000_IMC;
|
|---|
| [1df224c] | 1276 |
|
|---|
| [5a6cc679] | 1277 | errno_t rc = register_interrupt_handler(nic_get_ddf_dev(nic), e1000->irq,
|
|---|
| [071a1ddb] | 1278 | e1000_interrupt_handler, &e1000_irq_code, handle);
|
|---|
| [1df224c] | 1279 |
|
|---|
| [bf84871] | 1280 | fibril_mutex_unlock(&irq_reg_mutex);
|
|---|
| [071a1ddb] | 1281 | return rc;
|
|---|
| [bf84871] | 1282 | }
|
|---|
| 1283 |
|
|---|
| [1bc35b5] | 1284 | /** Force receiving all frames in the receive buffer
|
|---|
| [bf84871] | 1285 | *
|
|---|
| [c4be33a] | 1286 | * @param nic NIC data
|
|---|
| [1df224c] | 1287 | *
|
|---|
| [bf84871] | 1288 | */
|
|---|
| [c4be33a] | 1289 | static void e1000_poll(nic_t *nic)
|
|---|
| [bf84871] | 1290 | {
|
|---|
| [c4be33a] | 1291 | assert(nic);
|
|---|
| [1df224c] | 1292 |
|
|---|
| [c4be33a] | 1293 | e1000_t *e1000 = nic_get_specific(nic);
|
|---|
| 1294 | assert(e1000);
|
|---|
| [1df224c] | 1295 |
|
|---|
| [c4be33a] | 1296 | uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
|
|---|
| 1297 | e1000_interrupt_handler_impl(nic, icr);
|
|---|
| [bf84871] | 1298 | }
|
|---|
| 1299 |
|
|---|
| 1300 | /** Calculates ITR register interrupt from timeval structure
|
|---|
| 1301 | *
|
|---|
| [1df224c] | 1302 | * @param period Period
|
|---|
| 1303 | *
|
|---|
| [bf84871] | 1304 | */
|
|---|
| [1df224c] | 1305 | static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
|
|---|
| 1306 | {
|
|---|
| 1307 | // TODO: use also tv_sec
|
|---|
| [bf84871] | 1308 | return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
|
|---|
| 1309 | }
|
|---|
| 1310 |
|
|---|
| 1311 | /** Set polling mode
|
|---|
| 1312 | *
|
|---|
| [1df224c] | 1313 | * @param device Device to set
|
|---|
| 1314 | * @param mode Mode to set
|
|---|
| 1315 | * @param period Period for NIC_POLL_PERIODIC
|
|---|
| 1316 | *
|
|---|
| 1317 | * @return EOK if succeed
|
|---|
| 1318 | * @return ENOTSUP if the mode is not supported
|
|---|
| [bf84871] | 1319 | *
|
|---|
| 1320 | */
|
|---|
| [5a6cc679] | 1321 | static errno_t e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
|
|---|
| [bf84871] | 1322 | const struct timeval *period)
|
|---|
| 1323 | {
|
|---|
| [c4be33a] | 1324 | assert(nic);
|
|---|
| [1df224c] | 1325 |
|
|---|
| [c4be33a] | 1326 | e1000_t *e1000 = nic_get_specific(nic);
|
|---|
| 1327 | assert(e1000);
|
|---|
| [bf84871] | 1328 |
|
|---|
| [1df224c] | 1329 | switch (mode) {
|
|---|
| [bf84871] | 1330 | case NIC_POLL_IMMEDIATE:
|
|---|
| [c4be33a] | 1331 | E1000_REG_WRITE(e1000, E1000_ITR, 0);
|
|---|
| 1332 | e1000_enable_interrupts(e1000);
|
|---|
| [bf84871] | 1333 | break;
|
|---|
| 1334 | case NIC_POLL_ON_DEMAND:
|
|---|
| [c4be33a] | 1335 | e1000_disable_interrupts(e1000);
|
|---|
| [bf84871] | 1336 | break;
|
|---|
| 1337 | case NIC_POLL_PERIODIC:
|
|---|
| 1338 | assert(period);
|
|---|
| 1339 | uint16_t itr_interval = e1000_calculate_itr_interval(period);
|
|---|
| [c4be33a] | 1340 | E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
|
|---|
| 1341 | e1000_enable_interrupts(e1000);
|
|---|
| [bf84871] | 1342 | break;
|
|---|
| 1343 | default:
|
|---|
| 1344 | return ENOTSUP;
|
|---|
| 1345 | }
|
|---|
| [1df224c] | 1346 |
|
|---|
| [bf84871] | 1347 | return EOK;
|
|---|
| 1348 | }
|
|---|
| 1349 |
|
|---|
| [1df224c] | 1350 | /** Initialize receive registers
|
|---|
| 1351 | *
|
|---|
| [c4be33a] | 1352 | * @param e1000 E1000 data structure
|
|---|
| [bf84871] | 1353 | *
|
|---|
| 1354 | */
|
|---|
| [c4be33a] | 1355 | static void e1000_initialize_rx_registers(e1000_t *e1000)
|
|---|
| [bf84871] | 1356 | {
|
|---|
| [1bc35b5] | 1357 | E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
|
|---|
| [c4be33a] | 1358 | E1000_REG_WRITE(e1000, E1000_RDH, 0);
|
|---|
| [1df224c] | 1359 |
|
|---|
| 1360 | /* It is not posible to let HW use all descriptors */
|
|---|
| [1bc35b5] | 1361 | E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
|
|---|
| [bf84871] | 1362 |
|
|---|
| [1df224c] | 1363 | /* Set Broadcast Enable Bit */
|
|---|
| [c4be33a] | 1364 | E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
|
|---|
| [bf84871] | 1365 | }
|
|---|
| 1366 |
|
|---|
| [1df224c] | 1367 | /** Initialize receive structure
|
|---|
| 1368 | *
|
|---|
| [c4be33a] | 1369 | * @param nic NIC data
|
|---|
| [1df224c] | 1370 | *
|
|---|
| 1371 | * @return EOK if succeed
|
|---|
| [cde999a] | 1372 | * @return An error code otherwise
|
|---|
| [bf84871] | 1373 | *
|
|---|
| 1374 | */
|
|---|
| [5a6cc679] | 1375 | static errno_t e1000_initialize_rx_structure(nic_t *nic)
|
|---|
| [bf84871] | 1376 | {
|
|---|
| [c4be33a] | 1377 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| 1378 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 1379 |
|
|---|
| [bf9cb2f] | 1380 | e1000->rx_ring_virt = AS_AREA_ANY;
|
|---|
| [5a6cc679] | 1381 | errno_t rc = dmamem_map_anonymous(
|
|---|
| [1bc35b5] | 1382 | E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
|
|---|
| [8442d10] | 1383 | DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
|
|---|
| 1384 | &e1000->rx_ring_phys, &e1000->rx_ring_virt);
|
|---|
| [1df224c] | 1385 | if (rc != EOK)
|
|---|
| [bf84871] | 1386 | return rc;
|
|---|
| [1df224c] | 1387 |
|
|---|
| [c4be33a] | 1388 | E1000_REG_WRITE(e1000, E1000_RDBAH,
|
|---|
| 1389 | (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
|
|---|
| 1390 | E1000_REG_WRITE(e1000, E1000_RDBAL,
|
|---|
| 1391 | (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
|
|---|
| [1df224c] | 1392 |
|
|---|
| [8442d10] | 1393 | e1000->rx_frame_phys = (uintptr_t *)
|
|---|
| 1394 | calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t));
|
|---|
| [1bc35b5] | 1395 | e1000->rx_frame_virt =
|
|---|
| 1396 | calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
|
|---|
| [8442d10] | 1397 | if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) {
|
|---|
| [1bc35b5] | 1398 | rc = ENOMEM;
|
|---|
| 1399 | goto error;
|
|---|
| 1400 | }
|
|---|
| 1401 |
|
|---|
| [bf9cb2f] | 1402 | for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
|
|---|
| 1403 | uintptr_t frame_phys;
|
|---|
| 1404 | void *frame_virt = AS_AREA_ANY;
|
|---|
| 1405 |
|
|---|
| [8442d10] | 1406 | rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
|
|---|
| 1407 | DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
|
|---|
| 1408 | &frame_phys, &frame_virt);
|
|---|
| [1bc35b5] | 1409 | if (rc != EOK)
|
|---|
| 1410 | goto error;
|
|---|
| 1411 |
|
|---|
| 1412 | e1000->rx_frame_phys[i] = frame_phys;
|
|---|
| [8442d10] | 1413 | e1000->rx_frame_virt[i] = frame_virt;
|
|---|
| [1bc35b5] | 1414 | }
|
|---|
| [1df224c] | 1415 |
|
|---|
| 1416 | /* Write descriptor */
|
|---|
| [bf9cb2f] | 1417 | for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++)
|
|---|
| [1bc35b5] | 1418 | e1000_fill_new_rx_descriptor(nic, i);
|
|---|
| [bf84871] | 1419 |
|
|---|
| [c4be33a] | 1420 | e1000_initialize_rx_registers(e1000);
|
|---|
| [bf84871] | 1421 |
|
|---|
| [c4be33a] | 1422 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1423 | return EOK;
|
|---|
| [5cc9eba] | 1424 |
|
|---|
| [1bc35b5] | 1425 | error:
|
|---|
| [bf9cb2f] | 1426 | for (size_t i = 0; i < E1000_RX_FRAME_COUNT; i++) {
|
|---|
| [1bc35b5] | 1427 | if (e1000->rx_frame_virt[i] != NULL) {
|
|---|
| 1428 | dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
|
|---|
| [8442d10] | 1429 | e1000->rx_frame_phys[i] = 0;
|
|---|
| [1bc35b5] | 1430 | e1000->rx_frame_virt[i] = NULL;
|
|---|
| 1431 | }
|
|---|
| 1432 | }
|
|---|
| [5cc9eba] | 1433 |
|
|---|
| [1bc35b5] | 1434 | if (e1000->rx_frame_phys != NULL) {
|
|---|
| 1435 | free(e1000->rx_frame_phys);
|
|---|
| 1436 | e1000->rx_frame_phys = NULL;
|
|---|
| 1437 | }
|
|---|
| [5cc9eba] | 1438 |
|
|---|
| [1bc35b5] | 1439 | if (e1000->rx_frame_virt != NULL) {
|
|---|
| 1440 | free(e1000->rx_frame_virt);
|
|---|
| [8442d10] | 1441 | e1000->rx_frame_virt = NULL;
|
|---|
| [1bc35b5] | 1442 | }
|
|---|
| [5cc9eba] | 1443 |
|
|---|
| [1bc35b5] | 1444 | return rc;
|
|---|
| [bf84871] | 1445 | }
|
|---|
| 1446 |
|
|---|
| [1df224c] | 1447 | /** Uninitialize receive structure
|
|---|
| 1448 | *
|
|---|
| [c4be33a] | 1449 | * @param nic NIC data
|
|---|
| [bf84871] | 1450 | *
|
|---|
| 1451 | */
|
|---|
| [c4be33a] | 1452 | static void e1000_uninitialize_rx_structure(nic_t *nic)
|
|---|
| [bf84871] | 1453 | {
|
|---|
| [c4be33a] | 1454 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1455 |
|
|---|
| 1456 | /* Write descriptor */
|
|---|
| [1bc35b5] | 1457 | for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
|
|---|
| 1458 | dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
|
|---|
| [8442d10] | 1459 | e1000->rx_frame_phys[offset] = 0;
|
|---|
| [1bc35b5] | 1460 | e1000->rx_frame_virt[offset] = NULL;
|
|---|
| [bf84871] | 1461 | }
|
|---|
| 1462 |
|
|---|
| [1bc35b5] | 1463 | free(e1000->rx_frame_virt);
|
|---|
| [8442d10] | 1464 |
|
|---|
| [1bc35b5] | 1465 | e1000->rx_frame_phys = NULL;
|
|---|
| [8442d10] | 1466 | e1000->rx_frame_virt = NULL;
|
|---|
| 1467 |
|
|---|
| [c4be33a] | 1468 | dmamem_unmap_anonymous(e1000->rx_ring_virt);
|
|---|
| [bf84871] | 1469 | }
|
|---|
| 1470 |
|
|---|
| 1471 | /** Clear receive descriptor ring
|
|---|
| 1472 | *
|
|---|
| [c4be33a] | 1473 | * @param e1000 E1000 data
|
|---|
| [1df224c] | 1474 | *
|
|---|
| [bf84871] | 1475 | */
|
|---|
| [c4be33a] | 1476 | static void e1000_clear_rx_ring(e1000_t *e1000)
|
|---|
| [bf84871] | 1477 | {
|
|---|
| [1df224c] | 1478 | /* Write descriptor */
|
|---|
| 1479 | for (unsigned int offset = 0;
|
|---|
| [1bc35b5] | 1480 | offset < E1000_RX_FRAME_COUNT;
|
|---|
| [1df224c] | 1481 | offset++)
|
|---|
| [c4be33a] | 1482 | e1000_clear_rx_descriptor(e1000, offset);
|
|---|
| [bf84871] | 1483 | }
|
|---|
| 1484 |
|
|---|
| 1485 | /** Initialize filters
|
|---|
| 1486 | *
|
|---|
| [c4be33a] | 1487 | * @param e1000 E1000 data
|
|---|
| [1df224c] | 1488 | *
|
|---|
| [bf84871] | 1489 | */
|
|---|
| [c4be33a] | 1490 | static void e1000_initialize_filters(e1000_t *e1000)
|
|---|
| [bf84871] | 1491 | {
|
|---|
| [1df224c] | 1492 | /* Initialize address filter */
|
|---|
| [c4be33a] | 1493 | e1000->unicast_ra_count = 0;
|
|---|
| 1494 | e1000->multicast_ra_count = 0;
|
|---|
| 1495 | e1000_clear_unicast_receive_addresses(e1000);
|
|---|
| [bf84871] | 1496 | }
|
|---|
| 1497 |
|
|---|
| 1498 | /** Initialize VLAN
|
|---|
| 1499 | *
|
|---|
| [c4be33a] | 1500 | * @param e1000 E1000 data
|
|---|
| [1df224c] | 1501 | *
|
|---|
| [bf84871] | 1502 | */
|
|---|
| [c4be33a] | 1503 | static void e1000_initialize_vlan(e1000_t *e1000)
|
|---|
| [bf84871] | 1504 | {
|
|---|
| [c4be33a] | 1505 | e1000->vlan_tag_add = false;
|
|---|
| [bf84871] | 1506 | }
|
|---|
| 1507 |
|
|---|
| [1df224c] | 1508 | /** Fill MAC address from EEPROM to RA[0] register
|
|---|
| 1509 | *
|
|---|
| [c4be33a] | 1510 | * @param e1000 E1000 data
|
|---|
| [bf84871] | 1511 | *
|
|---|
| 1512 | */
|
|---|
| [c4be33a] | 1513 | static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
|
|---|
| [bf84871] | 1514 | {
|
|---|
| [1df224c] | 1515 | /* MAC address from eeprom to RA[0] */
|
|---|
| [bf84871] | 1516 | nic_address_t address;
|
|---|
| [c4be33a] | 1517 | e1000_eeprom_get_address(e1000, &address);
|
|---|
| 1518 | e1000_write_receive_address(e1000, 0, &address, true);
|
|---|
| [bf84871] | 1519 | }
|
|---|
| 1520 |
|
|---|
| [1df224c] | 1521 | /** Initialize other registers
|
|---|
| 1522 | *
|
|---|
| 1523 | * @param dev E1000 data.
|
|---|
| 1524 | *
|
|---|
| 1525 | * @return EOK if succeed
|
|---|
| [cde999a] | 1526 | * @return An error code otherwise
|
|---|
| [bf84871] | 1527 | *
|
|---|
| 1528 | */
|
|---|
| [c4be33a] | 1529 | static void e1000_initialize_registers(e1000_t *e1000)
|
|---|
| [bf84871] | 1530 | {
|
|---|
| [c4be33a] | 1531 | E1000_REG_WRITE(e1000, E1000_ITR,
|
|---|
| [1df224c] | 1532 | e1000_calculate_itr_interval_from_usecs(
|
|---|
| [9916841] | 1533 | E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
|
|---|
| [c4be33a] | 1534 | E1000_REG_WRITE(e1000, E1000_FCAH, 0);
|
|---|
| 1535 | E1000_REG_WRITE(e1000, E1000_FCAL, 0);
|
|---|
| 1536 | E1000_REG_WRITE(e1000, E1000_FCT, 0);
|
|---|
| 1537 | E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
|
|---|
| 1538 | E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
|
|---|
| 1539 | E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
|
|---|
| [bf84871] | 1540 | }
|
|---|
| 1541 |
|
|---|
| [1df224c] | 1542 | /** Initialize transmit registers
|
|---|
| 1543 | *
|
|---|
| [c4be33a] | 1544 | * @param e1000 E1000 data.
|
|---|
| [bf84871] | 1545 | *
|
|---|
| 1546 | */
|
|---|
| [c4be33a] | 1547 | static void e1000_initialize_tx_registers(e1000_t *e1000)
|
|---|
| [bf84871] | 1548 | {
|
|---|
| [1bc35b5] | 1549 | E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
|
|---|
| [c4be33a] | 1550 | E1000_REG_WRITE(e1000, E1000_TDH, 0);
|
|---|
| 1551 | E1000_REG_WRITE(e1000, E1000_TDT, 0);
|
|---|
| [bf84871] | 1552 |
|
|---|
| [c4be33a] | 1553 | E1000_REG_WRITE(e1000, E1000_TIPG,
|
|---|
| [1df224c] | 1554 | 10 << TIPG_IPGT_SHIFT |
|
|---|
| 1555 | 8 << TIPG_IPGR1_SHIFT |
|
|---|
| 1556 | 6 << TIPG_IPGR2_SHIFT);
|
|---|
| [bf84871] | 1557 |
|
|---|
| [c4be33a] | 1558 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
|---|
| [1df224c] | 1559 | 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
|
|---|
| 1560 | 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
|
|---|
| 1561 | TCTL_PSP /* Pad Short Packets */);
|
|---|
| [bf84871] | 1562 | }
|
|---|
| 1563 |
|
|---|
| 1564 | /** Initialize transmit structure
|
|---|
| 1565 | *
|
|---|
| [c4be33a] | 1566 | * @param e1000 E1000 data.
|
|---|
| [1df224c] | 1567 | *
|
|---|
| [bf84871] | 1568 | */
|
|---|
| [5a6cc679] | 1569 | static errno_t e1000_initialize_tx_structure(e1000_t *e1000)
|
|---|
| [bf84871] | 1570 | {
|
|---|
| [6d8455d] | 1571 | size_t i;
|
|---|
| 1572 |
|
|---|
| [c4be33a] | 1573 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| [1df224c] | 1574 |
|
|---|
| [8442d10] | 1575 | e1000->tx_ring_phys = 0;
|
|---|
| [bf9cb2f] | 1576 | e1000->tx_ring_virt = AS_AREA_ANY;
|
|---|
| [8442d10] | 1577 |
|
|---|
| [6d8455d] | 1578 | e1000->tx_frame_phys = NULL;
|
|---|
| 1579 | e1000->tx_frame_virt = NULL;
|
|---|
| 1580 |
|
|---|
| [5a6cc679] | 1581 | errno_t rc = dmamem_map_anonymous(
|
|---|
| [1bc35b5] | 1582 | E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
|
|---|
| [8442d10] | 1583 | DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
|
|---|
| 1584 | &e1000->tx_ring_phys, &e1000->tx_ring_virt);
|
|---|
| [1df224c] | 1585 | if (rc != EOK)
|
|---|
| [6d8455d] | 1586 | goto error;
|
|---|
| [bf84871] | 1587 |
|
|---|
| [acdb5bac] | 1588 | memset(e1000->tx_ring_virt, 0,
|
|---|
| [1bc35b5] | 1589 | E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
|
|---|
| [1df224c] | 1590 |
|
|---|
| [8442d10] | 1591 | e1000->tx_frame_phys = (uintptr_t *)
|
|---|
| 1592 | calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t));
|
|---|
| 1593 | e1000->tx_frame_virt =
|
|---|
| 1594 | calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
|
|---|
| [6d8455d] | 1595 |
|
|---|
| [8442d10] | 1596 | if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) {
|
|---|
| [6d8455d] | 1597 | rc = ENOMEM;
|
|---|
| 1598 | goto error;
|
|---|
| 1599 | }
|
|---|
| 1600 |
|
|---|
| [1bc35b5] | 1601 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
|---|
| [bf9cb2f] | 1602 | e1000->tx_frame_virt[i] = AS_AREA_ANY;
|
|---|
| [8442d10] | 1603 | rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE,
|
|---|
| 1604 | DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE,
|
|---|
| [6d8455d] | 1605 | 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
|
|---|
| 1606 | if (rc != EOK)
|
|---|
| 1607 | goto error;
|
|---|
| 1608 | }
|
|---|
| 1609 |
|
|---|
| [c4be33a] | 1610 | E1000_REG_WRITE(e1000, E1000_TDBAH,
|
|---|
| 1611 | (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
|
|---|
| 1612 | E1000_REG_WRITE(e1000, E1000_TDBAL,
|
|---|
| 1613 | (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
|
|---|
| [1df224c] | 1614 |
|
|---|
| [c4be33a] | 1615 | e1000_initialize_tx_registers(e1000);
|
|---|
| [bf84871] | 1616 |
|
|---|
| [c4be33a] | 1617 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| [bf84871] | 1618 | return EOK;
|
|---|
| [6d8455d] | 1619 |
|
|---|
| 1620 | error:
|
|---|
| 1621 | if (e1000->tx_ring_virt != NULL) {
|
|---|
| 1622 | dmamem_unmap_anonymous(e1000->tx_ring_virt);
|
|---|
| 1623 | e1000->tx_ring_virt = NULL;
|
|---|
| 1624 | }
|
|---|
| 1625 |
|
|---|
| [8442d10] | 1626 | if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) {
|
|---|
| [1bc35b5] | 1627 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
|---|
| [6d8455d] | 1628 | if (e1000->tx_frame_virt[i] != NULL) {
|
|---|
| 1629 | dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
|
|---|
| [8442d10] | 1630 | e1000->tx_frame_phys[i] = 0;
|
|---|
| [6d8455d] | 1631 | e1000->tx_frame_virt[i] = NULL;
|
|---|
| 1632 | }
|
|---|
| 1633 | }
|
|---|
| 1634 | }
|
|---|
| 1635 |
|
|---|
| 1636 | if (e1000->tx_frame_phys != NULL) {
|
|---|
| 1637 | free(e1000->tx_frame_phys);
|
|---|
| 1638 | e1000->tx_frame_phys = NULL;
|
|---|
| 1639 | }
|
|---|
| 1640 |
|
|---|
| 1641 | if (e1000->tx_frame_virt != NULL) {
|
|---|
| 1642 | free(e1000->tx_frame_virt);
|
|---|
| [8442d10] | 1643 | e1000->tx_frame_virt = NULL;
|
|---|
| [6d8455d] | 1644 | }
|
|---|
| 1645 |
|
|---|
| 1646 | return rc;
|
|---|
| [bf84871] | 1647 | }
|
|---|
| 1648 |
|
|---|
| [1df224c] | 1649 | /** Uninitialize transmit structure
|
|---|
| 1650 | *
|
|---|
| [c4be33a] | 1651 | * @param nic NIC data
|
|---|
| [bf84871] | 1652 | *
|
|---|
| 1653 | */
|
|---|
| [c4be33a] | 1654 | static void e1000_uninitialize_tx_structure(e1000_t *e1000)
|
|---|
| [bf84871] | 1655 | {
|
|---|
| [6d8455d] | 1656 | size_t i;
|
|---|
| 1657 |
|
|---|
| [1bc35b5] | 1658 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
|---|
| [6d8455d] | 1659 | dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
|
|---|
| [8442d10] | 1660 | e1000->tx_frame_phys[i] = 0;
|
|---|
| [6d8455d] | 1661 | e1000->tx_frame_virt[i] = NULL;
|
|---|
| 1662 | }
|
|---|
| 1663 |
|
|---|
| 1664 | if (e1000->tx_frame_phys != NULL) {
|
|---|
| 1665 | free(e1000->tx_frame_phys);
|
|---|
| 1666 | e1000->tx_frame_phys = NULL;
|
|---|
| 1667 | }
|
|---|
| 1668 |
|
|---|
| 1669 | if (e1000->tx_frame_virt != NULL) {
|
|---|
| 1670 | free(e1000->tx_frame_virt);
|
|---|
| [8442d10] | 1671 | e1000->tx_frame_virt = NULL;
|
|---|
| [6d8455d] | 1672 | }
|
|---|
| [5cc9eba] | 1673 |
|
|---|
| [c4be33a] | 1674 | dmamem_unmap_anonymous(e1000->tx_ring_virt);
|
|---|
| [bf84871] | 1675 | }
|
|---|
| 1676 |
|
|---|
| 1677 | /** Clear transmit descriptor ring
|
|---|
| 1678 | *
|
|---|
| [c4be33a] | 1679 | * @param nic NIC data
|
|---|
| [1df224c] | 1680 | *
|
|---|
| [bf84871] | 1681 | */
|
|---|
| [c4be33a] | 1682 | static void e1000_clear_tx_ring(nic_t *nic)
|
|---|
| [bf84871] | 1683 | {
|
|---|
| [1df224c] | 1684 | /* Write descriptor */
|
|---|
| 1685 | for (unsigned int offset = 0;
|
|---|
| [1bc35b5] | 1686 | offset < E1000_TX_FRAME_COUNT;
|
|---|
| [1df224c] | 1687 | offset++)
|
|---|
| [c4be33a] | 1688 | e1000_clear_tx_descriptor(nic, offset);
|
|---|
| [bf84871] | 1689 | }
|
|---|
| 1690 |
|
|---|
| 1691 | /** Enable transmit
|
|---|
| 1692 | *
|
|---|
| [c4be33a] | 1693 | * @param e1000 E1000 data
|
|---|
| [1df224c] | 1694 | *
|
|---|
| [bf84871] | 1695 | */
|
|---|
| [c4be33a] | 1696 | static void e1000_enable_tx(e1000_t *e1000)
|
|---|
| [bf84871] | 1697 | {
|
|---|
| [1df224c] | 1698 | /* Set Transmit Enable Bit */
|
|---|
| [c4be33a] | 1699 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
|---|
| 1700 | E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
|
|---|
| [bf84871] | 1701 | }
|
|---|
| 1702 |
|
|---|
| 1703 | /** Disable transmit
|
|---|
| 1704 | *
|
|---|
| [c4be33a] | 1705 | * @param e1000 E1000 data
|
|---|
| [1df224c] | 1706 | *
|
|---|
| [bf84871] | 1707 | */
|
|---|
| [c4be33a] | 1708 | static void e1000_disable_tx(e1000_t *e1000)
|
|---|
| [bf84871] | 1709 | {
|
|---|
| [1df224c] | 1710 | /* Clear Transmit Enable Bit */
|
|---|
| [c4be33a] | 1711 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
|---|
| 1712 | E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
|
|---|
| [bf84871] | 1713 | }
|
|---|
| 1714 |
|
|---|
| 1715 | /** Reset E1000 device
|
|---|
| 1716 | *
|
|---|
| [c4be33a] | 1717 | * @param e1000 The E1000 data
|
|---|
| [1df224c] | 1718 | *
|
|---|
| [bf84871] | 1719 | */
|
|---|
| [5a6cc679] | 1720 | static errno_t e1000_reset(nic_t *nic)
|
|---|
| [bf84871] | 1721 | {
|
|---|
| [c4be33a] | 1722 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [bf84871] | 1723 |
|
|---|
| [c4be33a] | 1724 | E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
|
|---|
| [1df224c] | 1725 |
|
|---|
| 1726 | /* Wait for the reset */
|
|---|
| [f300523] | 1727 | async_usleep(20);
|
|---|
| [1df224c] | 1728 |
|
|---|
| 1729 | /* check if RST_BIT cleared */
|
|---|
| [c4be33a] | 1730 | if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
|
|---|
| [1df224c] | 1731 | return EINVAL;
|
|---|
| 1732 |
|
|---|
| [c4be33a] | 1733 | e1000_initialize_registers(e1000);
|
|---|
| 1734 | e1000_initialize_rx_registers(e1000);
|
|---|
| 1735 | e1000_initialize_tx_registers(e1000);
|
|---|
| 1736 | e1000_fill_mac_from_eeprom(e1000);
|
|---|
| 1737 | e1000_initialize_filters(e1000);
|
|---|
| 1738 | e1000_initialize_vlan(e1000);
|
|---|
| [bf84871] | 1739 |
|
|---|
| 1740 | return EOK;
|
|---|
| 1741 | }
|
|---|
| 1742 |
|
|---|
| [1bc35b5] | 1743 | /** Activate the device to receive and transmit frames
|
|---|
| [bf84871] | 1744 | *
|
|---|
| [c4be33a] | 1745 | * @param nic NIC driver data
|
|---|
| [1df224c] | 1746 | *
|
|---|
| 1747 | * @return EOK if activated successfully
|
|---|
| 1748 | * @return Error code otherwise
|
|---|
| 1749 | *
|
|---|
| [bf84871] | 1750 | */
|
|---|
| [5a6cc679] | 1751 | static errno_t e1000_on_activating(nic_t *nic)
|
|---|
| [bf84871] | 1752 | {
|
|---|
| [c4be33a] | 1753 | assert(nic);
|
|---|
| [1df224c] | 1754 |
|
|---|
| [c4be33a] | 1755 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 1756 |
|
|---|
| [c4be33a] | 1757 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| 1758 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| 1759 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 1760 |
|
|---|
| [c4be33a] | 1761 | e1000_enable_interrupts(e1000);
|
|---|
| [1df224c] | 1762 |
|
|---|
| [5a6cc679] | 1763 | errno_t rc = hw_res_enable_interrupt(e1000->parent_sess, e1000->irq);
|
|---|
| [e5424e9] | 1764 | if (rc != EOK) {
|
|---|
| 1765 | e1000_disable_interrupts(e1000);
|
|---|
| 1766 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| 1767 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| 1768 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| 1769 | return rc;
|
|---|
| 1770 | }
|
|---|
| [bf84871] | 1771 |
|
|---|
| [c4be33a] | 1772 | e1000_clear_rx_ring(e1000);
|
|---|
| 1773 | e1000_enable_rx(e1000);
|
|---|
| [1df224c] | 1774 |
|
|---|
| [c4be33a] | 1775 | e1000_clear_tx_ring(nic);
|
|---|
| 1776 | e1000_enable_tx(e1000);
|
|---|
| [bf84871] | 1777 |
|
|---|
| [c4be33a] | 1778 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [bf84871] | 1779 | ctrl |= CTRL_SLU;
|
|---|
| [c4be33a] | 1780 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [bf84871] | 1781 |
|
|---|
| [c4be33a] | 1782 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| 1783 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| 1784 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [1df224c] | 1785 |
|
|---|
| [bf84871] | 1786 | return EOK;
|
|---|
| 1787 | }
|
|---|
| 1788 |
|
|---|
| 1789 | /** Callback for NIC_STATE_DOWN change
|
|---|
| 1790 | *
|
|---|
| [c4be33a] | 1791 | * @param nic NIC driver data
|
|---|
| [1df224c] | 1792 | *
|
|---|
| 1793 | * @return EOK if succeed
|
|---|
| 1794 | * @return Error code otherwise
|
|---|
| 1795 | *
|
|---|
| [bf84871] | 1796 | */
|
|---|
| [5a6cc679] | 1797 | static errno_t e1000_on_down_unlocked(nic_t *nic)
|
|---|
| [bf84871] | 1798 | {
|
|---|
| [c4be33a] | 1799 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [bf84871] | 1800 |
|
|---|
| [c4be33a] | 1801 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
|---|
| [bf84871] | 1802 | ctrl &= ~CTRL_SLU;
|
|---|
| [c4be33a] | 1803 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
|---|
| [bf84871] | 1804 |
|
|---|
| [c4be33a] | 1805 | e1000_disable_tx(e1000);
|
|---|
| 1806 | e1000_disable_rx(e1000);
|
|---|
| [bf84871] | 1807 |
|
|---|
| [d51838f] | 1808 | hw_res_disable_interrupt(e1000->parent_sess, e1000->irq);
|
|---|
| [c4be33a] | 1809 | e1000_disable_interrupts(e1000);
|
|---|
| [bf84871] | 1810 |
|
|---|
| [1df224c] | 1811 | /*
|
|---|
| 1812 | * Wait for the for the end of all data
|
|---|
| 1813 | * transfers to descriptors.
|
|---|
| 1814 | */
|
|---|
| [f300523] | 1815 | async_usleep(100);
|
|---|
| [1df224c] | 1816 |
|
|---|
| [bf84871] | 1817 | return EOK;
|
|---|
| 1818 | }
|
|---|
| 1819 |
|
|---|
| 1820 | /** Callback for NIC_STATE_DOWN change
|
|---|
| 1821 | *
|
|---|
| [c4be33a] | 1822 | * @param nic NIC driver data
|
|---|
| [1df224c] | 1823 | *
|
|---|
| 1824 | * @return EOK if succeed
|
|---|
| 1825 | * @return Error code otherwise
|
|---|
| 1826 | *
|
|---|
| [bf84871] | 1827 | */
|
|---|
| [5a6cc679] | 1828 | static errno_t e1000_on_down(nic_t *nic)
|
|---|
| [bf84871] | 1829 | {
|
|---|
| [c4be33a] | 1830 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [bf84871] | 1831 |
|
|---|
| [c4be33a] | 1832 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| 1833 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| 1834 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [1df224c] | 1835 |
|
|---|
| [5a6cc679] | 1836 | errno_t rc = e1000_on_down_unlocked(nic);
|
|---|
| [bf84871] | 1837 |
|
|---|
| [c4be33a] | 1838 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| 1839 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| 1840 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1841 |
|
|---|
| 1842 | return rc;
|
|---|
| 1843 | }
|
|---|
| 1844 |
|
|---|
| 1845 | /** Callback for NIC_STATE_STOPPED change
|
|---|
| 1846 | *
|
|---|
| [c4be33a] | 1847 | * @param nic NIC driver data
|
|---|
| [1df224c] | 1848 | *
|
|---|
| 1849 | * @return EOK if succeed
|
|---|
| 1850 | * @return Error code otherwise
|
|---|
| 1851 | *
|
|---|
| [bf84871] | 1852 | */
|
|---|
| [5a6cc679] | 1853 | static errno_t e1000_on_stopping(nic_t *nic)
|
|---|
| [bf84871] | 1854 | {
|
|---|
| [c4be33a] | 1855 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [bf84871] | 1856 |
|
|---|
| [c4be33a] | 1857 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| 1858 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| 1859 | fibril_mutex_lock(&e1000->ctrl_lock);
|
|---|
| [bf84871] | 1860 |
|
|---|
| [5a6cc679] | 1861 | errno_t rc = e1000_on_down_unlocked(nic);
|
|---|
| [1df224c] | 1862 | if (rc == EOK)
|
|---|
| [c4be33a] | 1863 | rc = e1000_reset(nic);
|
|---|
| [bf84871] | 1864 |
|
|---|
| [c4be33a] | 1865 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
|---|
| 1866 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| 1867 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 1868 |
|
|---|
| 1869 | return rc;
|
|---|
| 1870 | }
|
|---|
| 1871 |
|
|---|
| 1872 | /** Create driver data structure
|
|---|
| 1873 | *
|
|---|
| [1df224c] | 1874 | * @return Intialized device data structure or NULL
|
|---|
| 1875 | *
|
|---|
| [bf84871] | 1876 | */
|
|---|
| 1877 | static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
|
|---|
| 1878 | {
|
|---|
| [c4be33a] | 1879 | nic_t *nic = nic_create_and_bind(dev);
|
|---|
| 1880 | if (!nic)
|
|---|
| [bf84871] | 1881 | return NULL;
|
|---|
| [1df224c] | 1882 |
|
|---|
| [c4be33a] | 1883 | e1000_t *e1000 = malloc(sizeof(e1000_t));
|
|---|
| 1884 | if (!e1000) {
|
|---|
| [bf84871] | 1885 | nic_unbind_and_destroy(dev);
|
|---|
| 1886 | return NULL;
|
|---|
| 1887 | }
|
|---|
| [1df224c] | 1888 |
|
|---|
| [acdb5bac] | 1889 | memset(e1000, 0, sizeof(e1000_t));
|
|---|
| [d51838f] | 1890 | e1000->dev = dev;
|
|---|
| [1df224c] | 1891 |
|
|---|
| [c4be33a] | 1892 | nic_set_specific(nic, e1000);
|
|---|
| [6d8455d] | 1893 | nic_set_send_frame_handler(nic, e1000_send_frame);
|
|---|
| [c4be33a] | 1894 | nic_set_state_change_handlers(nic, e1000_on_activating,
|
|---|
| [1df224c] | 1895 | e1000_on_down, e1000_on_stopping);
|
|---|
| [c4be33a] | 1896 | nic_set_filtering_change_handlers(nic,
|
|---|
| [1df224c] | 1897 | e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
|
|---|
| 1898 | e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
|
|---|
| [c4be33a] | 1899 | nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
|
|---|
| [1df224c] | 1900 |
|
|---|
| [c4be33a] | 1901 | fibril_mutex_initialize(&e1000->ctrl_lock);
|
|---|
| 1902 | fibril_mutex_initialize(&e1000->rx_lock);
|
|---|
| 1903 | fibril_mutex_initialize(&e1000->tx_lock);
|
|---|
| 1904 | fibril_mutex_initialize(&e1000->eeprom_lock);
|
|---|
| [bf84871] | 1905 |
|
|---|
| [c4be33a] | 1906 | return e1000;
|
|---|
| [bf84871] | 1907 | }
|
|---|
| 1908 |
|
|---|
| [1df224c] | 1909 | /** Delete driver data structure
|
|---|
| 1910 | *
|
|---|
| 1911 | * @param data E1000 device data structure
|
|---|
| [bf84871] | 1912 | *
|
|---|
| 1913 | */
|
|---|
| 1914 | inline static void e1000_delete_dev_data(ddf_dev_t *dev)
|
|---|
| 1915 | {
|
|---|
| 1916 | assert(dev);
|
|---|
| [1df224c] | 1917 |
|
|---|
| [56fd7cf] | 1918 | if (ddf_dev_data_get(dev) != NULL)
|
|---|
| [bf84871] | 1919 | nic_unbind_and_destroy(dev);
|
|---|
| 1920 | }
|
|---|
| 1921 |
|
|---|
| [1df224c] | 1922 | /** Clean up the E1000 device structure.
|
|---|
| 1923 | *
|
|---|
| 1924 | * @param dev Device structure.
|
|---|
| [bf84871] | 1925 | *
|
|---|
| 1926 | */
|
|---|
| 1927 | static void e1000_dev_cleanup(ddf_dev_t *dev)
|
|---|
| 1928 | {
|
|---|
| 1929 | assert(dev);
|
|---|
| [1df224c] | 1930 |
|
|---|
| [bf84871] | 1931 | e1000_delete_dev_data(dev);
|
|---|
| 1932 | }
|
|---|
| 1933 |
|
|---|
| 1934 | /** Fill the irq and io_addr part of device data structure
|
|---|
| 1935 | *
|
|---|
| [1df224c] | 1936 | * The hw_resources must be obtained before calling this function
|
|---|
| 1937 | *
|
|---|
| 1938 | * @param dev Device structure
|
|---|
| 1939 | * @param hw_resources Hardware resources obtained from the parent device
|
|---|
| 1940 | *
|
|---|
| 1941 | * @return EOK if succeed
|
|---|
| [cde999a] | 1942 | * @return An error code otherwise
|
|---|
| [bf84871] | 1943 | *
|
|---|
| 1944 | */
|
|---|
| [5a6cc679] | 1945 | static errno_t e1000_fill_resource_info(ddf_dev_t *dev,
|
|---|
| [1df224c] | 1946 | const hw_res_list_parsed_t *hw_resources)
|
|---|
| [bf84871] | 1947 | {
|
|---|
| [c4be33a] | 1948 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
|---|
| [1df224c] | 1949 |
|
|---|
| 1950 | if (hw_resources->irqs.count != 1)
|
|---|
| [bf84871] | 1951 | return EINVAL;
|
|---|
| [1df224c] | 1952 |
|
|---|
| [c4be33a] | 1953 | e1000->irq = hw_resources->irqs.irqs[0];
|
|---|
| 1954 | e1000->reg_base_phys =
|
|---|
| [7de1988c] | 1955 | MEMADDR_TO_PTR(RNGABS(hw_resources->mem_ranges.ranges[0]));
|
|---|
| [1df224c] | 1956 |
|
|---|
| [bf84871] | 1957 | return EOK;
|
|---|
| 1958 | }
|
|---|
| 1959 |
|
|---|
| 1960 | /** Obtain information about hardware resources of the device
|
|---|
| 1961 | *
|
|---|
| [1df224c] | 1962 | * The device must be connected to the parent
|
|---|
| 1963 | *
|
|---|
| 1964 | * @param dev Device structure
|
|---|
| 1965 | *
|
|---|
| 1966 | * @return EOK if succeed
|
|---|
| [cde999a] | 1967 | * @return An error code otherwise
|
|---|
| [bf84871] | 1968 | *
|
|---|
| 1969 | */
|
|---|
| [5a6cc679] | 1970 | static errno_t e1000_get_resource_info(ddf_dev_t *dev)
|
|---|
| [bf84871] | 1971 | {
|
|---|
| 1972 | assert(dev != NULL);
|
|---|
| 1973 | assert(NIC_DATA_DEV(dev) != NULL);
|
|---|
| [1df224c] | 1974 |
|
|---|
| [bf84871] | 1975 | hw_res_list_parsed_t hw_res_parsed;
|
|---|
| 1976 | hw_res_list_parsed_init(&hw_res_parsed);
|
|---|
| [1df224c] | 1977 |
|
|---|
| [bf84871] | 1978 | /* Get hw resources form parent driver */
|
|---|
| [5a6cc679] | 1979 | errno_t rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
|
|---|
| [bf84871] | 1980 | if (rc != EOK)
|
|---|
| 1981 | return rc;
|
|---|
| [1df224c] | 1982 |
|
|---|
| [bf84871] | 1983 | /* Fill resources information to the device */
|
|---|
| 1984 | rc = e1000_fill_resource_info(dev, &hw_res_parsed);
|
|---|
| 1985 | hw_res_list_parsed_clean(&hw_res_parsed);
|
|---|
| [1df224c] | 1986 |
|
|---|
| [bf84871] | 1987 | return rc;
|
|---|
| 1988 | }
|
|---|
| 1989 |
|
|---|
| [1df224c] | 1990 | /** Initialize the E1000 device structure
|
|---|
| 1991 | *
|
|---|
| 1992 | * @param dev Device information
|
|---|
| 1993 | *
|
|---|
| 1994 | * @return EOK if succeed
|
|---|
| [cde999a] | 1995 | * @return An error code otherwise
|
|---|
| [bf84871] | 1996 | *
|
|---|
| 1997 | */
|
|---|
| [5a6cc679] | 1998 | static errno_t e1000_device_initialize(ddf_dev_t *dev)
|
|---|
| [bf84871] | 1999 | {
|
|---|
| 2000 | /* Allocate driver data for the device. */
|
|---|
| [c4be33a] | 2001 | e1000_t *e1000 = e1000_create_dev_data(dev);
|
|---|
| [77c2b02] | 2002 | if (e1000 == NULL) {
|
|---|
| 2003 | ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
|
|---|
| [bf84871] | 2004 | return ENOMEM;
|
|---|
| [77c2b02] | 2005 | }
|
|---|
| [1df224c] | 2006 |
|
|---|
| [d51838f] | 2007 | e1000->parent_sess = ddf_dev_parent_sess_get(dev);
|
|---|
| 2008 | if (e1000->parent_sess == NULL) {
|
|---|
| 2009 | ddf_msg(LVL_ERROR, "Failed connecting parent device.");
|
|---|
| 2010 | return EIO;
|
|---|
| 2011 | }
|
|---|
| 2012 |
|
|---|
| [bf84871] | 2013 | /* Obtain and fill hardware resources info */
|
|---|
| [5a6cc679] | 2014 | errno_t rc = e1000_get_resource_info(dev);
|
|---|
| [bf84871] | 2015 | if (rc != EOK) {
|
|---|
| [77c2b02] | 2016 | ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
|
|---|
| [1df224c] | 2017 | e1000_dev_cleanup(dev);
|
|---|
| 2018 | return rc;
|
|---|
| [bf84871] | 2019 | }
|
|---|
| 2020 |
|
|---|
| [77c2b02] | 2021 | uint16_t device_id;
|
|---|
| [56fd7cf] | 2022 | rc = pci_config_space_read_16(ddf_dev_parent_sess_get(dev), PCI_DEVICE_ID,
|
|---|
| [77c2b02] | 2023 | &device_id);
|
|---|
| [bf84871] | 2024 | if (rc != EOK) {
|
|---|
| [77c2b02] | 2025 | ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
|
|---|
| [1df224c] | 2026 | e1000_dev_cleanup(dev);
|
|---|
| 2027 | return rc;
|
|---|
| [bf84871] | 2028 | }
|
|---|
| [1df224c] | 2029 |
|
|---|
| [77c2b02] | 2030 | e1000_board_t board;
|
|---|
| 2031 | switch (device_id) {
|
|---|
| [9f0fb84] | 2032 | case 0x100e:
|
|---|
| 2033 | case 0x1015:
|
|---|
| 2034 | case 0x1016:
|
|---|
| 2035 | case 0x1017:
|
|---|
| 2036 | board = E1000_82540;
|
|---|
| 2037 | break;
|
|---|
| [77c2b02] | 2038 | case 0x1013:
|
|---|
| 2039 | case 0x1018:
|
|---|
| 2040 | case 0x1078:
|
|---|
| 2041 | board = E1000_82541;
|
|---|
| 2042 | break;
|
|---|
| 2043 | case 0x1076:
|
|---|
| 2044 | case 0x1077:
|
|---|
| 2045 | case 0x107c:
|
|---|
| 2046 | board = E1000_82541REV2;
|
|---|
| 2047 | break;
|
|---|
| [9f0fb84] | 2048 | case 0x100f:
|
|---|
| 2049 | case 0x1011:
|
|---|
| 2050 | case 0x1026:
|
|---|
| 2051 | case 0x1027:
|
|---|
| 2052 | case 0x1028:
|
|---|
| 2053 | board = E1000_82545;
|
|---|
| 2054 | break;
|
|---|
| 2055 | case 0x1010:
|
|---|
| 2056 | case 0x1012:
|
|---|
| 2057 | case 0x101d:
|
|---|
| 2058 | case 0x1079:
|
|---|
| 2059 | case 0x107a:
|
|---|
| 2060 | case 0x107b:
|
|---|
| 2061 | board = E1000_82546;
|
|---|
| 2062 | break;
|
|---|
| [77c2b02] | 2063 | case 0x1019:
|
|---|
| 2064 | case 0x101a:
|
|---|
| 2065 | board = E1000_82547;
|
|---|
| 2066 | break;
|
|---|
| 2067 | case 0x10b9:
|
|---|
| 2068 | board = E1000_82572;
|
|---|
| 2069 | break;
|
|---|
| 2070 | case 0x1096:
|
|---|
| 2071 | board = E1000_80003ES2;
|
|---|
| 2072 | break;
|
|---|
| 2073 | default:
|
|---|
| 2074 | ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
|
|---|
| 2075 | device_id);
|
|---|
| 2076 | e1000_dev_cleanup(dev);
|
|---|
| 2077 | return ENOTSUP;
|
|---|
| 2078 | }
|
|---|
| 2079 |
|
|---|
| 2080 | switch (board) {
|
|---|
| [9f0fb84] | 2081 | case E1000_82540:
|
|---|
| [77c2b02] | 2082 | case E1000_82541:
|
|---|
| 2083 | case E1000_82541REV2:
|
|---|
| [9f0fb84] | 2084 | case E1000_82545:
|
|---|
| 2085 | case E1000_82546:
|
|---|
| [77c2b02] | 2086 | e1000->info.eerd_start = 0x01;
|
|---|
| 2087 | e1000->info.eerd_done = 0x10;
|
|---|
| 2088 | e1000->info.eerd_address_offset = 8;
|
|---|
| 2089 | e1000->info.eerd_data_offset = 16;
|
|---|
| 2090 | break;
|
|---|
| 2091 | case E1000_82547:
|
|---|
| [d81eaf94] | 2092 | case E1000_82572:
|
|---|
| [77c2b02] | 2093 | case E1000_80003ES2:
|
|---|
| 2094 | e1000->info.eerd_start = 0x01;
|
|---|
| 2095 | e1000->info.eerd_done = 0x02;
|
|---|
| 2096 | e1000->info.eerd_address_offset = 2;
|
|---|
| 2097 | e1000->info.eerd_data_offset = 16;
|
|---|
| 2098 | break;
|
|---|
| 2099 | }
|
|---|
| 2100 |
|
|---|
| [1df224c] | 2101 | return EOK;
|
|---|
| [bf84871] | 2102 | }
|
|---|
| 2103 |
|
|---|
| [1df224c] | 2104 | /** Enable the I/O ports of the device.
|
|---|
| 2105 | *
|
|---|
| 2106 | * @param dev E1000 device.
|
|---|
| 2107 | *
|
|---|
| 2108 | * @return EOK if successed
|
|---|
| [cde999a] | 2109 | * @return An error code otherwise
|
|---|
| [bf84871] | 2110 | *
|
|---|
| 2111 | */
|
|---|
| [5a6cc679] | 2112 | static errno_t e1000_pio_enable(ddf_dev_t *dev)
|
|---|
| [bf84871] | 2113 | {
|
|---|
| [c4be33a] | 2114 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
|---|
| [1df224c] | 2115 |
|
|---|
| [5a6cc679] | 2116 | errno_t rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
|
|---|
| [c4be33a] | 2117 | &e1000->reg_base_virt);
|
|---|
| [1df224c] | 2118 | if (rc != EOK)
|
|---|
| [bf84871] | 2119 | return EADDRNOTAVAIL;
|
|---|
| [1df224c] | 2120 |
|
|---|
| [bf84871] | 2121 | return EOK;
|
|---|
| 2122 | }
|
|---|
| 2123 |
|
|---|
| [9916841] | 2124 | /** Probe and initialize the newly added device.
|
|---|
| [bf84871] | 2125 | *
|
|---|
| [1df224c] | 2126 | * @param dev E1000 device.
|
|---|
| 2127 | *
|
|---|
| [bf84871] | 2128 | */
|
|---|
| [5a6cc679] | 2129 | errno_t e1000_dev_add(ddf_dev_t *dev)
|
|---|
| [bf84871] | 2130 | {
|
|---|
| [e86b8f0] | 2131 | ddf_fun_t *fun;
|
|---|
| [1df224c] | 2132 |
|
|---|
| 2133 | /* Initialize device structure for E1000 */
|
|---|
| [5a6cc679] | 2134 | errno_t rc = e1000_device_initialize(dev);
|
|---|
| [bf84871] | 2135 | if (rc != EOK)
|
|---|
| 2136 | return rc;
|
|---|
| 2137 |
|
|---|
| [1df224c] | 2138 | /* Device initialization */
|
|---|
| [56fd7cf] | 2139 | nic_t *nic = ddf_dev_data_get(dev);
|
|---|
| [c4be33a] | 2140 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 2141 |
|
|---|
| [bf84871] | 2142 | /* Map registers */
|
|---|
| 2143 | rc = e1000_pio_enable(dev);
|
|---|
| 2144 | if (rc != EOK)
|
|---|
| 2145 | goto err_destroy;
|
|---|
| [1df224c] | 2146 |
|
|---|
| [c4be33a] | 2147 | e1000_initialize_registers(e1000);
|
|---|
| 2148 | rc = e1000_initialize_tx_structure(e1000);
|
|---|
| [1df224c] | 2149 | if (rc != EOK)
|
|---|
| [bf84871] | 2150 | goto err_pio;
|
|---|
| [1df224c] | 2151 |
|
|---|
| [c4be33a] | 2152 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [bf84871] | 2153 |
|
|---|
| [c4be33a] | 2154 | e1000_fill_mac_from_eeprom(e1000);
|
|---|
| 2155 | e1000_initialize_filters(e1000);
|
|---|
| [bf84871] | 2156 |
|
|---|
| [c4be33a] | 2157 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [1df224c] | 2158 |
|
|---|
| [c4be33a] | 2159 | e1000_initialize_vlan(e1000);
|
|---|
| [1df224c] | 2160 |
|
|---|
| [e86b8f0] | 2161 | fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
|
|---|
| 2162 | if (fun == NULL)
|
|---|
| [bf84871] | 2163 | goto err_tx_structure;
|
|---|
| [e86b8f0] | 2164 | nic_set_ddf_fun(nic, fun);
|
|---|
| [56fd7cf] | 2165 | ddf_fun_set_ops(fun, &e1000_dev_ops);
|
|---|
| [bf84871] | 2166 |
|
|---|
| [071a1ddb] | 2167 | int irq_cap;
|
|---|
| 2168 | rc = e1000_register_int_handler(nic, &irq_cap);
|
|---|
| 2169 | if (rc != EOK) {
|
|---|
| [e86b8f0] | 2170 | goto err_fun_create;
|
|---|
| [e9d15d9] | 2171 | }
|
|---|
| [bf84871] | 2172 |
|
|---|
| [c4be33a] | 2173 | rc = e1000_initialize_rx_structure(nic);
|
|---|
| [1df224c] | 2174 | if (rc != EOK)
|
|---|
| [bf84871] | 2175 | goto err_irq;
|
|---|
| 2176 |
|
|---|
| 2177 | nic_address_t e1000_address;
|
|---|
| [c4be33a] | 2178 | e1000_get_address(e1000, &e1000_address);
|
|---|
| 2179 | rc = nic_report_address(nic, &e1000_address);
|
|---|
| [1df224c] | 2180 | if (rc != EOK)
|
|---|
| [bf84871] | 2181 | goto err_rx_structure;
|
|---|
| [1df224c] | 2182 |
|
|---|
| [bf84871] | 2183 | struct timeval period;
|
|---|
| 2184 | period.tv_sec = 0;
|
|---|
| [1df224c] | 2185 | period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
|
|---|
| [c4be33a] | 2186 | rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
|
|---|
| [1df224c] | 2187 | if (rc != EOK)
|
|---|
| [bf84871] | 2188 | goto err_rx_structure;
|
|---|
| 2189 |
|
|---|
| [e86b8f0] | 2190 | rc = ddf_fun_bind(fun);
|
|---|
| 2191 | if (rc != EOK)
|
|---|
| 2192 | goto err_fun_bind;
|
|---|
| 2193 |
|
|---|
| 2194 | rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
|
|---|
| 2195 | if (rc != EOK)
|
|---|
| 2196 | goto err_add_to_cat;
|
|---|
| 2197 |
|
|---|
| [bf84871] | 2198 | return EOK;
|
|---|
| [1df224c] | 2199 |
|
|---|
| [e86b8f0] | 2200 | err_add_to_cat:
|
|---|
| 2201 | ddf_fun_unbind(fun);
|
|---|
| 2202 | err_fun_bind:
|
|---|
| [bf84871] | 2203 | err_rx_structure:
|
|---|
| [c4be33a] | 2204 | e1000_uninitialize_rx_structure(nic);
|
|---|
| [bf84871] | 2205 | err_irq:
|
|---|
| [e9d15d9] | 2206 | unregister_interrupt_handler(dev, irq_cap);
|
|---|
| [e86b8f0] | 2207 | err_fun_create:
|
|---|
| 2208 | ddf_fun_destroy(fun);
|
|---|
| 2209 | nic_set_ddf_fun(nic, NULL);
|
|---|
| [bf84871] | 2210 | err_tx_structure:
|
|---|
| [c4be33a] | 2211 | e1000_uninitialize_tx_structure(e1000);
|
|---|
| [bf84871] | 2212 | err_pio:
|
|---|
| [1df224c] | 2213 | // TODO: e1000_pio_disable(dev);
|
|---|
| [bf84871] | 2214 | err_destroy:
|
|---|
| 2215 | e1000_dev_cleanup(dev);
|
|---|
| 2216 | return rc;
|
|---|
| [1df224c] | 2217 | }
|
|---|
| [bf84871] | 2218 |
|
|---|
| 2219 | /** Read 16-bit value from EEPROM of E1000 adapter
|
|---|
| [1df224c] | 2220 | *
|
|---|
| 2221 | * Read using the EERD register.
|
|---|
| 2222 | *
|
|---|
| 2223 | * @param device E1000 device
|
|---|
| 2224 | * @param eeprom_address 8-bit EEPROM address
|
|---|
| 2225 | *
|
|---|
| 2226 | * @return 16-bit value from EEPROM
|
|---|
| 2227 | *
|
|---|
| [bf84871] | 2228 | */
|
|---|
| [c4be33a] | 2229 | static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
|
|---|
| [bf84871] | 2230 | {
|
|---|
| [c4be33a] | 2231 | fibril_mutex_lock(&e1000->eeprom_lock);
|
|---|
| [1df224c] | 2232 |
|
|---|
| 2233 | /* Write address and START bit to EERD register */
|
|---|
| [77c2b02] | 2234 | uint32_t write_data = e1000->info.eerd_start |
|
|---|
| 2235 | (((uint32_t) eeprom_address) <<
|
|---|
| 2236 | e1000->info.eerd_address_offset);
|
|---|
| [c4be33a] | 2237 | E1000_REG_WRITE(e1000, E1000_EERD, write_data);
|
|---|
| [bf84871] | 2238 |
|
|---|
| [c4be33a] | 2239 | uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
|
|---|
| [77c2b02] | 2240 | while ((eerd & e1000->info.eerd_done) == 0) {
|
|---|
| [f300523] | 2241 | async_usleep(1);
|
|---|
| [c4be33a] | 2242 | eerd = E1000_REG_READ(e1000, E1000_EERD);
|
|---|
| [bf84871] | 2243 | }
|
|---|
| 2244 |
|
|---|
| [c4be33a] | 2245 | fibril_mutex_unlock(&e1000->eeprom_lock);
|
|---|
| [1df224c] | 2246 |
|
|---|
| [77c2b02] | 2247 | return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
|
|---|
| [bf84871] | 2248 | }
|
|---|
| 2249 |
|
|---|
| 2250 | /** Get MAC address of the E1000 adapter
|
|---|
| 2251 | *
|
|---|
| [1df224c] | 2252 | * @param device E1000 device
|
|---|
| 2253 | * @param address Place to store the address
|
|---|
| 2254 | * @param max_len Maximal addresss length to store
|
|---|
| 2255 | *
|
|---|
| 2256 | * @return EOK if succeed
|
|---|
| [cde999a] | 2257 | * @return An error code otherwise
|
|---|
| [1df224c] | 2258 | *
|
|---|
| [bf84871] | 2259 | */
|
|---|
| [5a6cc679] | 2260 | static errno_t e1000_get_address(e1000_t *e1000, nic_address_t *address)
|
|---|
| [bf84871] | 2261 | {
|
|---|
| [c4be33a] | 2262 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| [1df224c] | 2263 |
|
|---|
| 2264 | uint8_t *mac0_dest = (uint8_t *) address->address;
|
|---|
| 2265 | uint8_t *mac1_dest = (uint8_t *) address->address + 1;
|
|---|
| 2266 | uint8_t *mac2_dest = (uint8_t *) address->address + 2;
|
|---|
| 2267 | uint8_t *mac3_dest = (uint8_t *) address->address + 3;
|
|---|
| 2268 | uint8_t *mac4_dest = (uint8_t *) address->address + 4;
|
|---|
| 2269 | uint8_t *mac5_dest = (uint8_t *) address->address + 5;
|
|---|
| 2270 |
|
|---|
| [c4be33a] | 2271 | uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
|---|
| 2272 | uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
|
|---|
| [bf84871] | 2273 |
|
|---|
| 2274 | *mac0_dest = (uint8_t) ral;
|
|---|
| 2275 | *mac1_dest = (uint8_t) (ral >> 8);
|
|---|
| 2276 | *mac2_dest = (uint8_t) (ral >> 16);
|
|---|
| 2277 | *mac3_dest = (uint8_t) (ral >> 24);
|
|---|
| 2278 | *mac4_dest = (uint8_t) rah;
|
|---|
| 2279 | *mac5_dest = (uint8_t) (rah >> 8);
|
|---|
| [1df224c] | 2280 |
|
|---|
| [c4be33a] | 2281 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [bf84871] | 2282 | return EOK;
|
|---|
| 2283 | };
|
|---|
| 2284 |
|
|---|
| 2285 | /** Set card MAC address
|
|---|
| 2286 | *
|
|---|
| [1df224c] | 2287 | * @param device E1000 device
|
|---|
| 2288 | * @param address Address
|
|---|
| 2289 | *
|
|---|
| 2290 | * @return EOK if succeed
|
|---|
| [cde999a] | 2291 | * @return An error code otherwise
|
|---|
| [bf84871] | 2292 | */
|
|---|
| [5a6cc679] | 2293 | static errno_t e1000_set_addr(ddf_fun_t *fun, const nic_address_t *addr)
|
|---|
| [bf84871] | 2294 | {
|
|---|
| [56fd7cf] | 2295 | nic_t *nic = NIC_DATA_FUN(fun);
|
|---|
| [c4be33a] | 2296 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| [1df224c] | 2297 |
|
|---|
| [c4be33a] | 2298 | fibril_mutex_lock(&e1000->rx_lock);
|
|---|
| 2299 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| [1df224c] | 2300 |
|
|---|
| [5a6cc679] | 2301 | errno_t rc = nic_report_address(nic, addr);
|
|---|
| [1df224c] | 2302 | if (rc == EOK)
|
|---|
| [c4be33a] | 2303 | e1000_write_receive_address(e1000, 0, addr, false);
|
|---|
| [1df224c] | 2304 |
|
|---|
| [c4be33a] | 2305 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| 2306 | fibril_mutex_unlock(&e1000->rx_lock);
|
|---|
| [1df224c] | 2307 |
|
|---|
| [bf84871] | 2308 | return rc;
|
|---|
| 2309 | }
|
|---|
| 2310 |
|
|---|
| [c4be33a] | 2311 | static void e1000_eeprom_get_address(e1000_t *e1000,
|
|---|
| [1df224c] | 2312 | nic_address_t *address)
|
|---|
| [bf84871] | 2313 | {
|
|---|
| [1df224c] | 2314 | uint16_t *mac0_dest = (uint16_t *) address->address;
|
|---|
| 2315 | uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
|
|---|
| 2316 | uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
|
|---|
| 2317 |
|
|---|
| [c4be33a] | 2318 | *mac0_dest = e1000_eeprom_read(e1000, 0);
|
|---|
| 2319 | *mac2_dest = e1000_eeprom_read(e1000, 1);
|
|---|
| 2320 | *mac4_dest = e1000_eeprom_read(e1000, 2);
|
|---|
| [bf84871] | 2321 | }
|
|---|
| 2322 |
|
|---|
| [6d8455d] | 2323 | /** Send frame
|
|---|
| [1df224c] | 2324 | *
|
|---|
| [c4be33a] | 2325 | * @param nic NIC driver data structure
|
|---|
| [6d8455d] | 2326 | * @param data Frame data
|
|---|
| 2327 | * @param size Frame size in bytes
|
|---|
| [bf84871] | 2328 | *
|
|---|
| [1df224c] | 2329 | * @return EOK if succeed
|
|---|
| 2330 | * @return Error code in the case of error
|
|---|
| [bf84871] | 2331 | *
|
|---|
| 2332 | */
|
|---|
| [6d8455d] | 2333 | static void e1000_send_frame(nic_t *nic, void *data, size_t size)
|
|---|
| [bf84871] | 2334 | {
|
|---|
| [c4be33a] | 2335 | assert(nic);
|
|---|
| [1df224c] | 2336 |
|
|---|
| [c4be33a] | 2337 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
|---|
| 2338 | fibril_mutex_lock(&e1000->tx_lock);
|
|---|
| [1df224c] | 2339 |
|
|---|
| [c4be33a] | 2340 | uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
|
|---|
| [1df224c] | 2341 | e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
|
|---|
| [c4be33a] | 2342 | (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
|
|---|
| [1df224c] | 2343 |
|
|---|
| [bf84871] | 2344 | bool descriptor_available = false;
|
|---|
| [1df224c] | 2345 |
|
|---|
| 2346 | /* Descriptor never used */
|
|---|
| 2347 | if (tx_descriptor_addr->length == 0)
|
|---|
| [bf84871] | 2348 | descriptor_available = true;
|
|---|
| [1df224c] | 2349 |
|
|---|
| 2350 | /* Descriptor done */
|
|---|
| [6d8455d] | 2351 | if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
|
|---|
| [bf84871] | 2352 | descriptor_available = true;
|
|---|
| [1df224c] | 2353 |
|
|---|
| 2354 | if (!descriptor_available) {
|
|---|
| [1bc35b5] | 2355 | /* Frame lost */
|
|---|
| [c4be33a] | 2356 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| [bf84871] | 2357 | return;
|
|---|
| 2358 | }
|
|---|
| [1df224c] | 2359 |
|
|---|
| [6d8455d] | 2360 | memcpy(e1000->tx_frame_virt[tdt], data, size);
|
|---|
| [1df224c] | 2361 |
|
|---|
| [6d8455d] | 2362 | tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
|
|---|
| 2363 | tx_descriptor_addr->length = size;
|
|---|
| [1df224c] | 2364 |
|
|---|
| 2365 | /*
|
|---|
| 2366 | * Report status to STATUS.DD (descriptor done),
|
|---|
| 2367 | * add ethernet CRC, end of packet.
|
|---|
| 2368 | */
|
|---|
| 2369 | tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
|
|---|
| 2370 | TXDESCRIPTOR_COMMAND_IFCS |
|
|---|
| 2371 | TXDESCRIPTOR_COMMAND_EOP;
|
|---|
| 2372 |
|
|---|
| [bf84871] | 2373 | tx_descriptor_addr->checksum_offset = 0;
|
|---|
| 2374 | tx_descriptor_addr->status = 0;
|
|---|
| [c4be33a] | 2375 | if (e1000->vlan_tag_add) {
|
|---|
| 2376 | tx_descriptor_addr->special = e1000->vlan_tag;
|
|---|
| [bf84871] | 2377 | tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
|
|---|
| [1df224c] | 2378 | } else
|
|---|
| 2379 | tx_descriptor_addr->special = 0;
|
|---|
| 2380 |
|
|---|
| [bf84871] | 2381 | tx_descriptor_addr->checksum_start_field = 0;
|
|---|
| 2382 |
|
|---|
| [1df224c] | 2383 | tdt++;
|
|---|
| [1bc35b5] | 2384 | if (tdt == E1000_TX_FRAME_COUNT)
|
|---|
| [bf84871] | 2385 | tdt = 0;
|
|---|
| [1df224c] | 2386 |
|
|---|
| [c4be33a] | 2387 | E1000_REG_WRITE(e1000, E1000_TDT, tdt);
|
|---|
| [1df224c] | 2388 |
|
|---|
| [c4be33a] | 2389 | fibril_mutex_unlock(&e1000->tx_lock);
|
|---|
| [bf84871] | 2390 | }
|
|---|
| 2391 |
|
|---|
| 2392 | int main(void)
|
|---|
| 2393 | {
|
|---|
| [869d936] | 2394 | printf("%s: HelenOS E1000 network adapter driver\n", NAME);
|
|---|
| 2395 |
|
|---|
| 2396 | if (nic_driver_init(NAME) != EOK)
|
|---|
| 2397 | return 1;
|
|---|
| [1df224c] | 2398 |
|
|---|
| [c4be33a] | 2399 | nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
|
|---|
| 2400 | &e1000_nic_iface);
|
|---|
| [77c2b02] | 2401 |
|
|---|
| [267f235] | 2402 | ddf_log_init(NAME);
|
|---|
| [bf84871] | 2403 | return ddf_driver_main(&e1000_driver);
|
|---|
| 2404 | }
|
|---|