[bf84871] | 1 | /*
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| 2 | * Copyright (c) 2011 Zdenek Bouska
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[1df224c] | 29 | /** @file e1k.c
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| 30 | *
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| 31 | * Driver for Intel Pro/1000 8254x Family of Gigabit Ethernet Controllers
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[bf84871] | 32 | *
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| 33 | */
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| 34 |
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| 35 | #include <assert.h>
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| 36 | #include <stdio.h>
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| 37 | #include <errno.h>
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| 38 | #include <adt/list.h>
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| 39 | #include <align.h>
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| 40 | #include <byteorder.h>
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| 41 | #include <sysinfo.h>
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| 42 | #include <ipc/irc.h>
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| 43 | #include <ipc/ns.h>
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| 44 | #include <libarch/ddi.h>
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| 45 | #include <as.h>
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[77c2b02] | 46 | #include <ddf/log.h>
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[bf84871] | 47 | #include <ddf/interrupt.h>
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| 48 | #include <devman.h>
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| 49 | #include <device/hw_res_parsed.h>
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| 50 | #include <device/pci.h>
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| 51 | #include <nic.h>
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| 52 | #include <nil_remote.h>
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| 53 | #include <ops/nic.h>
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[1df224c] | 54 | #include "e1k.h"
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[bf84871] | 55 |
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[1df224c] | 56 | #define NAME "e1k"
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[bf84871] | 57 |
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[9916841] | 58 | #define E1000_DEFAULT_INTERRUPT_INTERVAL_USEC 250
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[bf84871] | 59 |
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[1df224c] | 60 | /* Must be power of 8 */
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[1bc35b5] | 61 | #define E1000_RX_FRAME_COUNT 128
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| 62 | #define E1000_TX_FRAME_COUNT 128
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[bf84871] | 63 |
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[1df224c] | 64 | #define E1000_RECEIVE_ADDRESS 16
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[bf84871] | 65 |
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[1bc35b5] | 66 | /** Maximum sending frame size */
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[6d8455d] | 67 | #define E1000_MAX_SEND_FRAME_SIZE 2048
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[321052f7] | 68 | /** Maximum receiving frame size */
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[1bc35b5] | 69 | #define E1000_MAX_RECEIVE_FRAME_SIZE 2048
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[bf84871] | 70 |
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| 71 | /** nic_driver_data_t* -> e1000_t* cast */
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[c4be33a] | 72 | #define DRIVER_DATA_NIC(nic) \
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| 73 | ((e1000_t *) nic_get_specific(nic))
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[1df224c] | 74 |
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[bf84871] | 75 | /** device_t* -> nic_driver_data_t* cast */
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[1df224c] | 76 | #define NIC_DATA_DEV(dev) \
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| 77 | ((nic_t *) ((dev)->driver_data))
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| 78 |
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[bf84871] | 79 | /** device_t* -> e1000_t* cast */
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[1df224c] | 80 | #define DRIVER_DATA_DEV(dev) \
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| 81 | (DRIVER_DATA_NIC(NIC_DATA_DEV(dev)))
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[bf84871] | 82 |
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[1df224c] | 83 | /** Cast pointer to uint64_t
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| 84 | *
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| 85 | * @param ptr Pointer to cast
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| 86 | *
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| 87 | * @return The uint64_t pointer representation.
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[bf84871] | 88 | *
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| 89 | */
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[1df224c] | 90 | #define PTR_TO_U64(ptr) ((uint64_t) ((uintptr_t) (ptr)))
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[bf84871] | 91 |
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| 92 | /** Cast the memaddr part to the void*
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| 93 | *
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[1df224c] | 94 | * @param memaddr The memaddr value
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| 95 | *
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[bf84871] | 96 | */
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[1df224c] | 97 | #define MEMADDR_TO_PTR(memaddr) ((void *) ((size_t) (memaddr)))
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| 98 |
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[c4be33a] | 99 | #define E1000_REG_BASE(e1000) \
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| 100 | ((e1000)->reg_base_virt)
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[bf84871] | 101 |
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[c4be33a] | 102 | #define E1000_REG_ADDR(e1000, reg) \
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| 103 | ((uint32_t *) (E1000_REG_BASE(e1000) + reg))
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[bf84871] | 104 |
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[c4be33a] | 105 | #define E1000_REG_READ(e1000, reg) \
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| 106 | (pio_read_32(E1000_REG_ADDR(e1000, reg)))
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[1df224c] | 107 |
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[c4be33a] | 108 | #define E1000_REG_WRITE(e1000, reg, value) \
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| 109 | (pio_write_32(E1000_REG_ADDR(e1000, reg), value))
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[bf84871] | 110 |
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| 111 | /** E1000 device data */
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[c4be33a] | 112 | typedef struct {
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[77c2b02] | 113 | /** Device configuration */
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| 114 | e1000_info_t info;
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| 115 |
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[bf84871] | 116 | /** Physical registers base address */
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[c4be33a] | 117 | void *reg_base_phys;
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[bf84871] | 118 | /** Virtual registers base address */
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[c4be33a] | 119 | void *reg_base_virt;
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| 120 |
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| 121 | /** Physical tx ring address */
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| 122 | void *tx_ring_phys;
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| 123 | /** Virtual tx ring address */
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| 124 | void *tx_ring_virt;
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| 125 |
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[6d8455d] | 126 | /** Ring of TX frames, physical address */
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| 127 | void **tx_frame_phys;
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| 128 | /** Ring of TX frames, virtual address */
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| 129 | void **tx_frame_virt;
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[c4be33a] | 130 |
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| 131 | /** Physical rx ring address */
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| 132 | void *rx_ring_phys;
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| 133 | /** Virtual rx ring address */
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| 134 | void *rx_ring_virt;
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| 135 |
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[1bc35b5] | 136 | /** Ring of RX frames, physical address */
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| 137 | void **rx_frame_phys;
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| 138 | /** Ring of RX frames, virtual address */
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| 139 | void **rx_frame_virt;
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[c4be33a] | 140 |
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[bf84871] | 141 | /** VLAN tag */
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| 142 | uint16_t vlan_tag;
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[c4be33a] | 143 |
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[1bc35b5] | 144 | /** Add VLAN tag to frame */
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[1df224c] | 145 | bool vlan_tag_add;
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[c4be33a] | 146 |
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[bf84871] | 147 | /** Used unicast Receive Address count */
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| 148 | unsigned int unicast_ra_count;
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[c4be33a] | 149 |
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[1df224c] | 150 | /** Used milticast Receive addrress count */
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[bf84871] | 151 | unsigned int multicast_ra_count;
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[c4be33a] | 152 |
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[bf84871] | 153 | /** The irq assigned */
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| 154 | int irq;
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[c4be33a] | 155 |
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[bf84871] | 156 | /** Lock for CTRL register */
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| 157 | fibril_mutex_t ctrl_lock;
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[c4be33a] | 158 |
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[bf84871] | 159 | /** Lock for receiver */
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| 160 | fibril_mutex_t rx_lock;
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[c4be33a] | 161 |
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[bf84871] | 162 | /** Lock for transmitter */
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| 163 | fibril_mutex_t tx_lock;
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[c4be33a] | 164 |
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[bf84871] | 165 | /** Lock for EEPROM access */
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| 166 | fibril_mutex_t eeprom_lock;
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| 167 | } e1000_t;
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| 168 |
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| 169 | /** Global mutex for work with shared irq structure */
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| 170 | FIBRIL_MUTEX_INITIALIZE(irq_reg_mutex);
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| 171 |
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| 172 | static int e1000_get_address(e1000_t *, nic_address_t *);
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[1df224c] | 173 | static void e1000_eeprom_get_address(e1000_t *, nic_address_t *);
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| 174 | static int e1000_set_addr(ddf_fun_t *, const nic_address_t *);
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[bf84871] | 175 |
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[1df224c] | 176 | static int e1000_defective_get_mode(ddf_fun_t *, uint32_t *);
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| 177 | static int e1000_defective_set_mode(ddf_fun_t *, uint32_t);
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[bf84871] | 178 |
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[1df224c] | 179 | static int e1000_get_cable_state(ddf_fun_t *, nic_cable_state_t *);
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| 180 | static int e1000_get_device_info(ddf_fun_t *, nic_device_info_t *);
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| 181 | static int e1000_get_operation_mode(ddf_fun_t *, int *,
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| 182 | nic_channel_mode_t *, nic_role_t *);
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| 183 | static int e1000_set_operation_mode(ddf_fun_t *, int,
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| 184 | nic_channel_mode_t, nic_role_t);
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| 185 | static int e1000_autoneg_enable(ddf_fun_t *, uint32_t);
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| 186 | static int e1000_autoneg_disable(ddf_fun_t *);
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| 187 | static int e1000_autoneg_restart(ddf_fun_t *);
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[bf84871] | 188 |
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[1df224c] | 189 | static int e1000_vlan_set_tag(ddf_fun_t *, uint16_t, bool, bool);
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[bf84871] | 190 |
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| 191 | /** Network interface options for E1000 card driver */
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| 192 | static nic_iface_t e1000_nic_iface;
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| 193 |
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| 194 | /** Network interface options for E1000 card driver */
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| 195 | static nic_iface_t e1000_nic_iface = {
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| 196 | .set_address = &e1000_set_addr,
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| 197 | .get_device_info = &e1000_get_device_info,
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| 198 | .get_cable_state = &e1000_get_cable_state,
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| 199 | .get_operation_mode = &e1000_get_operation_mode,
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| 200 | .set_operation_mode = &e1000_set_operation_mode,
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| 201 | .autoneg_enable = &e1000_autoneg_enable,
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| 202 | .autoneg_disable = &e1000_autoneg_disable,
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| 203 | .autoneg_restart = &e1000_autoneg_restart,
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| 204 | .vlan_set_tag = &e1000_vlan_set_tag,
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| 205 | .defective_get_mode = &e1000_defective_get_mode,
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| 206 | .defective_set_mode = &e1000_defective_set_mode,
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| 207 | };
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| 208 |
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| 209 | /** Basic device operations for E1000 driver */
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| 210 | static ddf_dev_ops_t e1000_dev_ops;
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| 211 |
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[9916841] | 212 | static int e1000_dev_add(ddf_dev_t *);
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[bf84871] | 213 |
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| 214 | /** Basic driver operations for E1000 driver */
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| 215 | static driver_ops_t e1000_driver_ops = {
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[9916841] | 216 | .dev_add = e1000_dev_add
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[bf84871] | 217 | };
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| 218 |
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| 219 | /** Driver structure for E1000 driver */
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| 220 | static driver_t e1000_driver = {
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| 221 | .name = NAME,
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| 222 | .driver_ops = &e1000_driver_ops
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| 223 | };
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| 224 |
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| 225 | /* The default implementation callbacks */
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[1df224c] | 226 | static int e1000_on_activating(nic_t *);
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| 227 | static int e1000_on_stopping(nic_t *);
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[6d8455d] | 228 | static void e1000_send_frame(nic_t *, void *, size_t);
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[bf84871] | 229 |
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| 230 | /** Commands to deal with interrupt
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| 231 | *
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| 232 | */
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| 233 | irq_cmd_t e1000_irq_commands[] = {
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[1df224c] | 234 | {
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| 235 | /* Get the interrupt status */
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| 236 | .cmd = CMD_PIO_READ_32,
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| 237 | .addr = NULL,
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| 238 | .dstarg = 2
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| 239 | },
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| 240 | {
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| 241 | .cmd = CMD_PREDICATE,
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| 242 | .value = 2,
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| 243 | .srcarg = 2
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| 244 | },
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| 245 | {
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| 246 | /* Disable interrupts until interrupt routine is finished */
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| 247 | .cmd = CMD_PIO_WRITE_32,
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| 248 | .addr = NULL,
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[c4be33a] | 249 | .value = 0xffffffff
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[1df224c] | 250 | },
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| 251 | {
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| 252 | .cmd = CMD_ACCEPT
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| 253 | }
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[bf84871] | 254 | };
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| 255 |
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| 256 | /** Interrupt code definition */
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| 257 | irq_code_t e1000_irq_code = {
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[1df224c] | 258 | .cmdcount = sizeof(e1000_irq_commands) / sizeof(irq_cmd_t),
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[bf84871] | 259 | .cmds = e1000_irq_commands
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| 260 | };
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| 261 |
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| 262 | /** Get the device information
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| 263 | *
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[1df224c] | 264 | * @param dev NIC device
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| 265 | * @param info Information to fill
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| 266 | *
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| 267 | * @return EOK
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| 268 | *
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[bf84871] | 269 | */
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| 270 | static int e1000_get_device_info(ddf_fun_t *dev, nic_device_info_t *info)
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| 271 | {
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| 272 | assert(dev);
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| 273 | assert(info);
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[1df224c] | 274 |
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[bf84871] | 275 | bzero(info, sizeof(nic_device_info_t));
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[1df224c] | 276 |
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| 277 | info->vendor_id = 0x8086;
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| 278 | str_cpy(info->vendor_name, NIC_VENDOR_MAX_LENGTH,
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| 279 | "Intel Corporation");
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| 280 | str_cpy(info->model_name, NIC_MODEL_MAX_LENGTH,
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| 281 | "Intel Pro");
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| 282 |
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[bf84871] | 283 | info->ethernet_support[ETH_10M] = ETH_10BASE_T;
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| 284 | info->ethernet_support[ETH_100M] = ETH_100BASE_TX;
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| 285 | info->ethernet_support[ETH_1000M] = ETH_1000BASE_T;
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[1df224c] | 286 |
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[bf84871] | 287 | return EOK;
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| 288 | }
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| 289 |
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| 290 | /** Check the cable state
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| 291 | *
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[1df224c] | 292 | * @param[in] dev device
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| 293 | * @param[out] state state to fill
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| 294 | *
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| 295 | * @return EOK
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| 296 | *
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[bf84871] | 297 | */
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| 298 | static int e1000_get_cable_state(ddf_fun_t *dev, nic_cable_state_t *state)
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| 299 | {
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| 300 | assert(dev);
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| 301 | assert(DRIVER_DATA_DEV(dev));
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| 302 | assert(state);
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[1df224c] | 303 |
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[c4be33a] | 304 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
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| 305 | if (E1000_REG_READ(e1000, E1000_STATUS) & (STATUS_LU))
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[bf84871] | 306 | *state = NIC_CS_PLUGGED;
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[1df224c] | 307 | else
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[bf84871] | 308 | *state = NIC_CS_UNPLUGGED;
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[1df224c] | 309 |
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[bf84871] | 310 | return EOK;
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| 311 | }
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| 312 |
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[1df224c] | 313 | static uint16_t e1000_calculate_itr_interval_from_usecs(suseconds_t useconds)
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| 314 | {
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[bf84871] | 315 | return useconds * 4;
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| 316 | }
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| 317 |
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| 318 | /** Get operation mode of the device
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[1df224c] | 319 | *
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[bf84871] | 320 | */
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| 321 | static int e1000_get_operation_mode(ddf_fun_t *dev, int *speed,
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| 322 | nic_channel_mode_t *duplex, nic_role_t *role)
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| 323 | {
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[c4be33a] | 324 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
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| 325 | uint32_t status = E1000_REG_READ(e1000, E1000_STATUS);
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[1df224c] | 326 |
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| 327 | if (status & STATUS_FD)
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[bf84871] | 328 | *duplex = NIC_CM_FULL_DUPLEX;
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[1df224c] | 329 | else
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[bf84871] | 330 | *duplex = NIC_CM_HALF_DUPLEX;
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[1df224c] | 331 |
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| 332 | uint32_t speed_bits =
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| 333 | (status >> STATUS_SPEED_SHIFT) & STATUS_SPEED_ALL;
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| 334 |
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| 335 | if (speed_bits == STATUS_SPEED_10)
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[bf84871] | 336 | *speed = 10;
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[1df224c] | 337 | else if (speed_bits == STATUS_SPEED_100)
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[bf84871] | 338 | *speed = 100;
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[1df224c] | 339 | else if ((speed_bits == STATUS_SPEED_1000A) ||
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| 340 | (speed_bits == STATUS_SPEED_1000B))
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[bf84871] | 341 | *speed = 1000;
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[1df224c] | 342 |
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[bf84871] | 343 | *role = NIC_ROLE_UNKNOWN;
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| 344 | return EOK;
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| 345 | }
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| 346 |
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[c4be33a] | 347 | static void e1000_link_restart(e1000_t *e1000)
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[bf84871] | 348 | {
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[c4be33a] | 349 | fibril_mutex_lock(&e1000->ctrl_lock);
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[1df224c] | 350 |
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[c4be33a] | 351 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
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[bf84871] | 352 |
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| 353 | if (ctrl & CTRL_SLU) {
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| 354 | ctrl &= ~(CTRL_SLU);
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[c4be33a] | 355 | fibril_mutex_unlock(&e1000->ctrl_lock);
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[bf84871] | 356 | usleep(10);
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[c4be33a] | 357 | fibril_mutex_lock(&e1000->ctrl_lock);
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[bf84871] | 358 | ctrl |= CTRL_SLU;
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| 359 | }
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[1df224c] | 360 |
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[c4be33a] | 361 | fibril_mutex_unlock(&e1000->ctrl_lock);
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[bf84871] | 362 |
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[c4be33a] | 363 | e1000_link_restart(e1000);
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[bf84871] | 364 | }
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| 365 |
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| 366 | /** Set operation mode of the device
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| 367 | *
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| 368 | */
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| 369 | static int e1000_set_operation_mode(ddf_fun_t *dev, int speed,
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| 370 | nic_channel_mode_t duplex, nic_role_t role)
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| 371 | {
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[1df224c] | 372 | if ((speed != 10) && (speed != 100) && (speed != 1000))
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[bf84871] | 373 | return EINVAL;
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[1df224c] | 374 |
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| 375 | if ((duplex != NIC_CM_HALF_DUPLEX) && (duplex != NIC_CM_FULL_DUPLEX))
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[bf84871] | 376 | return EINVAL;
|
---|
[1df224c] | 377 |
|
---|
[c4be33a] | 378 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
---|
[1df224c] | 379 |
|
---|
[c4be33a] | 380 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
| 381 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[1df224c] | 382 |
|
---|
[bf84871] | 383 | ctrl |= CTRL_FRCSPD;
|
---|
| 384 | ctrl |= CTRL_FRCDPLX;
|
---|
| 385 | ctrl &= ~(CTRL_ASDE);
|
---|
[1df224c] | 386 |
|
---|
| 387 | if (duplex == NIC_CM_FULL_DUPLEX)
|
---|
[bf84871] | 388 | ctrl |= CTRL_FD;
|
---|
[1df224c] | 389 | else
|
---|
[bf84871] | 390 | ctrl &= ~(CTRL_FD);
|
---|
| 391 |
|
---|
| 392 | ctrl &= ~(CTRL_SPEED_MASK);
|
---|
[1df224c] | 393 | if (speed == 1000)
|
---|
[bf84871] | 394 | ctrl |= CTRL_SPEED_1000 << CTRL_SPEED_SHIFT;
|
---|
[1df224c] | 395 | else if (speed == 100)
|
---|
[bf84871] | 396 | ctrl |= CTRL_SPEED_100 << CTRL_SPEED_SHIFT;
|
---|
[1df224c] | 397 | else
|
---|
[bf84871] | 398 | ctrl |= CTRL_SPEED_10 << CTRL_SPEED_SHIFT;
|
---|
[1df224c] | 399 |
|
---|
[c4be33a] | 400 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[1df224c] | 401 |
|
---|
[c4be33a] | 402 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
[1df224c] | 403 |
|
---|
[c4be33a] | 404 | e1000_link_restart(e1000);
|
---|
[1df224c] | 405 |
|
---|
[bf84871] | 406 | return EOK;
|
---|
| 407 | }
|
---|
| 408 |
|
---|
[1df224c] | 409 | /** Enable auto-negotiation
|
---|
| 410 | *
|
---|
| 411 | * @param dev Device to update
|
---|
| 412 | * @param advertisement Ignored on E1000
|
---|
| 413 | *
|
---|
| 414 | * @return EOK if advertisement mode set successfully
|
---|
[bf84871] | 415 | *
|
---|
| 416 | */
|
---|
| 417 | static int e1000_autoneg_enable(ddf_fun_t *dev, uint32_t advertisement)
|
---|
| 418 | {
|
---|
[c4be33a] | 419 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
---|
[1df224c] | 420 |
|
---|
[c4be33a] | 421 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[1df224c] | 422 |
|
---|
[c4be33a] | 423 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[1df224c] | 424 |
|
---|
[bf84871] | 425 | ctrl &= ~(CTRL_FRCSPD);
|
---|
| 426 | ctrl &= ~(CTRL_FRCDPLX);
|
---|
| 427 | ctrl |= CTRL_ASDE;
|
---|
[1df224c] | 428 |
|
---|
[c4be33a] | 429 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[1df224c] | 430 |
|
---|
[c4be33a] | 431 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
[1df224c] | 432 |
|
---|
[c4be33a] | 433 | e1000_link_restart(e1000);
|
---|
[1df224c] | 434 |
|
---|
[bf84871] | 435 | return EOK;
|
---|
| 436 | }
|
---|
| 437 |
|
---|
[1df224c] | 438 | /** Disable auto-negotiation
|
---|
| 439 | *
|
---|
| 440 | * @param dev Device to update
|
---|
| 441 | *
|
---|
| 442 | * @return EOK
|
---|
[bf84871] | 443 | *
|
---|
| 444 | */
|
---|
| 445 | static int e1000_autoneg_disable(ddf_fun_t *dev)
|
---|
| 446 | {
|
---|
[c4be33a] | 447 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
---|
[1df224c] | 448 |
|
---|
[c4be33a] | 449 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[1df224c] | 450 |
|
---|
[c4be33a] | 451 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[1df224c] | 452 |
|
---|
[bf84871] | 453 | ctrl |= CTRL_FRCSPD;
|
---|
| 454 | ctrl |= CTRL_FRCDPLX;
|
---|
| 455 | ctrl &= ~(CTRL_ASDE);
|
---|
[1df224c] | 456 |
|
---|
[c4be33a] | 457 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[1df224c] | 458 |
|
---|
[c4be33a] | 459 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
[1df224c] | 460 |
|
---|
[c4be33a] | 461 | e1000_link_restart(e1000);
|
---|
[1df224c] | 462 |
|
---|
[bf84871] | 463 | return EOK;
|
---|
| 464 | }
|
---|
| 465 |
|
---|
[1df224c] | 466 | /** Restart auto-negotiation
|
---|
| 467 | *
|
---|
| 468 | * @param dev Device to update
|
---|
| 469 | *
|
---|
| 470 | * @return EOK if advertisement mode set successfully
|
---|
[bf84871] | 471 | *
|
---|
| 472 | */
|
---|
| 473 | static int e1000_autoneg_restart(ddf_fun_t *dev)
|
---|
| 474 | {
|
---|
| 475 | return e1000_autoneg_enable(dev, 0);
|
---|
| 476 | }
|
---|
| 477 |
|
---|
[1bc35b5] | 478 | /** Get state of acceptance of weird frames
|
---|
[bf84871] | 479 | *
|
---|
[1df224c] | 480 | * @param device Device to check
|
---|
| 481 | * @param[out] mode Current mode
|
---|
| 482 | *
|
---|
[bf84871] | 483 | */
|
---|
| 484 | static int e1000_defective_get_mode(ddf_fun_t *device, uint32_t *mode)
|
---|
| 485 | {
|
---|
[c4be33a] | 486 | e1000_t *e1000 = DRIVER_DATA_DEV(device);
|
---|
[1df224c] | 487 |
|
---|
[bf84871] | 488 | *mode = 0;
|
---|
[c4be33a] | 489 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[1df224c] | 490 | if (rctl & RCTL_SBP)
|
---|
[bf84871] | 491 | *mode = NIC_DEFECTIVE_BAD_CRC | NIC_DEFECTIVE_SHORT;
|
---|
[1df224c] | 492 |
|
---|
[bf84871] | 493 | return EOK;
|
---|
| 494 | };
|
---|
| 495 |
|
---|
[1bc35b5] | 496 | /** Set acceptance of weird frames
|
---|
[bf84871] | 497 | *
|
---|
[1df224c] | 498 | * @param device Device to update
|
---|
| 499 | * @param mode Mode to set
|
---|
| 500 | *
|
---|
| 501 | * @return ENOTSUP if the mode is not supported
|
---|
| 502 | * @return EOK of mode was set
|
---|
| 503 | *
|
---|
[bf84871] | 504 | */
|
---|
| 505 | static int e1000_defective_set_mode(ddf_fun_t *device, uint32_t mode)
|
---|
| 506 | {
|
---|
[c4be33a] | 507 | e1000_t *e1000 = DRIVER_DATA_DEV(device);
|
---|
[bf84871] | 508 | int rc = EOK;
|
---|
[1df224c] | 509 |
|
---|
[c4be33a] | 510 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 511 |
|
---|
[c4be33a] | 512 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 513 | bool short_mode = (mode & NIC_DEFECTIVE_SHORT ? true : false);
|
---|
| 514 | bool bad_mode = (mode & NIC_DEFECTIVE_BAD_CRC ? true : false);
|
---|
[1df224c] | 515 |
|
---|
| 516 | if (short_mode && bad_mode)
|
---|
[bf84871] | 517 | rctl |= RCTL_SBP;
|
---|
[1df224c] | 518 | else if ((!short_mode) && (!bad_mode))
|
---|
[bf84871] | 519 | rctl &= ~RCTL_SBP;
|
---|
[1df224c] | 520 | else
|
---|
[bf84871] | 521 | rc = ENOTSUP;
|
---|
[1df224c] | 522 |
|
---|
[c4be33a] | 523 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[1df224c] | 524 |
|
---|
[c4be33a] | 525 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 526 | return rc;
|
---|
| 527 | };
|
---|
| 528 |
|
---|
| 529 | /** Write receive address to RA registr
|
---|
| 530 | *
|
---|
[c4be33a] | 531 | * @param e1000 E1000 data structure
|
---|
[1df224c] | 532 | * @param position RA register position
|
---|
| 533 | * @param address Ethernet address
|
---|
| 534 | * @param set_av_bit Set the Addtess Valid bit
|
---|
| 535 | *
|
---|
[bf84871] | 536 | */
|
---|
[c4be33a] | 537 | static void e1000_write_receive_address(e1000_t *e1000, unsigned int position,
|
---|
| 538 | const nic_address_t * address, bool set_av_bit)
|
---|
[1df224c] | 539 | {
|
---|
| 540 | uint8_t *mac0 = (uint8_t *) address->address;
|
---|
| 541 | uint8_t *mac1 = (uint8_t *) address->address + 1;
|
---|
| 542 | uint8_t *mac2 = (uint8_t *) address->address + 2;
|
---|
| 543 | uint8_t *mac3 = (uint8_t *) address->address + 3;
|
---|
| 544 | uint8_t *mac4 = (uint8_t *) address->address + 4;
|
---|
| 545 | uint8_t *mac5 = (uint8_t *) address->address + 5;
|
---|
| 546 |
|
---|
[bf84871] | 547 | uint32_t rah;
|
---|
| 548 | uint32_t ral;
|
---|
[1df224c] | 549 |
|
---|
[bf84871] | 550 | ral = ((*mac3) << 24) | ((*mac2) << 16) | ((*mac1) << 8) | (*mac0);
|
---|
| 551 | rah = ((*mac5) << 8) | ((*mac4));
|
---|
[1df224c] | 552 |
|
---|
| 553 | if (set_av_bit)
|
---|
[bf84871] | 554 | rah |= RAH_AV;
|
---|
[1df224c] | 555 | else
|
---|
[c4be33a] | 556 | rah |= E1000_REG_READ(e1000, E1000_RAH_ARRAY(position)) & RAH_AV;
|
---|
[1df224c] | 557 |
|
---|
[c4be33a] | 558 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
|
---|
| 559 | E1000_REG_WRITE(e1000, E1000_RAL_ARRAY(position), ral);
|
---|
[bf84871] | 560 | }
|
---|
| 561 |
|
---|
| 562 | /** Disable receive address in RA registr
|
---|
| 563 | *
|
---|
[1df224c] | 564 | * Clear Address Valid bit
|
---|
| 565 | *
|
---|
[c4be33a] | 566 | * @param e1000 E1000 data structure
|
---|
| 567 | * @param position RA register position
|
---|
[1df224c] | 568 | *
|
---|
[bf84871] | 569 | */
|
---|
[c4be33a] | 570 | static void e1000_disable_receive_address(e1000_t *e1000, unsigned int position)
|
---|
[bf84871] | 571 | {
|
---|
[c4be33a] | 572 | uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(position));
|
---|
[bf84871] | 573 | rah = rah & ~RAH_AV;
|
---|
[c4be33a] | 574 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(position), rah);
|
---|
[bf84871] | 575 | }
|
---|
| 576 |
|
---|
[1df224c] | 577 | /** Clear all unicast addresses from RA registers
|
---|
| 578 | *
|
---|
[c4be33a] | 579 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 580 | *
|
---|
| 581 | */
|
---|
[c4be33a] | 582 | static void e1000_clear_unicast_receive_addresses(e1000_t *e1000)
|
---|
[bf84871] | 583 | {
|
---|
[1df224c] | 584 | for (unsigned int ra_num = 1;
|
---|
[c4be33a] | 585 | ra_num <= e1000->unicast_ra_count;
|
---|
[1df224c] | 586 | ra_num++)
|
---|
[c4be33a] | 587 | e1000_disable_receive_address(e1000, ra_num);
|
---|
[1df224c] | 588 |
|
---|
[c4be33a] | 589 | e1000->unicast_ra_count = 0;
|
---|
[bf84871] | 590 | }
|
---|
| 591 |
|
---|
[1df224c] | 592 | /** Clear all multicast addresses from RA registers
|
---|
| 593 | *
|
---|
[c4be33a] | 594 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 595 | *
|
---|
| 596 | */
|
---|
[c4be33a] | 597 | static void e1000_clear_multicast_receive_addresses(e1000_t *e1000)
|
---|
[bf84871] | 598 | {
|
---|
[1df224c] | 599 | unsigned int first_multicast_ra_num =
|
---|
[c4be33a] | 600 | E1000_RECEIVE_ADDRESS - e1000->multicast_ra_count;
|
---|
[1df224c] | 601 |
|
---|
| 602 | for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
|
---|
| 603 | ra_num >= first_multicast_ra_num;
|
---|
| 604 | ra_num--)
|
---|
[c4be33a] | 605 | e1000_disable_receive_address(e1000, ra_num);
|
---|
[1df224c] | 606 |
|
---|
[c4be33a] | 607 | e1000->multicast_ra_count = 0;
|
---|
[bf84871] | 608 | }
|
---|
| 609 |
|
---|
[1df224c] | 610 | /** Return receive address filter positions count usable for unicast
|
---|
| 611 | *
|
---|
[c4be33a] | 612 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 613 | *
|
---|
| 614 | * @return receive address filter positions count usable for unicast
|
---|
[1df224c] | 615 | *
|
---|
[bf84871] | 616 | */
|
---|
[c4be33a] | 617 | static unsigned int get_free_unicast_address_count(e1000_t *e1000)
|
---|
[bf84871] | 618 | {
|
---|
[c4be33a] | 619 | return E1000_RECEIVE_ADDRESS - 1 - e1000->multicast_ra_count;
|
---|
[bf84871] | 620 | }
|
---|
| 621 |
|
---|
[1df224c] | 622 | /** Return receive address filter positions count usable for multicast
|
---|
| 623 | *
|
---|
[c4be33a] | 624 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 625 | *
|
---|
| 626 | * @return receive address filter positions count usable for multicast
|
---|
[1df224c] | 627 | *
|
---|
[bf84871] | 628 | */
|
---|
[c4be33a] | 629 | static unsigned int get_free_multicast_address_count(e1000_t *e1000)
|
---|
[bf84871] | 630 | {
|
---|
[c4be33a] | 631 | return E1000_RECEIVE_ADDRESS - 1 - e1000->unicast_ra_count;
|
---|
[bf84871] | 632 | }
|
---|
| 633 |
|
---|
[1df224c] | 634 | /** Write unicast receive addresses to receive address filter registers
|
---|
| 635 | *
|
---|
[c4be33a] | 636 | * @param e1000 E1000 data structure
|
---|
| 637 | * @param addr Pointer to address array
|
---|
| 638 | * @param addr_cnt Address array count
|
---|
[bf84871] | 639 | *
|
---|
| 640 | */
|
---|
[c4be33a] | 641 | static void e1000_add_unicast_receive_addresses(e1000_t *e1000,
|
---|
[1df224c] | 642 | const nic_address_t *addr, size_t addr_cnt)
|
---|
[bf84871] | 643 | {
|
---|
[c4be33a] | 644 | assert(addr_cnt <= get_free_unicast_address_count(e1000));
|
---|
[1df224c] | 645 |
|
---|
| 646 | nic_address_t *addr_iterator = (nic_address_t *) addr;
|
---|
| 647 |
|
---|
| 648 | /* ra_num = 0 is primary address */
|
---|
| 649 | for (unsigned int ra_num = 1;
|
---|
| 650 | ra_num <= addr_cnt;
|
---|
| 651 | ra_num++) {
|
---|
[c4be33a] | 652 | e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
|
---|
[bf84871] | 653 | addr_iterator++;
|
---|
| 654 | }
|
---|
| 655 | }
|
---|
| 656 |
|
---|
[1df224c] | 657 | /** Write multicast receive addresses to receive address filter registers
|
---|
| 658 | *
|
---|
[c4be33a] | 659 | * @param e1000 E1000 data structure
|
---|
| 660 | * @param addr Pointer to address array
|
---|
| 661 | * @param addr_cnt Address array count
|
---|
[bf84871] | 662 | *
|
---|
| 663 | */
|
---|
[c4be33a] | 664 | static void e1000_add_multicast_receive_addresses(e1000_t *e1000,
|
---|
[1df224c] | 665 | const nic_address_t *addr, size_t addr_cnt)
|
---|
[bf84871] | 666 | {
|
---|
[c4be33a] | 667 | assert(addr_cnt <= get_free_multicast_address_count(e1000));
|
---|
[1df224c] | 668 |
|
---|
| 669 | nic_address_t *addr_iterator = (nic_address_t *) addr;
|
---|
| 670 |
|
---|
[bf84871] | 671 | unsigned int first_multicast_ra_num = E1000_RECEIVE_ADDRESS - addr_cnt;
|
---|
[1df224c] | 672 | for (unsigned int ra_num = E1000_RECEIVE_ADDRESS - 1;
|
---|
| 673 | ra_num >= first_multicast_ra_num;
|
---|
[9916841] | 674 | ra_num--) {
|
---|
[c4be33a] | 675 | e1000_write_receive_address(e1000, ra_num, addr_iterator, true);
|
---|
[bf84871] | 676 | addr_iterator++;
|
---|
| 677 | }
|
---|
| 678 | }
|
---|
| 679 |
|
---|
[1bc35b5] | 680 | /** Disable receiving frames for default address
|
---|
[1df224c] | 681 | *
|
---|
[c4be33a] | 682 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 683 | *
|
---|
| 684 | */
|
---|
[c4be33a] | 685 | static void disable_ra0_address_filter(e1000_t *e1000)
|
---|
[bf84871] | 686 | {
|
---|
[c4be33a] | 687 | uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
---|
[bf84871] | 688 | rah0 = rah0 & ~RAH_AV;
|
---|
[c4be33a] | 689 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
|
---|
[bf84871] | 690 | }
|
---|
| 691 |
|
---|
[1bc35b5] | 692 | /** Enable receiving frames for default address
|
---|
[1df224c] | 693 | *
|
---|
[c4be33a] | 694 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 695 | *
|
---|
| 696 | */
|
---|
[c4be33a] | 697 | static void enable_ra0_address_filter(e1000_t *e1000)
|
---|
[bf84871] | 698 | {
|
---|
[c4be33a] | 699 | uint32_t rah0 = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
---|
[bf84871] | 700 | rah0 = rah0 | RAH_AV;
|
---|
[c4be33a] | 701 | E1000_REG_WRITE(e1000, E1000_RAH_ARRAY(0), rah0);
|
---|
[bf84871] | 702 | }
|
---|
| 703 |
|
---|
[1df224c] | 704 | /** Disable unicast promiscuous mode
|
---|
| 705 | *
|
---|
[c4be33a] | 706 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 707 | *
|
---|
| 708 | */
|
---|
[c4be33a] | 709 | static void e1000_disable_unicast_promisc(e1000_t *e1000)
|
---|
[bf84871] | 710 | {
|
---|
[c4be33a] | 711 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 712 | rctl = rctl & ~RCTL_UPE;
|
---|
[c4be33a] | 713 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 714 | }
|
---|
| 715 |
|
---|
[1df224c] | 716 | /** Enable unicast promiscuous mode
|
---|
| 717 | *
|
---|
[c4be33a] | 718 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 719 | *
|
---|
| 720 | */
|
---|
[c4be33a] | 721 | static void e1000_enable_unicast_promisc(e1000_t *e1000)
|
---|
[bf84871] | 722 | {
|
---|
[c4be33a] | 723 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 724 | rctl = rctl | RCTL_UPE;
|
---|
[c4be33a] | 725 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 726 | }
|
---|
| 727 |
|
---|
[1df224c] | 728 | /** Disable multicast promiscuous mode
|
---|
| 729 | *
|
---|
[c4be33a] | 730 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 731 | *
|
---|
| 732 | */
|
---|
[c4be33a] | 733 | static void e1000_disable_multicast_promisc(e1000_t *e1000)
|
---|
[bf84871] | 734 | {
|
---|
[c4be33a] | 735 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 736 | rctl = rctl & ~RCTL_MPE;
|
---|
[c4be33a] | 737 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 738 | }
|
---|
| 739 |
|
---|
[1df224c] | 740 | /** Enable multicast promiscuous mode
|
---|
| 741 | *
|
---|
[c4be33a] | 742 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 743 | *
|
---|
| 744 | */
|
---|
[c4be33a] | 745 | static void e1000_enable_multicast_promisc(e1000_t *e1000)
|
---|
[bf84871] | 746 | {
|
---|
[c4be33a] | 747 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 748 | rctl = rctl | RCTL_MPE;
|
---|
[c4be33a] | 749 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 750 | }
|
---|
| 751 |
|
---|
[1bc35b5] | 752 | /** Enable accepting of broadcast frames
|
---|
[1df224c] | 753 | *
|
---|
[c4be33a] | 754 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 755 | *
|
---|
| 756 | */
|
---|
[c4be33a] | 757 | static void e1000_enable_broadcast_accept(e1000_t *e1000)
|
---|
[bf84871] | 758 | {
|
---|
[c4be33a] | 759 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 760 | rctl = rctl | RCTL_BAM;
|
---|
[c4be33a] | 761 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 762 | }
|
---|
| 763 |
|
---|
[1bc35b5] | 764 | /** Disable accepting of broadcast frames
|
---|
[1df224c] | 765 | *
|
---|
[c4be33a] | 766 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 767 | *
|
---|
| 768 | */
|
---|
[c4be33a] | 769 | static void e1000_disable_broadcast_accept(e1000_t *e1000)
|
---|
[bf84871] | 770 | {
|
---|
[c4be33a] | 771 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 772 | rctl = rctl & ~RCTL_BAM;
|
---|
[c4be33a] | 773 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 774 | }
|
---|
| 775 |
|
---|
[1df224c] | 776 | /** Enable VLAN filtering according to VFTA registers
|
---|
| 777 | *
|
---|
[c4be33a] | 778 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 779 | *
|
---|
| 780 | */
|
---|
[c4be33a] | 781 | static void e1000_enable_vlan_filter(e1000_t *e1000)
|
---|
[bf84871] | 782 | {
|
---|
[c4be33a] | 783 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 784 | rctl = rctl | RCTL_VFE;
|
---|
[c4be33a] | 785 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 786 | }
|
---|
| 787 |
|
---|
[1df224c] | 788 | /** Disable VLAN filtering
|
---|
| 789 | *
|
---|
[c4be33a] | 790 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 791 | *
|
---|
| 792 | */
|
---|
[c4be33a] | 793 | static void e1000_disable_vlan_filter(e1000_t *e1000)
|
---|
[bf84871] | 794 | {
|
---|
[c4be33a] | 795 | uint32_t rctl = E1000_REG_READ(e1000, E1000_RCTL);
|
---|
[bf84871] | 796 | rctl = rctl & ~RCTL_VFE;
|
---|
[c4be33a] | 797 | E1000_REG_WRITE(e1000, E1000_RCTL, rctl);
|
---|
[bf84871] | 798 | }
|
---|
| 799 |
|
---|
[1bc35b5] | 800 | /** Set multicast frames acceptance mode
|
---|
[bf84871] | 801 | *
|
---|
[c4be33a] | 802 | * @param nic NIC device to update
|
---|
[1df224c] | 803 | * @param mode Mode to set
|
---|
| 804 | * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
|
---|
| 805 | * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
|
---|
| 806 | *
|
---|
| 807 | * @return EOK
|
---|
[bf84871] | 808 | *
|
---|
| 809 | */
|
---|
[c4be33a] | 810 | static int e1000_on_multicast_mode_change(nic_t *nic, nic_multicast_mode_t mode,
|
---|
| 811 | const nic_address_t *addr, size_t addr_cnt)
|
---|
[bf84871] | 812 | {
|
---|
[c4be33a] | 813 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 814 | int rc = EOK;
|
---|
| 815 |
|
---|
[c4be33a] | 816 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 817 |
|
---|
[bf84871] | 818 | switch (mode) {
|
---|
| 819 | case NIC_MULTICAST_BLOCKED:
|
---|
[c4be33a] | 820 | e1000_clear_multicast_receive_addresses(e1000);
|
---|
| 821 | e1000_disable_multicast_promisc(e1000);
|
---|
| 822 | nic_report_hw_filtering(nic, -1, 1, -1);
|
---|
[bf84871] | 823 | break;
|
---|
| 824 | case NIC_MULTICAST_LIST:
|
---|
[c4be33a] | 825 | e1000_clear_multicast_receive_addresses(e1000);
|
---|
| 826 | if (addr_cnt > get_free_multicast_address_count(e1000)) {
|
---|
[1df224c] | 827 | /*
|
---|
| 828 | * Future work: fill MTA table
|
---|
| 829 | * Not strictly neccessary, it only saves some compares
|
---|
| 830 | * in the NIC library.
|
---|
| 831 | */
|
---|
[c4be33a] | 832 | e1000_enable_multicast_promisc(e1000);
|
---|
| 833 | nic_report_hw_filtering(nic, -1, 0, -1);
|
---|
[bf84871] | 834 | } else {
|
---|
[c4be33a] | 835 | e1000_disable_multicast_promisc(e1000);
|
---|
| 836 | e1000_add_multicast_receive_addresses(e1000, addr, addr_cnt);
|
---|
| 837 | nic_report_hw_filtering(nic, -1, 1, -1);
|
---|
[bf84871] | 838 | }
|
---|
| 839 | break;
|
---|
| 840 | case NIC_MULTICAST_PROMISC:
|
---|
[c4be33a] | 841 | e1000_enable_multicast_promisc(e1000);
|
---|
| 842 | e1000_clear_multicast_receive_addresses(e1000);
|
---|
| 843 | nic_report_hw_filtering(nic, -1, 1, -1);
|
---|
[bf84871] | 844 | break;
|
---|
| 845 | default:
|
---|
| 846 | rc = ENOTSUP;
|
---|
| 847 | break;
|
---|
| 848 | }
|
---|
[1df224c] | 849 |
|
---|
[c4be33a] | 850 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 851 | return rc;
|
---|
| 852 | }
|
---|
[1df224c] | 853 |
|
---|
[1bc35b5] | 854 | /** Set unicast frames acceptance mode
|
---|
[bf84871] | 855 | *
|
---|
[c4be33a] | 856 | * @param nic NIC device to update
|
---|
[1df224c] | 857 | * @param mode Mode to set
|
---|
| 858 | * @param addr Address list (used in mode = NIC_MULTICAST_LIST)
|
---|
| 859 | * @param addr_cnt Length of address list (used in mode = NIC_MULTICAST_LIST)
|
---|
| 860 | *
|
---|
| 861 | * @return EOK
|
---|
[bf84871] | 862 | *
|
---|
| 863 | */
|
---|
[c4be33a] | 864 | static int e1000_on_unicast_mode_change(nic_t *nic, nic_unicast_mode_t mode,
|
---|
| 865 | const nic_address_t *addr, size_t addr_cnt)
|
---|
[bf84871] | 866 | {
|
---|
[c4be33a] | 867 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 868 | int rc = EOK;
|
---|
| 869 |
|
---|
[c4be33a] | 870 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 871 |
|
---|
[bf84871] | 872 | switch (mode) {
|
---|
| 873 | case NIC_UNICAST_BLOCKED:
|
---|
[c4be33a] | 874 | disable_ra0_address_filter(e1000);
|
---|
| 875 | e1000_clear_unicast_receive_addresses(e1000);
|
---|
| 876 | e1000_disable_unicast_promisc(e1000);
|
---|
| 877 | nic_report_hw_filtering(nic, 1, -1, -1);
|
---|
[bf84871] | 878 | break;
|
---|
| 879 | case NIC_UNICAST_DEFAULT:
|
---|
[c4be33a] | 880 | enable_ra0_address_filter(e1000);
|
---|
| 881 | e1000_clear_unicast_receive_addresses(e1000);
|
---|
| 882 | e1000_disable_unicast_promisc(e1000);
|
---|
| 883 | nic_report_hw_filtering(nic, 1, -1, -1);
|
---|
[bf84871] | 884 | break;
|
---|
| 885 | case NIC_UNICAST_LIST:
|
---|
[c4be33a] | 886 | enable_ra0_address_filter(e1000);
|
---|
| 887 | e1000_clear_unicast_receive_addresses(e1000);
|
---|
| 888 | if (addr_cnt > get_free_unicast_address_count(e1000)) {
|
---|
| 889 | e1000_enable_unicast_promisc(e1000);
|
---|
| 890 | nic_report_hw_filtering(nic, 0, -1, -1);
|
---|
[bf84871] | 891 | } else {
|
---|
[c4be33a] | 892 | e1000_disable_unicast_promisc(e1000);
|
---|
| 893 | e1000_add_unicast_receive_addresses(e1000, addr, addr_cnt);
|
---|
| 894 | nic_report_hw_filtering(nic, 1, -1, -1);
|
---|
[bf84871] | 895 | }
|
---|
| 896 | break;
|
---|
| 897 | case NIC_UNICAST_PROMISC:
|
---|
[c4be33a] | 898 | e1000_enable_unicast_promisc(e1000);
|
---|
| 899 | enable_ra0_address_filter(e1000);
|
---|
| 900 | e1000_clear_unicast_receive_addresses(e1000);
|
---|
| 901 | nic_report_hw_filtering(nic, 1, -1, -1);
|
---|
[bf84871] | 902 | break;
|
---|
| 903 | default:
|
---|
| 904 | rc = ENOTSUP;
|
---|
| 905 | break;
|
---|
| 906 | }
|
---|
[1df224c] | 907 |
|
---|
[c4be33a] | 908 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 909 | return rc;
|
---|
| 910 | }
|
---|
| 911 |
|
---|
[1bc35b5] | 912 | /** Set broadcast frames acceptance mode
|
---|
[bf84871] | 913 | *
|
---|
[c4be33a] | 914 | * @param nic NIC device to update
|
---|
| 915 | * @param mode Mode to set
|
---|
[1df224c] | 916 | *
|
---|
| 917 | * @return EOK
|
---|
[bf84871] | 918 | *
|
---|
| 919 | */
|
---|
[c4be33a] | 920 | static int e1000_on_broadcast_mode_change(nic_t *nic, nic_broadcast_mode_t mode)
|
---|
[bf84871] | 921 | {
|
---|
[c4be33a] | 922 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 923 | int rc = EOK;
|
---|
| 924 |
|
---|
[c4be33a] | 925 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 926 |
|
---|
[bf84871] | 927 | switch (mode) {
|
---|
| 928 | case NIC_BROADCAST_BLOCKED:
|
---|
[c4be33a] | 929 | e1000_disable_broadcast_accept(e1000);
|
---|
[bf84871] | 930 | break;
|
---|
| 931 | case NIC_BROADCAST_ACCEPTED:
|
---|
[c4be33a] | 932 | e1000_enable_broadcast_accept(e1000);
|
---|
[bf84871] | 933 | break;
|
---|
| 934 | default:
|
---|
| 935 | rc = ENOTSUP;
|
---|
| 936 | break;
|
---|
| 937 | }
|
---|
[1df224c] | 938 |
|
---|
[c4be33a] | 939 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 940 | return rc;
|
---|
| 941 | }
|
---|
| 942 |
|
---|
[1df224c] | 943 | /** Check if receiving is enabled
|
---|
| 944 | *
|
---|
[c4be33a] | 945 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 946 | *
|
---|
| 947 | * @return true if receiving is enabled
|
---|
[1df224c] | 948 | *
|
---|
[bf84871] | 949 | */
|
---|
[c4be33a] | 950 | static bool e1000_is_rx_enabled(e1000_t *e1000)
|
---|
[bf84871] | 951 | {
|
---|
[c4be33a] | 952 | if (E1000_REG_READ(e1000, E1000_RCTL) & (RCTL_EN))
|
---|
[bf84871] | 953 | return true;
|
---|
[1df224c] | 954 |
|
---|
| 955 | return false;
|
---|
[bf84871] | 956 | }
|
---|
| 957 |
|
---|
[1df224c] | 958 | /** Enable receiving
|
---|
| 959 | *
|
---|
[c4be33a] | 960 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 961 | *
|
---|
| 962 | */
|
---|
[c4be33a] | 963 | static void e1000_enable_rx(e1000_t *e1000)
|
---|
[bf84871] | 964 | {
|
---|
[1df224c] | 965 | /* Set Receive Enable Bit */
|
---|
[c4be33a] | 966 | E1000_REG_WRITE(e1000, E1000_RCTL,
|
---|
| 967 | E1000_REG_READ(e1000, E1000_RCTL) | (RCTL_EN));
|
---|
[bf84871] | 968 | }
|
---|
| 969 |
|
---|
[1df224c] | 970 | /** Disable receiving
|
---|
| 971 | *
|
---|
[c4be33a] | 972 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 973 | *
|
---|
| 974 | */
|
---|
[c4be33a] | 975 | static void e1000_disable_rx(e1000_t *e1000)
|
---|
[bf84871] | 976 | {
|
---|
[1df224c] | 977 | /* Clear Receive Enable Bit */
|
---|
[c4be33a] | 978 | E1000_REG_WRITE(e1000, E1000_RCTL,
|
---|
| 979 | E1000_REG_READ(e1000, E1000_RCTL) & ~(RCTL_EN));
|
---|
[bf84871] | 980 | }
|
---|
| 981 |
|
---|
| 982 | /** Set VLAN mask
|
---|
| 983 | *
|
---|
[c4be33a] | 984 | * @param nic NIC device to update
|
---|
[1df224c] | 985 | * @param vlan_mask VLAN mask
|
---|
| 986 | *
|
---|
[bf84871] | 987 | */
|
---|
[c4be33a] | 988 | static void e1000_on_vlan_mask_change(nic_t *nic,
|
---|
| 989 | const nic_vlan_mask_t *vlan_mask)
|
---|
[bf84871] | 990 | {
|
---|
[c4be33a] | 991 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 992 |
|
---|
[c4be33a] | 993 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 994 |
|
---|
[bf84871] | 995 | if (vlan_mask) {
|
---|
[1df224c] | 996 | /*
|
---|
[1bc35b5] | 997 | * Disable receiving, so that frame matching
|
---|
[1df224c] | 998 | * partially written VLAN is not received.
|
---|
| 999 | */
|
---|
[c4be33a] | 1000 | bool rx_enabled = e1000_is_rx_enabled(e1000);
|
---|
[1df224c] | 1001 | if (rx_enabled)
|
---|
[c4be33a] | 1002 | e1000_disable_rx(e1000);
|
---|
[1df224c] | 1003 |
|
---|
| 1004 | for (unsigned int i = 0; i < NIC_VLAN_BITMAP_SIZE; i += 4) {
|
---|
| 1005 | uint32_t bitmap_part =
|
---|
| 1006 | ((uint32_t) vlan_mask->bitmap[i]) |
|
---|
| 1007 | (((uint32_t) vlan_mask->bitmap[i + 1]) << 8) |
|
---|
| 1008 | (((uint32_t) vlan_mask->bitmap[i + 2]) << 16) |
|
---|
| 1009 | (((uint32_t) vlan_mask->bitmap[i + 3]) << 24);
|
---|
[c4be33a] | 1010 | E1000_REG_WRITE(e1000, E1000_VFTA_ARRAY(i / 4), bitmap_part);
|
---|
[bf84871] | 1011 | }
|
---|
[1df224c] | 1012 |
|
---|
[c4be33a] | 1013 | e1000_enable_vlan_filter(e1000);
|
---|
[1df224c] | 1014 | if (rx_enabled)
|
---|
[c4be33a] | 1015 | e1000_enable_rx(e1000);
|
---|
[1df224c] | 1016 | } else
|
---|
[c4be33a] | 1017 | e1000_disable_vlan_filter(e1000);
|
---|
[bf84871] | 1018 |
|
---|
[c4be33a] | 1019 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 1020 | }
|
---|
| 1021 |
|
---|
| 1022 | /** Set VLAN mask
|
---|
| 1023 | *
|
---|
[1df224c] | 1024 | * @param device E1000 device
|
---|
| 1025 | * @param tag VLAN tag
|
---|
| 1026 | *
|
---|
| 1027 | * @return EOK
|
---|
| 1028 | * @return ENOTSUP
|
---|
[bf84871] | 1029 | *
|
---|
| 1030 | */
|
---|
[1df224c] | 1031 | static int e1000_vlan_set_tag(ddf_fun_t *device, uint16_t tag, bool add,
|
---|
| 1032 | bool strip)
|
---|
[bf84871] | 1033 | {
|
---|
[1df224c] | 1034 | /* VLAN CFI bit cannot be set */
|
---|
| 1035 | if (tag & VLANTAG_CFI)
|
---|
[bf84871] | 1036 | return ENOTSUP;
|
---|
[1df224c] | 1037 |
|
---|
| 1038 | /*
|
---|
| 1039 | * CTRL.VME is neccessary for both strip and add
|
---|
| 1040 | * but CTRL.VME means stripping tags on receive.
|
---|
| 1041 | */
|
---|
| 1042 | if (!strip && add)
|
---|
[bf84871] | 1043 | return ENOTSUP;
|
---|
| 1044 |
|
---|
[c4be33a] | 1045 | e1000_t *e1000 = DRIVER_DATA_DEV(device);
|
---|
[1df224c] | 1046 |
|
---|
[c4be33a] | 1047 | e1000->vlan_tag = tag;
|
---|
| 1048 | e1000->vlan_tag_add = add;
|
---|
[1df224c] | 1049 |
|
---|
[c4be33a] | 1050 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[1df224c] | 1051 |
|
---|
[c4be33a] | 1052 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[1df224c] | 1053 | if (strip)
|
---|
[bf84871] | 1054 | ctrl |= CTRL_VME;
|
---|
[1df224c] | 1055 | else
|
---|
[bf84871] | 1056 | ctrl &= ~CTRL_VME;
|
---|
[1df224c] | 1057 |
|
---|
[c4be33a] | 1058 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[1df224c] | 1059 |
|
---|
[c4be33a] | 1060 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
[bf84871] | 1061 | return EOK;
|
---|
| 1062 | }
|
---|
[1df224c] | 1063 |
|
---|
[1bc35b5] | 1064 | /** Fill receive descriptor with new empty buffer
|
---|
[bf84871] | 1065 | *
|
---|
[1bc35b5] | 1066 | * Store frame in e1000->rx_frame_phys
|
---|
[1df224c] | 1067 | *
|
---|
[c4be33a] | 1068 | * @param nic NIC data stricture
|
---|
| 1069 | * @param offset Receive descriptor offset
|
---|
[1df224c] | 1070 | *
|
---|
[bf84871] | 1071 | */
|
---|
[c4be33a] | 1072 | static void e1000_fill_new_rx_descriptor(nic_t *nic, size_t offset)
|
---|
[bf84871] | 1073 | {
|
---|
[c4be33a] | 1074 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1075 |
|
---|
[c4be33a] | 1076 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
---|
| 1077 | (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
|
---|
[1df224c] | 1078 |
|
---|
[1bc35b5] | 1079 | rx_descriptor->phys_addr = PTR_TO_U64(e1000->rx_frame_phys[offset]);
|
---|
[bf84871] | 1080 | rx_descriptor->length = 0;
|
---|
| 1081 | rx_descriptor->checksum = 0;
|
---|
| 1082 | rx_descriptor->status = 0;
|
---|
| 1083 | rx_descriptor->errors = 0;
|
---|
| 1084 | rx_descriptor->special = 0;
|
---|
| 1085 | }
|
---|
| 1086 |
|
---|
| 1087 | /** Clear receive descriptor
|
---|
| 1088 | *
|
---|
[c4be33a] | 1089 | * @param e1000 E1000 data
|
---|
| 1090 | * @param offset Receive descriptor offset
|
---|
[1df224c] | 1091 | *
|
---|
[bf84871] | 1092 | */
|
---|
[c4be33a] | 1093 | static void e1000_clear_rx_descriptor(e1000_t *e1000, unsigned int offset)
|
---|
[1df224c] | 1094 | {
|
---|
| 1095 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
---|
[c4be33a] | 1096 | (e1000->rx_ring_virt + offset * sizeof(e1000_rx_descriptor_t));
|
---|
[1df224c] | 1097 |
|
---|
[bf84871] | 1098 | rx_descriptor->length = 0;
|
---|
| 1099 | rx_descriptor->checksum = 0;
|
---|
| 1100 | rx_descriptor->status = 0;
|
---|
| 1101 | rx_descriptor->errors = 0;
|
---|
| 1102 | rx_descriptor->special = 0;
|
---|
| 1103 | }
|
---|
| 1104 |
|
---|
| 1105 | /** Clear receive descriptor
|
---|
| 1106 | *
|
---|
[c4be33a] | 1107 | * @param nic NIC data
|
---|
| 1108 | * @param offset Receive descriptor offset
|
---|
[1df224c] | 1109 | *
|
---|
[bf84871] | 1110 | */
|
---|
[c4be33a] | 1111 | static void e1000_clear_tx_descriptor(nic_t *nic, unsigned int offset)
|
---|
[bf84871] | 1112 | {
|
---|
[c4be33a] | 1113 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1114 |
|
---|
[c4be33a] | 1115 | e1000_tx_descriptor_t *tx_descriptor = (e1000_tx_descriptor_t *)
|
---|
| 1116 | (e1000->tx_ring_virt + offset * sizeof(e1000_tx_descriptor_t));
|
---|
[bf84871] | 1117 |
|
---|
| 1118 | tx_descriptor->phys_addr = 0;
|
---|
| 1119 | tx_descriptor->length = 0;
|
---|
| 1120 | tx_descriptor->checksum_offset = 0;
|
---|
| 1121 | tx_descriptor->command = 0;
|
---|
| 1122 | tx_descriptor->status = 0;
|
---|
| 1123 | tx_descriptor->checksum_start_field = 0;
|
---|
| 1124 | tx_descriptor->special = 0;
|
---|
| 1125 | }
|
---|
| 1126 |
|
---|
| 1127 | /** Increment tail pointer for receive or transmit ring
|
---|
| 1128 | *
|
---|
[1df224c] | 1129 | * @param tail Old Tail
|
---|
| 1130 | * @param descriptors_count Ring length
|
---|
| 1131 | *
|
---|
| 1132 | * @return New tail
|
---|
[bf84871] | 1133 | *
|
---|
| 1134 | */
|
---|
| 1135 | static uint32_t e1000_inc_tail(uint32_t tail, uint32_t descriptors_count)
|
---|
| 1136 | {
|
---|
[1df224c] | 1137 | if (tail + 1 == descriptors_count)
|
---|
[bf84871] | 1138 | return 0;
|
---|
[1df224c] | 1139 | else
|
---|
[bf84871] | 1140 | return tail + 1;
|
---|
| 1141 | }
|
---|
| 1142 |
|
---|
[1bc35b5] | 1143 | /** Receive frames
|
---|
[1df224c] | 1144 | *
|
---|
[c4be33a] | 1145 | * @param nic NIC data
|
---|
[1df224c] | 1146 | *
|
---|
[bf84871] | 1147 | */
|
---|
[1bc35b5] | 1148 | static void e1000_receive_frames(nic_t *nic)
|
---|
[bf84871] | 1149 | {
|
---|
[c4be33a] | 1150 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1151 |
|
---|
[c4be33a] | 1152 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[bf84871] | 1153 |
|
---|
[c4be33a] | 1154 | uint32_t *tail_addr = E1000_REG_ADDR(e1000, E1000_RDT);
|
---|
[1bc35b5] | 1155 | uint32_t next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
---|
[bf84871] | 1156 |
|
---|
[1df224c] | 1157 | e1000_rx_descriptor_t *rx_descriptor = (e1000_rx_descriptor_t *)
|
---|
[c4be33a] | 1158 | (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
|
---|
[1df224c] | 1159 |
|
---|
| 1160 | while (rx_descriptor->status & 0x01) {
|
---|
[1bc35b5] | 1161 | uint32_t frame_size = rx_descriptor->length - E1000_CRC_SIZE;
|
---|
[1df224c] | 1162 |
|
---|
[1bc35b5] | 1163 | nic_frame_t *frame = nic_alloc_frame(nic, frame_size);
|
---|
| 1164 | if (frame != NULL) {
|
---|
| 1165 | memcpy(frame->data, e1000->rx_frame_virt[next_tail], frame_size);
|
---|
| 1166 | nic_received_frame(nic, frame);
|
---|
| 1167 | } else {
|
---|
| 1168 | ddf_msg(LVL_ERROR, "Memory allocation failed. Frame dropped.");
|
---|
| 1169 | }
|
---|
[1df224c] | 1170 |
|
---|
[c4be33a] | 1171 | e1000_fill_new_rx_descriptor(nic, next_tail);
|
---|
[1df224c] | 1172 |
|
---|
[1bc35b5] | 1173 | *tail_addr = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
---|
| 1174 | next_tail = e1000_inc_tail(*tail_addr, E1000_RX_FRAME_COUNT);
|
---|
[1df224c] | 1175 |
|
---|
| 1176 | rx_descriptor = (e1000_rx_descriptor_t *)
|
---|
[c4be33a] | 1177 | (e1000->rx_ring_virt + next_tail * sizeof(e1000_rx_descriptor_t));
|
---|
[bf84871] | 1178 | }
|
---|
| 1179 |
|
---|
[c4be33a] | 1180 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 1181 | }
|
---|
| 1182 |
|
---|
[1df224c] | 1183 | /** Enable E1000 interupts
|
---|
| 1184 | *
|
---|
[c4be33a] | 1185 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 1186 | *
|
---|
| 1187 | */
|
---|
[c4be33a] | 1188 | static void e1000_enable_interrupts(e1000_t *e1000)
|
---|
[bf84871] | 1189 | {
|
---|
[c4be33a] | 1190 | E1000_REG_WRITE(e1000, E1000_IMS, ICR_RXT0);
|
---|
[bf84871] | 1191 | }
|
---|
| 1192 |
|
---|
[1df224c] | 1193 | /** Disable E1000 interupts
|
---|
| 1194 | *
|
---|
[c4be33a] | 1195 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 1196 | *
|
---|
| 1197 | */
|
---|
[c4be33a] | 1198 | static void e1000_disable_interrupts(e1000_t *e1000)
|
---|
[bf84871] | 1199 | {
|
---|
[c4be33a] | 1200 | E1000_REG_WRITE(e1000, E1000_IMS, 0);
|
---|
[bf84871] | 1201 | }
|
---|
| 1202 |
|
---|
| 1203 | /** Interrupt handler implementation
|
---|
| 1204 | *
|
---|
[1df224c] | 1205 | * This function is called from e1000_interrupt_handler()
|
---|
| 1206 | * and e1000_poll()
|
---|
| 1207 | *
|
---|
[c4be33a] | 1208 | * @param nic NIC data
|
---|
| 1209 | * @param icr ICR register value
|
---|
[1df224c] | 1210 | *
|
---|
[bf84871] | 1211 | */
|
---|
[c4be33a] | 1212 | static void e1000_interrupt_handler_impl(nic_t *nic, uint32_t icr)
|
---|
[1df224c] | 1213 | {
|
---|
| 1214 | if (icr & ICR_RXT0)
|
---|
[1bc35b5] | 1215 | e1000_receive_frames(nic);
|
---|
[bf84871] | 1216 | }
|
---|
| 1217 |
|
---|
| 1218 | /** Handle device interrupt
|
---|
| 1219 | *
|
---|
[1df224c] | 1220 | * @param dev E1000 device
|
---|
| 1221 | * @param iid IPC call id
|
---|
| 1222 | * @param icall IPC call structure
|
---|
| 1223 | *
|
---|
[bf84871] | 1224 | */
|
---|
| 1225 | static void e1000_interrupt_handler(ddf_dev_t *dev, ipc_callid_t iid,
|
---|
| 1226 | ipc_call_t *icall)
|
---|
| 1227 | {
|
---|
| 1228 | uint32_t icr = (uint32_t) IPC_GET_ARG2(*icall);
|
---|
[c4be33a] | 1229 | nic_t *nic = NIC_DATA_DEV(dev);
|
---|
| 1230 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[bf84871] | 1231 |
|
---|
[c4be33a] | 1232 | e1000_interrupt_handler_impl(nic, icr);
|
---|
| 1233 | e1000_enable_interrupts(e1000);
|
---|
[1df224c] | 1234 | }
|
---|
[bf84871] | 1235 |
|
---|
| 1236 | /** Register interrupt handler for the card in the system
|
---|
| 1237 | *
|
---|
[1df224c] | 1238 | * Note: The global irq_reg_mutex is locked because of work with global
|
---|
| 1239 | * structure.
|
---|
| 1240 | *
|
---|
[c4be33a] | 1241 | * @param nic Driver data
|
---|
[1df224c] | 1242 | *
|
---|
| 1243 | * @return EOK if the handler was registered
|
---|
| 1244 | * @return Negative error code otherwise
|
---|
[bf84871] | 1245 | *
|
---|
| 1246 | */
|
---|
[c4be33a] | 1247 | inline static int e1000_register_int_handler(nic_t *nic)
|
---|
[bf84871] | 1248 | {
|
---|
[c4be33a] | 1249 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1250 |
|
---|
[bf84871] | 1251 | /* Lock the mutex in whole driver while working with global structure */
|
---|
| 1252 | fibril_mutex_lock(&irq_reg_mutex);
|
---|
[1df224c] | 1253 |
|
---|
[c4be33a] | 1254 | e1000_irq_code.cmds[0].addr = e1000->reg_base_virt + E1000_ICR;
|
---|
| 1255 | e1000_irq_code.cmds[2].addr = e1000->reg_base_virt + E1000_IMC;
|
---|
[1df224c] | 1256 |
|
---|
[c4be33a] | 1257 | int rc = register_interrupt_handler(nic_get_ddf_dev(nic),
|
---|
| 1258 | e1000->irq, e1000_interrupt_handler, &e1000_irq_code);
|
---|
[1df224c] | 1259 |
|
---|
[bf84871] | 1260 | fibril_mutex_unlock(&irq_reg_mutex);
|
---|
| 1261 | return rc;
|
---|
| 1262 | }
|
---|
| 1263 |
|
---|
[1bc35b5] | 1264 | /** Force receiving all frames in the receive buffer
|
---|
[bf84871] | 1265 | *
|
---|
[c4be33a] | 1266 | * @param nic NIC data
|
---|
[1df224c] | 1267 | *
|
---|
[bf84871] | 1268 | */
|
---|
[c4be33a] | 1269 | static void e1000_poll(nic_t *nic)
|
---|
[bf84871] | 1270 | {
|
---|
[c4be33a] | 1271 | assert(nic);
|
---|
[1df224c] | 1272 |
|
---|
[c4be33a] | 1273 | e1000_t *e1000 = nic_get_specific(nic);
|
---|
| 1274 | assert(e1000);
|
---|
[1df224c] | 1275 |
|
---|
[c4be33a] | 1276 | uint32_t icr = E1000_REG_READ(e1000, E1000_ICR);
|
---|
| 1277 | e1000_interrupt_handler_impl(nic, icr);
|
---|
[bf84871] | 1278 | }
|
---|
| 1279 |
|
---|
| 1280 | /** Calculates ITR register interrupt from timeval structure
|
---|
| 1281 | *
|
---|
[1df224c] | 1282 | * @param period Period
|
---|
| 1283 | *
|
---|
[bf84871] | 1284 | */
|
---|
[1df224c] | 1285 | static uint16_t e1000_calculate_itr_interval(const struct timeval *period)
|
---|
| 1286 | {
|
---|
| 1287 | // TODO: use also tv_sec
|
---|
[bf84871] | 1288 | return e1000_calculate_itr_interval_from_usecs(period->tv_usec);
|
---|
| 1289 | }
|
---|
| 1290 |
|
---|
| 1291 | /** Set polling mode
|
---|
| 1292 | *
|
---|
[1df224c] | 1293 | * @param device Device to set
|
---|
| 1294 | * @param mode Mode to set
|
---|
| 1295 | * @param period Period for NIC_POLL_PERIODIC
|
---|
| 1296 | *
|
---|
| 1297 | * @return EOK if succeed
|
---|
| 1298 | * @return ENOTSUP if the mode is not supported
|
---|
[bf84871] | 1299 | *
|
---|
| 1300 | */
|
---|
[c4be33a] | 1301 | static int e1000_poll_mode_change(nic_t *nic, nic_poll_mode_t mode,
|
---|
[bf84871] | 1302 | const struct timeval *period)
|
---|
| 1303 | {
|
---|
[c4be33a] | 1304 | assert(nic);
|
---|
[1df224c] | 1305 |
|
---|
[c4be33a] | 1306 | e1000_t *e1000 = nic_get_specific(nic);
|
---|
| 1307 | assert(e1000);
|
---|
[bf84871] | 1308 |
|
---|
[1df224c] | 1309 | switch (mode) {
|
---|
[bf84871] | 1310 | case NIC_POLL_IMMEDIATE:
|
---|
[c4be33a] | 1311 | E1000_REG_WRITE(e1000, E1000_ITR, 0);
|
---|
| 1312 | e1000_enable_interrupts(e1000);
|
---|
[bf84871] | 1313 | break;
|
---|
| 1314 | case NIC_POLL_ON_DEMAND:
|
---|
[c4be33a] | 1315 | e1000_disable_interrupts(e1000);
|
---|
[bf84871] | 1316 | break;
|
---|
| 1317 | case NIC_POLL_PERIODIC:
|
---|
| 1318 | assert(period);
|
---|
| 1319 | uint16_t itr_interval = e1000_calculate_itr_interval(period);
|
---|
[c4be33a] | 1320 | E1000_REG_WRITE(e1000, E1000_ITR, (uint32_t) itr_interval);
|
---|
| 1321 | e1000_enable_interrupts(e1000);
|
---|
[bf84871] | 1322 | break;
|
---|
| 1323 | default:
|
---|
| 1324 | return ENOTSUP;
|
---|
| 1325 | }
|
---|
[1df224c] | 1326 |
|
---|
[bf84871] | 1327 | return EOK;
|
---|
| 1328 | }
|
---|
| 1329 |
|
---|
[1df224c] | 1330 | /** Initialize receive registers
|
---|
| 1331 | *
|
---|
[c4be33a] | 1332 | * @param e1000 E1000 data structure
|
---|
[bf84871] | 1333 | *
|
---|
| 1334 | */
|
---|
[c4be33a] | 1335 | static void e1000_initialize_rx_registers(e1000_t *e1000)
|
---|
[bf84871] | 1336 | {
|
---|
[1bc35b5] | 1337 | E1000_REG_WRITE(e1000, E1000_RDLEN, E1000_RX_FRAME_COUNT * 16);
|
---|
[c4be33a] | 1338 | E1000_REG_WRITE(e1000, E1000_RDH, 0);
|
---|
[1df224c] | 1339 |
|
---|
| 1340 | /* It is not posible to let HW use all descriptors */
|
---|
[1bc35b5] | 1341 | E1000_REG_WRITE(e1000, E1000_RDT, E1000_RX_FRAME_COUNT - 1);
|
---|
[bf84871] | 1342 |
|
---|
[1df224c] | 1343 | /* Set Broadcast Enable Bit */
|
---|
[c4be33a] | 1344 | E1000_REG_WRITE(e1000, E1000_RCTL, RCTL_BAM);
|
---|
[bf84871] | 1345 | }
|
---|
| 1346 |
|
---|
[1df224c] | 1347 | /** Initialize receive structure
|
---|
| 1348 | *
|
---|
[c4be33a] | 1349 | * @param nic NIC data
|
---|
[1df224c] | 1350 | *
|
---|
| 1351 | * @return EOK if succeed
|
---|
| 1352 | * @return Negative error code otherwise
|
---|
[bf84871] | 1353 | *
|
---|
| 1354 | */
|
---|
[c4be33a] | 1355 | static int e1000_initialize_rx_structure(nic_t *nic)
|
---|
[bf84871] | 1356 | {
|
---|
[c4be33a] | 1357 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
| 1358 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 1359 |
|
---|
[c4be33a] | 1360 | int rc = dmamem_map_anonymous(
|
---|
[1bc35b5] | 1361 | E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t),
|
---|
[c4be33a] | 1362 | AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,
|
---|
| 1363 | &e1000->rx_ring_virt);
|
---|
[1df224c] | 1364 | if (rc != EOK)
|
---|
[bf84871] | 1365 | return rc;
|
---|
[1df224c] | 1366 |
|
---|
[c4be33a] | 1367 | E1000_REG_WRITE(e1000, E1000_RDBAH,
|
---|
| 1368 | (uint32_t) (PTR_TO_U64(e1000->rx_ring_phys) >> 32));
|
---|
| 1369 | E1000_REG_WRITE(e1000, E1000_RDBAL,
|
---|
| 1370 | (uint32_t) PTR_TO_U64(e1000->rx_ring_phys));
|
---|
[1df224c] | 1371 |
|
---|
[1bc35b5] | 1372 | e1000->rx_frame_phys =
|
---|
| 1373 | calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
|
---|
| 1374 | e1000->rx_frame_virt =
|
---|
| 1375 | calloc(E1000_RX_FRAME_COUNT, sizeof(void *));
|
---|
| 1376 | if (e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {
|
---|
| 1377 | rc = ENOMEM;
|
---|
| 1378 | goto error;
|
---|
| 1379 | }
|
---|
| 1380 |
|
---|
| 1381 | size_t i;
|
---|
| 1382 | void *frame_virt;
|
---|
| 1383 | void *frame_phys;
|
---|
| 1384 |
|
---|
| 1385 | for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
|
---|
| 1386 | rc = dmamem_map_anonymous(
|
---|
| 1387 | E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
|
---|
| 1388 | 0, &frame_phys, &frame_virt);
|
---|
| 1389 | if (rc != EOK)
|
---|
| 1390 | goto error;
|
---|
| 1391 |
|
---|
| 1392 | e1000->rx_frame_virt[i] = frame_virt;
|
---|
| 1393 | e1000->rx_frame_phys[i] = frame_phys;
|
---|
| 1394 | }
|
---|
[1df224c] | 1395 |
|
---|
| 1396 | /* Write descriptor */
|
---|
[1bc35b5] | 1397 | for (i = 0; i < E1000_RX_FRAME_COUNT; i++)
|
---|
| 1398 | e1000_fill_new_rx_descriptor(nic, i);
|
---|
[bf84871] | 1399 |
|
---|
[c4be33a] | 1400 | e1000_initialize_rx_registers(e1000);
|
---|
[bf84871] | 1401 |
|
---|
[c4be33a] | 1402 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 1403 | return EOK;
|
---|
[5cc9eba] | 1404 |
|
---|
[1bc35b5] | 1405 | error:
|
---|
| 1406 | for (i = 0; i < E1000_RX_FRAME_COUNT; i++) {
|
---|
| 1407 | if (e1000->rx_frame_virt[i] != NULL) {
|
---|
| 1408 | dmamem_unmap_anonymous(e1000->rx_frame_virt[i]);
|
---|
| 1409 | e1000->rx_frame_virt[i] = NULL;
|
---|
| 1410 | e1000->rx_frame_phys[i] = NULL;
|
---|
| 1411 | }
|
---|
| 1412 | }
|
---|
[5cc9eba] | 1413 |
|
---|
[1bc35b5] | 1414 | if (e1000->rx_frame_phys != NULL) {
|
---|
| 1415 | free(e1000->rx_frame_phys);
|
---|
| 1416 | e1000->rx_frame_phys = NULL;
|
---|
| 1417 | }
|
---|
[5cc9eba] | 1418 |
|
---|
[1bc35b5] | 1419 | if (e1000->rx_frame_virt != NULL) {
|
---|
| 1420 | free(e1000->rx_frame_virt);
|
---|
| 1421 | e1000->rx_frame_phys = NULL;
|
---|
| 1422 | }
|
---|
[5cc9eba] | 1423 |
|
---|
[1bc35b5] | 1424 | return rc;
|
---|
[bf84871] | 1425 | }
|
---|
| 1426 |
|
---|
[1df224c] | 1427 | /** Uninitialize receive structure
|
---|
| 1428 | *
|
---|
[c4be33a] | 1429 | * @param nic NIC data
|
---|
[bf84871] | 1430 | *
|
---|
| 1431 | */
|
---|
[c4be33a] | 1432 | static void e1000_uninitialize_rx_structure(nic_t *nic)
|
---|
[bf84871] | 1433 | {
|
---|
[c4be33a] | 1434 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1435 |
|
---|
| 1436 | /* Write descriptor */
|
---|
[1bc35b5] | 1437 | for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) {
|
---|
| 1438 | dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]);
|
---|
| 1439 | e1000->rx_frame_virt[offset] = NULL;
|
---|
| 1440 | e1000->rx_frame_phys[offset] = NULL;
|
---|
[bf84871] | 1441 | }
|
---|
| 1442 |
|
---|
[1bc35b5] | 1443 | free(e1000->rx_frame_virt);
|
---|
| 1444 | free(e1000->rx_frame_phys);
|
---|
| 1445 | e1000->rx_frame_virt = NULL;
|
---|
| 1446 | e1000->rx_frame_phys = NULL;
|
---|
[c4be33a] | 1447 | dmamem_unmap_anonymous(e1000->rx_ring_virt);
|
---|
[bf84871] | 1448 | }
|
---|
| 1449 |
|
---|
| 1450 | /** Clear receive descriptor ring
|
---|
| 1451 | *
|
---|
[c4be33a] | 1452 | * @param e1000 E1000 data
|
---|
[1df224c] | 1453 | *
|
---|
[bf84871] | 1454 | */
|
---|
[c4be33a] | 1455 | static void e1000_clear_rx_ring(e1000_t *e1000)
|
---|
[bf84871] | 1456 | {
|
---|
[1df224c] | 1457 | /* Write descriptor */
|
---|
| 1458 | for (unsigned int offset = 0;
|
---|
[1bc35b5] | 1459 | offset < E1000_RX_FRAME_COUNT;
|
---|
[1df224c] | 1460 | offset++)
|
---|
[c4be33a] | 1461 | e1000_clear_rx_descriptor(e1000, offset);
|
---|
[bf84871] | 1462 | }
|
---|
| 1463 |
|
---|
| 1464 | /** Initialize filters
|
---|
| 1465 | *
|
---|
[c4be33a] | 1466 | * @param e1000 E1000 data
|
---|
[1df224c] | 1467 | *
|
---|
[bf84871] | 1468 | */
|
---|
[c4be33a] | 1469 | static void e1000_initialize_filters(e1000_t *e1000)
|
---|
[bf84871] | 1470 | {
|
---|
[1df224c] | 1471 | /* Initialize address filter */
|
---|
[c4be33a] | 1472 | e1000->unicast_ra_count = 0;
|
---|
| 1473 | e1000->multicast_ra_count = 0;
|
---|
| 1474 | e1000_clear_unicast_receive_addresses(e1000);
|
---|
[bf84871] | 1475 | }
|
---|
| 1476 |
|
---|
| 1477 | /** Initialize VLAN
|
---|
| 1478 | *
|
---|
[c4be33a] | 1479 | * @param e1000 E1000 data
|
---|
[1df224c] | 1480 | *
|
---|
[bf84871] | 1481 | */
|
---|
[c4be33a] | 1482 | static void e1000_initialize_vlan(e1000_t *e1000)
|
---|
[bf84871] | 1483 | {
|
---|
[c4be33a] | 1484 | e1000->vlan_tag_add = false;
|
---|
[bf84871] | 1485 | }
|
---|
| 1486 |
|
---|
[1df224c] | 1487 | /** Fill MAC address from EEPROM to RA[0] register
|
---|
| 1488 | *
|
---|
[c4be33a] | 1489 | * @param e1000 E1000 data
|
---|
[bf84871] | 1490 | *
|
---|
| 1491 | */
|
---|
[c4be33a] | 1492 | static void e1000_fill_mac_from_eeprom(e1000_t *e1000)
|
---|
[bf84871] | 1493 | {
|
---|
[1df224c] | 1494 | /* MAC address from eeprom to RA[0] */
|
---|
[bf84871] | 1495 | nic_address_t address;
|
---|
[c4be33a] | 1496 | e1000_eeprom_get_address(e1000, &address);
|
---|
| 1497 | e1000_write_receive_address(e1000, 0, &address, true);
|
---|
[bf84871] | 1498 | }
|
---|
| 1499 |
|
---|
[1df224c] | 1500 | /** Initialize other registers
|
---|
| 1501 | *
|
---|
| 1502 | * @param dev E1000 data.
|
---|
| 1503 | *
|
---|
| 1504 | * @return EOK if succeed
|
---|
| 1505 | * @return Negative error code otherwise
|
---|
[bf84871] | 1506 | *
|
---|
| 1507 | */
|
---|
[c4be33a] | 1508 | static void e1000_initialize_registers(e1000_t *e1000)
|
---|
[bf84871] | 1509 | {
|
---|
[c4be33a] | 1510 | E1000_REG_WRITE(e1000, E1000_ITR,
|
---|
[1df224c] | 1511 | e1000_calculate_itr_interval_from_usecs(
|
---|
[9916841] | 1512 | E1000_DEFAULT_INTERRUPT_INTERVAL_USEC));
|
---|
[c4be33a] | 1513 | E1000_REG_WRITE(e1000, E1000_FCAH, 0);
|
---|
| 1514 | E1000_REG_WRITE(e1000, E1000_FCAL, 0);
|
---|
| 1515 | E1000_REG_WRITE(e1000, E1000_FCT, 0);
|
---|
| 1516 | E1000_REG_WRITE(e1000, E1000_FCTTV, 0);
|
---|
| 1517 | E1000_REG_WRITE(e1000, E1000_VET, VET_VALUE);
|
---|
| 1518 | E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_ASDE);
|
---|
[bf84871] | 1519 | }
|
---|
| 1520 |
|
---|
[1df224c] | 1521 | /** Initialize transmit registers
|
---|
| 1522 | *
|
---|
[c4be33a] | 1523 | * @param e1000 E1000 data.
|
---|
[bf84871] | 1524 | *
|
---|
| 1525 | */
|
---|
[c4be33a] | 1526 | static void e1000_initialize_tx_registers(e1000_t *e1000)
|
---|
[bf84871] | 1527 | {
|
---|
[1bc35b5] | 1528 | E1000_REG_WRITE(e1000, E1000_TDLEN, E1000_TX_FRAME_COUNT * 16);
|
---|
[c4be33a] | 1529 | E1000_REG_WRITE(e1000, E1000_TDH, 0);
|
---|
| 1530 | E1000_REG_WRITE(e1000, E1000_TDT, 0);
|
---|
[bf84871] | 1531 |
|
---|
[c4be33a] | 1532 | E1000_REG_WRITE(e1000, E1000_TIPG,
|
---|
[1df224c] | 1533 | 10 << TIPG_IPGT_SHIFT |
|
---|
| 1534 | 8 << TIPG_IPGR1_SHIFT |
|
---|
| 1535 | 6 << TIPG_IPGR2_SHIFT);
|
---|
[bf84871] | 1536 |
|
---|
[c4be33a] | 1537 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
---|
[1df224c] | 1538 | 0x0F << TCTL_CT_SHIFT /* Collision Threshold */ |
|
---|
| 1539 | 0x40 << TCTL_COLD_SHIFT /* Collision Distance */ |
|
---|
| 1540 | TCTL_PSP /* Pad Short Packets */);
|
---|
[bf84871] | 1541 | }
|
---|
| 1542 |
|
---|
| 1543 | /** Initialize transmit structure
|
---|
| 1544 | *
|
---|
[c4be33a] | 1545 | * @param e1000 E1000 data.
|
---|
[1df224c] | 1546 | *
|
---|
[bf84871] | 1547 | */
|
---|
[c4be33a] | 1548 | static int e1000_initialize_tx_structure(e1000_t *e1000)
|
---|
[bf84871] | 1549 | {
|
---|
[6d8455d] | 1550 | size_t i;
|
---|
| 1551 |
|
---|
[c4be33a] | 1552 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
[1df224c] | 1553 |
|
---|
[6d8455d] | 1554 | e1000->tx_ring_phys = NULL;
|
---|
| 1555 | e1000->tx_ring_virt = NULL;
|
---|
| 1556 | e1000->tx_frame_phys = NULL;
|
---|
| 1557 | e1000->tx_frame_virt = NULL;
|
---|
| 1558 |
|
---|
[c4be33a] | 1559 | int rc = dmamem_map_anonymous(
|
---|
[1bc35b5] | 1560 | E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t),
|
---|
[c4be33a] | 1561 | AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,
|
---|
| 1562 | &e1000->tx_ring_virt);
|
---|
[1df224c] | 1563 | if (rc != EOK)
|
---|
[6d8455d] | 1564 | goto error;
|
---|
[bf84871] | 1565 |
|
---|
[c4be33a] | 1566 | bzero(e1000->tx_ring_virt,
|
---|
[1bc35b5] | 1567 | E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t));
|
---|
[1df224c] | 1568 |
|
---|
[1bc35b5] | 1569 | e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
|
---|
| 1570 | e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *));
|
---|
[6d8455d] | 1571 |
|
---|
| 1572 | if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) {
|
---|
| 1573 | rc = ENOMEM;
|
---|
| 1574 | goto error;
|
---|
| 1575 | }
|
---|
| 1576 |
|
---|
[1bc35b5] | 1577 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
---|
[6d8455d] | 1578 | rc = dmamem_map_anonymous(
|
---|
| 1579 | E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,
|
---|
| 1580 | 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]);
|
---|
| 1581 | if (rc != EOK)
|
---|
| 1582 | goto error;
|
---|
| 1583 | }
|
---|
| 1584 |
|
---|
[c4be33a] | 1585 | E1000_REG_WRITE(e1000, E1000_TDBAH,
|
---|
| 1586 | (uint32_t) (PTR_TO_U64(e1000->tx_ring_phys) >> 32));
|
---|
| 1587 | E1000_REG_WRITE(e1000, E1000_TDBAL,
|
---|
| 1588 | (uint32_t) PTR_TO_U64(e1000->tx_ring_phys));
|
---|
[1df224c] | 1589 |
|
---|
[c4be33a] | 1590 | e1000_initialize_tx_registers(e1000);
|
---|
[bf84871] | 1591 |
|
---|
[c4be33a] | 1592 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
[bf84871] | 1593 | return EOK;
|
---|
[6d8455d] | 1594 |
|
---|
| 1595 | error:
|
---|
| 1596 | if (e1000->tx_ring_virt != NULL) {
|
---|
| 1597 | dmamem_unmap_anonymous(e1000->tx_ring_virt);
|
---|
| 1598 | e1000->tx_ring_virt = NULL;
|
---|
| 1599 | }
|
---|
| 1600 |
|
---|
| 1601 | if (e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {
|
---|
[1bc35b5] | 1602 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
---|
[6d8455d] | 1603 | if (e1000->tx_frame_virt[i] != NULL) {
|
---|
| 1604 | dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
|
---|
| 1605 | e1000->tx_frame_virt[i] = NULL;
|
---|
| 1606 | e1000->tx_frame_phys[i] = NULL;
|
---|
| 1607 | }
|
---|
| 1608 | }
|
---|
| 1609 | }
|
---|
| 1610 |
|
---|
| 1611 | if (e1000->tx_frame_phys != NULL) {
|
---|
| 1612 | free(e1000->tx_frame_phys);
|
---|
| 1613 | e1000->tx_frame_phys = NULL;
|
---|
| 1614 | }
|
---|
| 1615 |
|
---|
| 1616 | if (e1000->tx_frame_virt != NULL) {
|
---|
| 1617 | free(e1000->tx_frame_virt);
|
---|
| 1618 | e1000->tx_frame_phys = NULL;
|
---|
| 1619 | }
|
---|
| 1620 |
|
---|
| 1621 | return rc;
|
---|
[bf84871] | 1622 | }
|
---|
| 1623 |
|
---|
[1df224c] | 1624 | /** Uninitialize transmit structure
|
---|
| 1625 | *
|
---|
[c4be33a] | 1626 | * @param nic NIC data
|
---|
[bf84871] | 1627 | *
|
---|
| 1628 | */
|
---|
[c4be33a] | 1629 | static void e1000_uninitialize_tx_structure(e1000_t *e1000)
|
---|
[bf84871] | 1630 | {
|
---|
[6d8455d] | 1631 | size_t i;
|
---|
| 1632 |
|
---|
[1bc35b5] | 1633 | for (i = 0; i < E1000_TX_FRAME_COUNT; i++) {
|
---|
[6d8455d] | 1634 | dmamem_unmap_anonymous(e1000->tx_frame_virt[i]);
|
---|
| 1635 | e1000->tx_frame_virt[i] = NULL;
|
---|
| 1636 | e1000->tx_frame_phys[i] = NULL;
|
---|
| 1637 | }
|
---|
| 1638 |
|
---|
| 1639 | if (e1000->tx_frame_phys != NULL) {
|
---|
| 1640 | free(e1000->tx_frame_phys);
|
---|
| 1641 | e1000->tx_frame_phys = NULL;
|
---|
| 1642 | }
|
---|
| 1643 |
|
---|
| 1644 | if (e1000->tx_frame_virt != NULL) {
|
---|
| 1645 | free(e1000->tx_frame_virt);
|
---|
| 1646 | e1000->tx_frame_phys = NULL;
|
---|
| 1647 | }
|
---|
[5cc9eba] | 1648 |
|
---|
[c4be33a] | 1649 | dmamem_unmap_anonymous(e1000->tx_ring_virt);
|
---|
[bf84871] | 1650 | }
|
---|
| 1651 |
|
---|
| 1652 | /** Clear transmit descriptor ring
|
---|
| 1653 | *
|
---|
[c4be33a] | 1654 | * @param nic NIC data
|
---|
[1df224c] | 1655 | *
|
---|
[bf84871] | 1656 | */
|
---|
[c4be33a] | 1657 | static void e1000_clear_tx_ring(nic_t *nic)
|
---|
[bf84871] | 1658 | {
|
---|
[1df224c] | 1659 | /* Write descriptor */
|
---|
| 1660 | for (unsigned int offset = 0;
|
---|
[1bc35b5] | 1661 | offset < E1000_TX_FRAME_COUNT;
|
---|
[1df224c] | 1662 | offset++)
|
---|
[c4be33a] | 1663 | e1000_clear_tx_descriptor(nic, offset);
|
---|
[bf84871] | 1664 | }
|
---|
| 1665 |
|
---|
| 1666 | /** Enable transmit
|
---|
| 1667 | *
|
---|
[c4be33a] | 1668 | * @param e1000 E1000 data
|
---|
[1df224c] | 1669 | *
|
---|
[bf84871] | 1670 | */
|
---|
[c4be33a] | 1671 | static void e1000_enable_tx(e1000_t *e1000)
|
---|
[bf84871] | 1672 | {
|
---|
[1df224c] | 1673 | /* Set Transmit Enable Bit */
|
---|
[c4be33a] | 1674 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
---|
| 1675 | E1000_REG_READ(e1000, E1000_TCTL) | (TCTL_EN));
|
---|
[bf84871] | 1676 | }
|
---|
| 1677 |
|
---|
| 1678 | /** Disable transmit
|
---|
| 1679 | *
|
---|
[c4be33a] | 1680 | * @param e1000 E1000 data
|
---|
[1df224c] | 1681 | *
|
---|
[bf84871] | 1682 | */
|
---|
[c4be33a] | 1683 | static void e1000_disable_tx(e1000_t *e1000)
|
---|
[bf84871] | 1684 | {
|
---|
[1df224c] | 1685 | /* Clear Transmit Enable Bit */
|
---|
[c4be33a] | 1686 | E1000_REG_WRITE(e1000, E1000_TCTL,
|
---|
| 1687 | E1000_REG_READ(e1000, E1000_TCTL) & ~(TCTL_EN));
|
---|
[bf84871] | 1688 | }
|
---|
| 1689 |
|
---|
| 1690 | /** Reset E1000 device
|
---|
| 1691 | *
|
---|
[c4be33a] | 1692 | * @param e1000 The E1000 data
|
---|
[1df224c] | 1693 | *
|
---|
[bf84871] | 1694 | */
|
---|
[c4be33a] | 1695 | static int e1000_reset(nic_t *nic)
|
---|
[bf84871] | 1696 | {
|
---|
[c4be33a] | 1697 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[bf84871] | 1698 |
|
---|
[c4be33a] | 1699 | E1000_REG_WRITE(e1000, E1000_CTRL, CTRL_RST);
|
---|
[1df224c] | 1700 |
|
---|
| 1701 | /* Wait for the reset */
|
---|
| 1702 | usleep(20);
|
---|
| 1703 |
|
---|
| 1704 | /* check if RST_BIT cleared */
|
---|
[c4be33a] | 1705 | if (E1000_REG_READ(e1000, E1000_CTRL) & (CTRL_RST))
|
---|
[1df224c] | 1706 | return EINVAL;
|
---|
| 1707 |
|
---|
[c4be33a] | 1708 | e1000_initialize_registers(e1000);
|
---|
| 1709 | e1000_initialize_rx_registers(e1000);
|
---|
| 1710 | e1000_initialize_tx_registers(e1000);
|
---|
| 1711 | e1000_fill_mac_from_eeprom(e1000);
|
---|
| 1712 | e1000_initialize_filters(e1000);
|
---|
| 1713 | e1000_initialize_vlan(e1000);
|
---|
[bf84871] | 1714 |
|
---|
| 1715 | return EOK;
|
---|
| 1716 | }
|
---|
| 1717 |
|
---|
[1bc35b5] | 1718 | /** Activate the device to receive and transmit frames
|
---|
[bf84871] | 1719 | *
|
---|
[c4be33a] | 1720 | * @param nic NIC driver data
|
---|
[1df224c] | 1721 | *
|
---|
| 1722 | * @return EOK if activated successfully
|
---|
| 1723 | * @return Error code otherwise
|
---|
| 1724 | *
|
---|
[bf84871] | 1725 | */
|
---|
[c4be33a] | 1726 | static int e1000_on_activating(nic_t *nic)
|
---|
[bf84871] | 1727 | {
|
---|
[c4be33a] | 1728 | assert(nic);
|
---|
[1df224c] | 1729 |
|
---|
[c4be33a] | 1730 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 1731 |
|
---|
[c4be33a] | 1732 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
| 1733 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
| 1734 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[1df224c] | 1735 |
|
---|
[c4be33a] | 1736 | e1000_enable_interrupts(e1000);
|
---|
[1df224c] | 1737 |
|
---|
[c4be33a] | 1738 | nic_enable_interrupt(nic, e1000->irq);
|
---|
[bf84871] | 1739 |
|
---|
[c4be33a] | 1740 | e1000_clear_rx_ring(e1000);
|
---|
| 1741 | e1000_enable_rx(e1000);
|
---|
[1df224c] | 1742 |
|
---|
[c4be33a] | 1743 | e1000_clear_tx_ring(nic);
|
---|
| 1744 | e1000_enable_tx(e1000);
|
---|
[bf84871] | 1745 |
|
---|
[c4be33a] | 1746 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[bf84871] | 1747 | ctrl |= CTRL_SLU;
|
---|
[c4be33a] | 1748 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[bf84871] | 1749 |
|
---|
[c4be33a] | 1750 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
| 1751 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
| 1752 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[1df224c] | 1753 |
|
---|
[bf84871] | 1754 | return EOK;
|
---|
| 1755 | }
|
---|
| 1756 |
|
---|
| 1757 | /** Callback for NIC_STATE_DOWN change
|
---|
| 1758 | *
|
---|
[c4be33a] | 1759 | * @param nic NIC driver data
|
---|
[1df224c] | 1760 | *
|
---|
| 1761 | * @return EOK if succeed
|
---|
| 1762 | * @return Error code otherwise
|
---|
| 1763 | *
|
---|
[bf84871] | 1764 | */
|
---|
[c4be33a] | 1765 | static int e1000_on_down_unlocked(nic_t *nic)
|
---|
[bf84871] | 1766 | {
|
---|
[c4be33a] | 1767 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[bf84871] | 1768 |
|
---|
[c4be33a] | 1769 | uint32_t ctrl = E1000_REG_READ(e1000, E1000_CTRL);
|
---|
[bf84871] | 1770 | ctrl &= ~CTRL_SLU;
|
---|
[c4be33a] | 1771 | E1000_REG_WRITE(e1000, E1000_CTRL, ctrl);
|
---|
[bf84871] | 1772 |
|
---|
[c4be33a] | 1773 | e1000_disable_tx(e1000);
|
---|
| 1774 | e1000_disable_rx(e1000);
|
---|
[bf84871] | 1775 |
|
---|
[c4be33a] | 1776 | nic_disable_interrupt(nic, e1000->irq);
|
---|
| 1777 | e1000_disable_interrupts(e1000);
|
---|
[bf84871] | 1778 |
|
---|
[1df224c] | 1779 | /*
|
---|
| 1780 | * Wait for the for the end of all data
|
---|
| 1781 | * transfers to descriptors.
|
---|
| 1782 | */
|
---|
[bf84871] | 1783 | usleep(100);
|
---|
[1df224c] | 1784 |
|
---|
[bf84871] | 1785 | return EOK;
|
---|
| 1786 | }
|
---|
| 1787 |
|
---|
| 1788 | /** Callback for NIC_STATE_DOWN change
|
---|
| 1789 | *
|
---|
[c4be33a] | 1790 | * @param nic NIC driver data
|
---|
[1df224c] | 1791 | *
|
---|
| 1792 | * @return EOK if succeed
|
---|
| 1793 | * @return Error code otherwise
|
---|
| 1794 | *
|
---|
[bf84871] | 1795 | */
|
---|
[c4be33a] | 1796 | static int e1000_on_down(nic_t *nic)
|
---|
[bf84871] | 1797 | {
|
---|
[c4be33a] | 1798 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[bf84871] | 1799 |
|
---|
[c4be33a] | 1800 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
| 1801 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
| 1802 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[1df224c] | 1803 |
|
---|
[c4be33a] | 1804 | int rc = e1000_on_down_unlocked(nic);
|
---|
[bf84871] | 1805 |
|
---|
[c4be33a] | 1806 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
| 1807 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
| 1808 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 1809 |
|
---|
| 1810 | return rc;
|
---|
| 1811 | }
|
---|
| 1812 |
|
---|
| 1813 | /** Callback for NIC_STATE_STOPPED change
|
---|
| 1814 | *
|
---|
[c4be33a] | 1815 | * @param nic NIC driver data
|
---|
[1df224c] | 1816 | *
|
---|
| 1817 | * @return EOK if succeed
|
---|
| 1818 | * @return Error code otherwise
|
---|
| 1819 | *
|
---|
[bf84871] | 1820 | */
|
---|
[c4be33a] | 1821 | static int e1000_on_stopping(nic_t *nic)
|
---|
[bf84871] | 1822 | {
|
---|
[c4be33a] | 1823 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[bf84871] | 1824 |
|
---|
[c4be33a] | 1825 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
| 1826 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
| 1827 | fibril_mutex_lock(&e1000->ctrl_lock);
|
---|
[bf84871] | 1828 |
|
---|
[c4be33a] | 1829 | int rc = e1000_on_down_unlocked(nic);
|
---|
[1df224c] | 1830 | if (rc == EOK)
|
---|
[c4be33a] | 1831 | rc = e1000_reset(nic);
|
---|
[bf84871] | 1832 |
|
---|
[c4be33a] | 1833 | fibril_mutex_unlock(&e1000->ctrl_lock);
|
---|
| 1834 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
| 1835 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 1836 |
|
---|
| 1837 | return rc;
|
---|
| 1838 | }
|
---|
| 1839 |
|
---|
| 1840 | /** Create driver data structure
|
---|
| 1841 | *
|
---|
[1df224c] | 1842 | * @return Intialized device data structure or NULL
|
---|
| 1843 | *
|
---|
[bf84871] | 1844 | */
|
---|
| 1845 | static e1000_t *e1000_create_dev_data(ddf_dev_t *dev)
|
---|
| 1846 | {
|
---|
| 1847 | assert(dev);
|
---|
| 1848 | assert(!dev->driver_data);
|
---|
[1df224c] | 1849 |
|
---|
[c4be33a] | 1850 | nic_t *nic = nic_create_and_bind(dev);
|
---|
| 1851 | if (!nic)
|
---|
[bf84871] | 1852 | return NULL;
|
---|
[1df224c] | 1853 |
|
---|
[c4be33a] | 1854 | e1000_t *e1000 = malloc(sizeof(e1000_t));
|
---|
| 1855 | if (!e1000) {
|
---|
[bf84871] | 1856 | nic_unbind_and_destroy(dev);
|
---|
| 1857 | return NULL;
|
---|
| 1858 | }
|
---|
[1df224c] | 1859 |
|
---|
[c4be33a] | 1860 | bzero(e1000, sizeof(e1000_t));
|
---|
[1df224c] | 1861 |
|
---|
[c4be33a] | 1862 | nic_set_specific(nic, e1000);
|
---|
[6d8455d] | 1863 | nic_set_send_frame_handler(nic, e1000_send_frame);
|
---|
[c4be33a] | 1864 | nic_set_state_change_handlers(nic, e1000_on_activating,
|
---|
[1df224c] | 1865 | e1000_on_down, e1000_on_stopping);
|
---|
[c4be33a] | 1866 | nic_set_filtering_change_handlers(nic,
|
---|
[1df224c] | 1867 | e1000_on_unicast_mode_change, e1000_on_multicast_mode_change,
|
---|
| 1868 | e1000_on_broadcast_mode_change, NULL, e1000_on_vlan_mask_change);
|
---|
[c4be33a] | 1869 | nic_set_poll_handlers(nic, e1000_poll_mode_change, e1000_poll);
|
---|
[1df224c] | 1870 |
|
---|
[c4be33a] | 1871 | fibril_mutex_initialize(&e1000->ctrl_lock);
|
---|
| 1872 | fibril_mutex_initialize(&e1000->rx_lock);
|
---|
| 1873 | fibril_mutex_initialize(&e1000->tx_lock);
|
---|
| 1874 | fibril_mutex_initialize(&e1000->eeprom_lock);
|
---|
[bf84871] | 1875 |
|
---|
[c4be33a] | 1876 | return e1000;
|
---|
[bf84871] | 1877 | }
|
---|
| 1878 |
|
---|
[1df224c] | 1879 | /** Delete driver data structure
|
---|
| 1880 | *
|
---|
| 1881 | * @param data E1000 device data structure
|
---|
[bf84871] | 1882 | *
|
---|
| 1883 | */
|
---|
| 1884 | inline static void e1000_delete_dev_data(ddf_dev_t *dev)
|
---|
| 1885 | {
|
---|
| 1886 | assert(dev);
|
---|
[1df224c] | 1887 |
|
---|
[bf84871] | 1888 | if (dev->driver_data != NULL)
|
---|
| 1889 | nic_unbind_and_destroy(dev);
|
---|
| 1890 | }
|
---|
| 1891 |
|
---|
[1df224c] | 1892 | /** Clean up the E1000 device structure.
|
---|
| 1893 | *
|
---|
| 1894 | * @param dev Device structure.
|
---|
[bf84871] | 1895 | *
|
---|
| 1896 | */
|
---|
| 1897 | static void e1000_dev_cleanup(ddf_dev_t *dev)
|
---|
| 1898 | {
|
---|
| 1899 | assert(dev);
|
---|
[1df224c] | 1900 |
|
---|
[bf84871] | 1901 | e1000_delete_dev_data(dev);
|
---|
[1df224c] | 1902 |
|
---|
[bf84871] | 1903 | if (dev->parent_sess != NULL) {
|
---|
| 1904 | async_hangup(dev->parent_sess);
|
---|
| 1905 | dev->parent_sess = NULL;
|
---|
| 1906 | }
|
---|
| 1907 | }
|
---|
| 1908 |
|
---|
| 1909 | /** Fill the irq and io_addr part of device data structure
|
---|
| 1910 | *
|
---|
[1df224c] | 1911 | * The hw_resources must be obtained before calling this function
|
---|
| 1912 | *
|
---|
| 1913 | * @param dev Device structure
|
---|
| 1914 | * @param hw_resources Hardware resources obtained from the parent device
|
---|
| 1915 | *
|
---|
| 1916 | * @return EOK if succeed
|
---|
| 1917 | * @return Negative error code otherwise
|
---|
[bf84871] | 1918 | *
|
---|
| 1919 | */
|
---|
[1df224c] | 1920 | static int e1000_fill_resource_info(ddf_dev_t *dev,
|
---|
| 1921 | const hw_res_list_parsed_t *hw_resources)
|
---|
[bf84871] | 1922 | {
|
---|
| 1923 | assert(dev != NULL);
|
---|
| 1924 | assert(hw_resources != NULL);
|
---|
| 1925 | assert(dev->driver_data != NULL);
|
---|
[1df224c] | 1926 |
|
---|
[c4be33a] | 1927 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
---|
[1df224c] | 1928 |
|
---|
| 1929 | if (hw_resources->irqs.count != 1)
|
---|
[bf84871] | 1930 | return EINVAL;
|
---|
[1df224c] | 1931 |
|
---|
[c4be33a] | 1932 | e1000->irq = hw_resources->irqs.irqs[0];
|
---|
| 1933 | e1000->reg_base_phys =
|
---|
[1df224c] | 1934 | MEMADDR_TO_PTR(hw_resources->mem_ranges.ranges[0].address);
|
---|
| 1935 |
|
---|
[bf84871] | 1936 | return EOK;
|
---|
| 1937 | }
|
---|
| 1938 |
|
---|
| 1939 | /** Obtain information about hardware resources of the device
|
---|
| 1940 | *
|
---|
[1df224c] | 1941 | * The device must be connected to the parent
|
---|
| 1942 | *
|
---|
| 1943 | * @param dev Device structure
|
---|
| 1944 | *
|
---|
| 1945 | * @return EOK if succeed
|
---|
| 1946 | * @return Negative error code otherwise
|
---|
[bf84871] | 1947 | *
|
---|
| 1948 | */
|
---|
| 1949 | static int e1000_get_resource_info(ddf_dev_t *dev)
|
---|
| 1950 | {
|
---|
| 1951 | assert(dev != NULL);
|
---|
| 1952 | assert(NIC_DATA_DEV(dev) != NULL);
|
---|
[1df224c] | 1953 |
|
---|
[bf84871] | 1954 | hw_res_list_parsed_t hw_res_parsed;
|
---|
| 1955 | hw_res_list_parsed_init(&hw_res_parsed);
|
---|
[1df224c] | 1956 |
|
---|
[bf84871] | 1957 | /* Get hw resources form parent driver */
|
---|
| 1958 | int rc = nic_get_resources(NIC_DATA_DEV(dev), &hw_res_parsed);
|
---|
| 1959 | if (rc != EOK)
|
---|
| 1960 | return rc;
|
---|
[1df224c] | 1961 |
|
---|
[bf84871] | 1962 | /* Fill resources information to the device */
|
---|
| 1963 | rc = e1000_fill_resource_info(dev, &hw_res_parsed);
|
---|
| 1964 | hw_res_list_parsed_clean(&hw_res_parsed);
|
---|
[1df224c] | 1965 |
|
---|
[bf84871] | 1966 | return rc;
|
---|
| 1967 | }
|
---|
| 1968 |
|
---|
[1df224c] | 1969 | /** Initialize the E1000 device structure
|
---|
| 1970 | *
|
---|
| 1971 | * @param dev Device information
|
---|
| 1972 | *
|
---|
| 1973 | * @return EOK if succeed
|
---|
| 1974 | * @return Negative error code otherwise
|
---|
[bf84871] | 1975 | *
|
---|
| 1976 | */
|
---|
| 1977 | static int e1000_device_initialize(ddf_dev_t *dev)
|
---|
| 1978 | {
|
---|
| 1979 | /* Allocate driver data for the device. */
|
---|
[c4be33a] | 1980 | e1000_t *e1000 = e1000_create_dev_data(dev);
|
---|
[77c2b02] | 1981 | if (e1000 == NULL) {
|
---|
| 1982 | ddf_msg(LVL_ERROR, "Unable to allocate device softstate");
|
---|
[bf84871] | 1983 | return ENOMEM;
|
---|
[77c2b02] | 1984 | }
|
---|
[1df224c] | 1985 |
|
---|
[bf84871] | 1986 | /* Obtain and fill hardware resources info */
|
---|
[9916841] | 1987 | int rc = e1000_get_resource_info(dev);
|
---|
[bf84871] | 1988 | if (rc != EOK) {
|
---|
[77c2b02] | 1989 | ddf_msg(LVL_ERROR, "Cannot obtain hardware resources");
|
---|
[1df224c] | 1990 | e1000_dev_cleanup(dev);
|
---|
| 1991 | return rc;
|
---|
[bf84871] | 1992 | }
|
---|
| 1993 |
|
---|
[77c2b02] | 1994 | uint16_t device_id;
|
---|
[bf84871] | 1995 | rc = pci_config_space_read_16(dev->parent_sess, PCI_DEVICE_ID,
|
---|
[77c2b02] | 1996 | &device_id);
|
---|
[bf84871] | 1997 | if (rc != EOK) {
|
---|
[77c2b02] | 1998 | ddf_msg(LVL_ERROR, "Cannot access PCI configuration space");
|
---|
[1df224c] | 1999 | e1000_dev_cleanup(dev);
|
---|
| 2000 | return rc;
|
---|
[bf84871] | 2001 | }
|
---|
[1df224c] | 2002 |
|
---|
[77c2b02] | 2003 | e1000_board_t board;
|
---|
| 2004 | switch (device_id) {
|
---|
[9f0fb84] | 2005 | case 0x100e:
|
---|
| 2006 | case 0x1015:
|
---|
| 2007 | case 0x1016:
|
---|
| 2008 | case 0x1017:
|
---|
| 2009 | board = E1000_82540;
|
---|
| 2010 | break;
|
---|
[77c2b02] | 2011 | case 0x1013:
|
---|
| 2012 | case 0x1018:
|
---|
| 2013 | case 0x1078:
|
---|
| 2014 | board = E1000_82541;
|
---|
| 2015 | break;
|
---|
| 2016 | case 0x1076:
|
---|
| 2017 | case 0x1077:
|
---|
| 2018 | case 0x107c:
|
---|
| 2019 | board = E1000_82541REV2;
|
---|
| 2020 | break;
|
---|
[9f0fb84] | 2021 | case 0x100f:
|
---|
| 2022 | case 0x1011:
|
---|
| 2023 | case 0x1026:
|
---|
| 2024 | case 0x1027:
|
---|
| 2025 | case 0x1028:
|
---|
| 2026 | board = E1000_82545;
|
---|
| 2027 | break;
|
---|
| 2028 | case 0x1010:
|
---|
| 2029 | case 0x1012:
|
---|
| 2030 | case 0x101d:
|
---|
| 2031 | case 0x1079:
|
---|
| 2032 | case 0x107a:
|
---|
| 2033 | case 0x107b:
|
---|
| 2034 | board = E1000_82546;
|
---|
| 2035 | break;
|
---|
[77c2b02] | 2036 | case 0x1019:
|
---|
| 2037 | case 0x101a:
|
---|
| 2038 | board = E1000_82547;
|
---|
| 2039 | break;
|
---|
| 2040 | case 0x10b9:
|
---|
| 2041 | board = E1000_82572;
|
---|
| 2042 | break;
|
---|
| 2043 | case 0x1096:
|
---|
| 2044 | board = E1000_80003ES2;
|
---|
| 2045 | break;
|
---|
| 2046 | default:
|
---|
| 2047 | ddf_msg(LVL_ERROR, "Device not supported (%#" PRIx16 ")",
|
---|
| 2048 | device_id);
|
---|
| 2049 | e1000_dev_cleanup(dev);
|
---|
| 2050 | return ENOTSUP;
|
---|
| 2051 | }
|
---|
| 2052 |
|
---|
| 2053 | switch (board) {
|
---|
[9f0fb84] | 2054 | case E1000_82540:
|
---|
[77c2b02] | 2055 | case E1000_82541:
|
---|
| 2056 | case E1000_82541REV2:
|
---|
[9f0fb84] | 2057 | case E1000_82545:
|
---|
| 2058 | case E1000_82546:
|
---|
[77c2b02] | 2059 | e1000->info.eerd_start = 0x01;
|
---|
| 2060 | e1000->info.eerd_done = 0x10;
|
---|
| 2061 | e1000->info.eerd_address_offset = 8;
|
---|
| 2062 | e1000->info.eerd_data_offset = 16;
|
---|
| 2063 | break;
|
---|
| 2064 | case E1000_82547:
|
---|
[d81eaf94] | 2065 | case E1000_82572:
|
---|
[77c2b02] | 2066 | case E1000_80003ES2:
|
---|
| 2067 | e1000->info.eerd_start = 0x01;
|
---|
| 2068 | e1000->info.eerd_done = 0x02;
|
---|
| 2069 | e1000->info.eerd_address_offset = 2;
|
---|
| 2070 | e1000->info.eerd_data_offset = 16;
|
---|
| 2071 | break;
|
---|
| 2072 | }
|
---|
| 2073 |
|
---|
[1df224c] | 2074 | return EOK;
|
---|
[bf84871] | 2075 | }
|
---|
| 2076 |
|
---|
[1df224c] | 2077 | /** Enable the I/O ports of the device.
|
---|
| 2078 | *
|
---|
| 2079 | * @param dev E1000 device.
|
---|
| 2080 | *
|
---|
| 2081 | * @return EOK if successed
|
---|
| 2082 | * @return Negative error code otherwise
|
---|
[bf84871] | 2083 | *
|
---|
| 2084 | */
|
---|
| 2085 | static int e1000_pio_enable(ddf_dev_t *dev)
|
---|
| 2086 | {
|
---|
[c4be33a] | 2087 | e1000_t *e1000 = DRIVER_DATA_DEV(dev);
|
---|
[1df224c] | 2088 |
|
---|
[c4be33a] | 2089 | int rc = pio_enable(e1000->reg_base_phys, 8 * PAGE_SIZE,
|
---|
| 2090 | &e1000->reg_base_virt);
|
---|
[1df224c] | 2091 | if (rc != EOK)
|
---|
[bf84871] | 2092 | return EADDRNOTAVAIL;
|
---|
[1df224c] | 2093 |
|
---|
[bf84871] | 2094 | return EOK;
|
---|
| 2095 | }
|
---|
| 2096 |
|
---|
[9916841] | 2097 | /** Probe and initialize the newly added device.
|
---|
[bf84871] | 2098 | *
|
---|
[1df224c] | 2099 | * @param dev E1000 device.
|
---|
| 2100 | *
|
---|
[bf84871] | 2101 | */
|
---|
[9916841] | 2102 | int e1000_dev_add(ddf_dev_t *dev)
|
---|
[bf84871] | 2103 | {
|
---|
[e86b8f0] | 2104 | ddf_fun_t *fun;
|
---|
[bf84871] | 2105 | assert(dev);
|
---|
[1df224c] | 2106 |
|
---|
| 2107 | /* Initialize device structure for E1000 */
|
---|
[bf84871] | 2108 | int rc = e1000_device_initialize(dev);
|
---|
| 2109 | if (rc != EOK)
|
---|
| 2110 | return rc;
|
---|
| 2111 |
|
---|
[1df224c] | 2112 | /* Device initialization */
|
---|
[c4be33a] | 2113 | nic_t *nic = dev->driver_data;
|
---|
| 2114 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 2115 |
|
---|
[bf84871] | 2116 | /* Map registers */
|
---|
| 2117 | rc = e1000_pio_enable(dev);
|
---|
| 2118 | if (rc != EOK)
|
---|
| 2119 | goto err_destroy;
|
---|
[1df224c] | 2120 |
|
---|
[c4be33a] | 2121 | e1000_initialize_registers(e1000);
|
---|
| 2122 | rc = e1000_initialize_tx_structure(e1000);
|
---|
[1df224c] | 2123 | if (rc != EOK)
|
---|
[bf84871] | 2124 | goto err_pio;
|
---|
[1df224c] | 2125 |
|
---|
[c4be33a] | 2126 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[bf84871] | 2127 |
|
---|
[c4be33a] | 2128 | e1000_fill_mac_from_eeprom(e1000);
|
---|
| 2129 | e1000_initialize_filters(e1000);
|
---|
[bf84871] | 2130 |
|
---|
[c4be33a] | 2131 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[1df224c] | 2132 |
|
---|
[c4be33a] | 2133 | e1000_initialize_vlan(e1000);
|
---|
[1df224c] | 2134 |
|
---|
[e86b8f0] | 2135 | fun = ddf_fun_create(nic_get_ddf_dev(nic), fun_exposed, "port0");
|
---|
| 2136 | if (fun == NULL)
|
---|
[bf84871] | 2137 | goto err_tx_structure;
|
---|
[e86b8f0] | 2138 | nic_set_ddf_fun(nic, fun);
|
---|
| 2139 | fun->ops = &e1000_dev_ops;
|
---|
| 2140 | fun->driver_data = nic;
|
---|
[bf84871] | 2141 |
|
---|
[c4be33a] | 2142 | rc = e1000_register_int_handler(nic);
|
---|
[1df224c] | 2143 | if (rc != EOK)
|
---|
[e86b8f0] | 2144 | goto err_fun_create;
|
---|
[bf84871] | 2145 |
|
---|
[c4be33a] | 2146 | rc = nic_connect_to_services(nic);
|
---|
[1df224c] | 2147 | if (rc != EOK)
|
---|
[bf84871] | 2148 | goto err_irq;
|
---|
| 2149 |
|
---|
[c4be33a] | 2150 | rc = e1000_initialize_rx_structure(nic);
|
---|
[1df224c] | 2151 | if (rc != EOK)
|
---|
[bf84871] | 2152 | goto err_irq;
|
---|
| 2153 |
|
---|
| 2154 | nic_address_t e1000_address;
|
---|
[c4be33a] | 2155 | e1000_get_address(e1000, &e1000_address);
|
---|
| 2156 | rc = nic_report_address(nic, &e1000_address);
|
---|
[1df224c] | 2157 | if (rc != EOK)
|
---|
[bf84871] | 2158 | goto err_rx_structure;
|
---|
[1df224c] | 2159 |
|
---|
[bf84871] | 2160 | struct timeval period;
|
---|
| 2161 | period.tv_sec = 0;
|
---|
[1df224c] | 2162 | period.tv_usec = E1000_DEFAULT_INTERRUPT_INTERVAL_USEC;
|
---|
[c4be33a] | 2163 | rc = nic_report_poll_mode(nic, NIC_POLL_PERIODIC, &period);
|
---|
[1df224c] | 2164 | if (rc != EOK)
|
---|
[bf84871] | 2165 | goto err_rx_structure;
|
---|
| 2166 |
|
---|
[e86b8f0] | 2167 | rc = ddf_fun_bind(fun);
|
---|
| 2168 | if (rc != EOK)
|
---|
| 2169 | goto err_fun_bind;
|
---|
| 2170 |
|
---|
| 2171 | rc = ddf_fun_add_to_category(fun, DEVICE_CATEGORY_NIC);
|
---|
| 2172 | if (rc != EOK)
|
---|
| 2173 | goto err_add_to_cat;
|
---|
| 2174 |
|
---|
[bf84871] | 2175 | return EOK;
|
---|
[1df224c] | 2176 |
|
---|
[e86b8f0] | 2177 | err_add_to_cat:
|
---|
| 2178 | ddf_fun_unbind(fun);
|
---|
| 2179 | err_fun_bind:
|
---|
[bf84871] | 2180 | err_rx_structure:
|
---|
[c4be33a] | 2181 | e1000_uninitialize_rx_structure(nic);
|
---|
[bf84871] | 2182 | err_irq:
|
---|
| 2183 | unregister_interrupt_handler(dev, DRIVER_DATA_DEV(dev)->irq);
|
---|
[e86b8f0] | 2184 | err_fun_create:
|
---|
| 2185 | ddf_fun_destroy(fun);
|
---|
| 2186 | nic_set_ddf_fun(nic, NULL);
|
---|
[bf84871] | 2187 | err_tx_structure:
|
---|
[c4be33a] | 2188 | e1000_uninitialize_tx_structure(e1000);
|
---|
[bf84871] | 2189 | err_pio:
|
---|
[1df224c] | 2190 | // TODO: e1000_pio_disable(dev);
|
---|
[bf84871] | 2191 | err_destroy:
|
---|
| 2192 | e1000_dev_cleanup(dev);
|
---|
| 2193 | return rc;
|
---|
[1df224c] | 2194 | }
|
---|
[bf84871] | 2195 |
|
---|
| 2196 | /** Read 16-bit value from EEPROM of E1000 adapter
|
---|
[1df224c] | 2197 | *
|
---|
| 2198 | * Read using the EERD register.
|
---|
| 2199 | *
|
---|
| 2200 | * @param device E1000 device
|
---|
| 2201 | * @param eeprom_address 8-bit EEPROM address
|
---|
| 2202 | *
|
---|
| 2203 | * @return 16-bit value from EEPROM
|
---|
| 2204 | *
|
---|
[bf84871] | 2205 | */
|
---|
[c4be33a] | 2206 | static uint16_t e1000_eeprom_read(e1000_t *e1000, uint8_t eeprom_address)
|
---|
[bf84871] | 2207 | {
|
---|
[c4be33a] | 2208 | fibril_mutex_lock(&e1000->eeprom_lock);
|
---|
[1df224c] | 2209 |
|
---|
| 2210 | /* Write address and START bit to EERD register */
|
---|
[77c2b02] | 2211 | uint32_t write_data = e1000->info.eerd_start |
|
---|
| 2212 | (((uint32_t) eeprom_address) <<
|
---|
| 2213 | e1000->info.eerd_address_offset);
|
---|
[c4be33a] | 2214 | E1000_REG_WRITE(e1000, E1000_EERD, write_data);
|
---|
[bf84871] | 2215 |
|
---|
[c4be33a] | 2216 | uint32_t eerd = E1000_REG_READ(e1000, E1000_EERD);
|
---|
[77c2b02] | 2217 | while ((eerd & e1000->info.eerd_done) == 0) {
|
---|
[1df224c] | 2218 | usleep(1);
|
---|
[c4be33a] | 2219 | eerd = E1000_REG_READ(e1000, E1000_EERD);
|
---|
[bf84871] | 2220 | }
|
---|
| 2221 |
|
---|
[c4be33a] | 2222 | fibril_mutex_unlock(&e1000->eeprom_lock);
|
---|
[1df224c] | 2223 |
|
---|
[77c2b02] | 2224 | return (uint16_t) (eerd >> e1000->info.eerd_data_offset);
|
---|
[bf84871] | 2225 | }
|
---|
| 2226 |
|
---|
| 2227 | /** Get MAC address of the E1000 adapter
|
---|
| 2228 | *
|
---|
[1df224c] | 2229 | * @param device E1000 device
|
---|
| 2230 | * @param address Place to store the address
|
---|
| 2231 | * @param max_len Maximal addresss length to store
|
---|
| 2232 | *
|
---|
| 2233 | * @return EOK if succeed
|
---|
| 2234 | * @return Negative error code otherwise
|
---|
| 2235 | *
|
---|
[bf84871] | 2236 | */
|
---|
[c4be33a] | 2237 | static int e1000_get_address(e1000_t *e1000, nic_address_t *address)
|
---|
[bf84871] | 2238 | {
|
---|
[c4be33a] | 2239 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
[1df224c] | 2240 |
|
---|
| 2241 | uint8_t *mac0_dest = (uint8_t *) address->address;
|
---|
| 2242 | uint8_t *mac1_dest = (uint8_t *) address->address + 1;
|
---|
| 2243 | uint8_t *mac2_dest = (uint8_t *) address->address + 2;
|
---|
| 2244 | uint8_t *mac3_dest = (uint8_t *) address->address + 3;
|
---|
| 2245 | uint8_t *mac4_dest = (uint8_t *) address->address + 4;
|
---|
| 2246 | uint8_t *mac5_dest = (uint8_t *) address->address + 5;
|
---|
| 2247 |
|
---|
[c4be33a] | 2248 | uint32_t rah = E1000_REG_READ(e1000, E1000_RAH_ARRAY(0));
|
---|
| 2249 | uint32_t ral = E1000_REG_READ(e1000, E1000_RAL_ARRAY(0));
|
---|
[bf84871] | 2250 |
|
---|
| 2251 | *mac0_dest = (uint8_t) ral;
|
---|
| 2252 | *mac1_dest = (uint8_t) (ral >> 8);
|
---|
| 2253 | *mac2_dest = (uint8_t) (ral >> 16);
|
---|
| 2254 | *mac3_dest = (uint8_t) (ral >> 24);
|
---|
| 2255 | *mac4_dest = (uint8_t) rah;
|
---|
| 2256 | *mac5_dest = (uint8_t) (rah >> 8);
|
---|
[1df224c] | 2257 |
|
---|
[c4be33a] | 2258 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[bf84871] | 2259 | return EOK;
|
---|
| 2260 | };
|
---|
| 2261 |
|
---|
| 2262 | /** Set card MAC address
|
---|
| 2263 | *
|
---|
[1df224c] | 2264 | * @param device E1000 device
|
---|
| 2265 | * @param address Address
|
---|
| 2266 | *
|
---|
| 2267 | * @return EOK if succeed
|
---|
| 2268 | * @return Negative error code otherwise
|
---|
[bf84871] | 2269 | */
|
---|
| 2270 | static int e1000_set_addr(ddf_fun_t *dev, const nic_address_t *addr)
|
---|
| 2271 | {
|
---|
[c4be33a] | 2272 | nic_t *nic = NIC_DATA_DEV(dev);
|
---|
| 2273 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
[1df224c] | 2274 |
|
---|
[c4be33a] | 2275 | fibril_mutex_lock(&e1000->rx_lock);
|
---|
| 2276 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
[1df224c] | 2277 |
|
---|
[c4be33a] | 2278 | int rc = nic_report_address(nic, addr);
|
---|
[1df224c] | 2279 | if (rc == EOK)
|
---|
[c4be33a] | 2280 | e1000_write_receive_address(e1000, 0, addr, false);
|
---|
[1df224c] | 2281 |
|
---|
[c4be33a] | 2282 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
| 2283 | fibril_mutex_unlock(&e1000->rx_lock);
|
---|
[1df224c] | 2284 |
|
---|
[bf84871] | 2285 | return rc;
|
---|
| 2286 | }
|
---|
| 2287 |
|
---|
[c4be33a] | 2288 | static void e1000_eeprom_get_address(e1000_t *e1000,
|
---|
[1df224c] | 2289 | nic_address_t *address)
|
---|
[bf84871] | 2290 | {
|
---|
[1df224c] | 2291 | uint16_t *mac0_dest = (uint16_t *) address->address;
|
---|
| 2292 | uint16_t *mac2_dest = (uint16_t *) (address->address + 2);
|
---|
| 2293 | uint16_t *mac4_dest = (uint16_t *) (address->address + 4);
|
---|
| 2294 |
|
---|
[c4be33a] | 2295 | *mac0_dest = e1000_eeprom_read(e1000, 0);
|
---|
| 2296 | *mac2_dest = e1000_eeprom_read(e1000, 1);
|
---|
| 2297 | *mac4_dest = e1000_eeprom_read(e1000, 2);
|
---|
[bf84871] | 2298 | }
|
---|
| 2299 |
|
---|
[6d8455d] | 2300 | /** Send frame
|
---|
[1df224c] | 2301 | *
|
---|
[c4be33a] | 2302 | * @param nic NIC driver data structure
|
---|
[6d8455d] | 2303 | * @param data Frame data
|
---|
| 2304 | * @param size Frame size in bytes
|
---|
[bf84871] | 2305 | *
|
---|
[1df224c] | 2306 | * @return EOK if succeed
|
---|
| 2307 | * @return Error code in the case of error
|
---|
[bf84871] | 2308 | *
|
---|
| 2309 | */
|
---|
[6d8455d] | 2310 | static void e1000_send_frame(nic_t *nic, void *data, size_t size)
|
---|
[bf84871] | 2311 | {
|
---|
[c4be33a] | 2312 | assert(nic);
|
---|
[1df224c] | 2313 |
|
---|
[c4be33a] | 2314 | e1000_t *e1000 = DRIVER_DATA_NIC(nic);
|
---|
| 2315 | fibril_mutex_lock(&e1000->tx_lock);
|
---|
[1df224c] | 2316 |
|
---|
[c4be33a] | 2317 | uint32_t tdt = E1000_REG_READ(e1000, E1000_TDT);
|
---|
[1df224c] | 2318 | e1000_tx_descriptor_t *tx_descriptor_addr = (e1000_tx_descriptor_t *)
|
---|
[c4be33a] | 2319 | (e1000->tx_ring_virt + tdt * sizeof(e1000_tx_descriptor_t));
|
---|
[1df224c] | 2320 |
|
---|
[bf84871] | 2321 | bool descriptor_available = false;
|
---|
[1df224c] | 2322 |
|
---|
| 2323 | /* Descriptor never used */
|
---|
| 2324 | if (tx_descriptor_addr->length == 0)
|
---|
[bf84871] | 2325 | descriptor_available = true;
|
---|
[1df224c] | 2326 |
|
---|
| 2327 | /* Descriptor done */
|
---|
[6d8455d] | 2328 | if (tx_descriptor_addr->status & TXDESCRIPTOR_STATUS_DD)
|
---|
[bf84871] | 2329 | descriptor_available = true;
|
---|
[1df224c] | 2330 |
|
---|
| 2331 | if (!descriptor_available) {
|
---|
[1bc35b5] | 2332 | /* Frame lost */
|
---|
[c4be33a] | 2333 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
[bf84871] | 2334 | return;
|
---|
| 2335 | }
|
---|
[1df224c] | 2336 |
|
---|
[6d8455d] | 2337 | memcpy(e1000->tx_frame_virt[tdt], data, size);
|
---|
[1df224c] | 2338 |
|
---|
[6d8455d] | 2339 | tx_descriptor_addr->phys_addr = PTR_TO_U64(e1000->tx_frame_phys[tdt]);
|
---|
| 2340 | tx_descriptor_addr->length = size;
|
---|
[1df224c] | 2341 |
|
---|
| 2342 | /*
|
---|
| 2343 | * Report status to STATUS.DD (descriptor done),
|
---|
| 2344 | * add ethernet CRC, end of packet.
|
---|
| 2345 | */
|
---|
| 2346 | tx_descriptor_addr->command = TXDESCRIPTOR_COMMAND_RS |
|
---|
| 2347 | TXDESCRIPTOR_COMMAND_IFCS |
|
---|
| 2348 | TXDESCRIPTOR_COMMAND_EOP;
|
---|
| 2349 |
|
---|
[bf84871] | 2350 | tx_descriptor_addr->checksum_offset = 0;
|
---|
| 2351 | tx_descriptor_addr->status = 0;
|
---|
[c4be33a] | 2352 | if (e1000->vlan_tag_add) {
|
---|
| 2353 | tx_descriptor_addr->special = e1000->vlan_tag;
|
---|
[bf84871] | 2354 | tx_descriptor_addr->command |= TXDESCRIPTOR_COMMAND_VLE;
|
---|
[1df224c] | 2355 | } else
|
---|
| 2356 | tx_descriptor_addr->special = 0;
|
---|
| 2357 |
|
---|
[bf84871] | 2358 | tx_descriptor_addr->checksum_start_field = 0;
|
---|
| 2359 |
|
---|
[1df224c] | 2360 | tdt++;
|
---|
[1bc35b5] | 2361 | if (tdt == E1000_TX_FRAME_COUNT)
|
---|
[bf84871] | 2362 | tdt = 0;
|
---|
[1df224c] | 2363 |
|
---|
[c4be33a] | 2364 | E1000_REG_WRITE(e1000, E1000_TDT, tdt);
|
---|
[1df224c] | 2365 |
|
---|
[c4be33a] | 2366 | fibril_mutex_unlock(&e1000->tx_lock);
|
---|
[bf84871] | 2367 | }
|
---|
| 2368 |
|
---|
| 2369 | int main(void)
|
---|
| 2370 | {
|
---|
[9916841] | 2371 | int rc = nic_driver_init(NAME);
|
---|
[1df224c] | 2372 | if (rc != EOK)
|
---|
[bf84871] | 2373 | return rc;
|
---|
[1df224c] | 2374 |
|
---|
[c4be33a] | 2375 | nic_driver_implement(&e1000_driver_ops, &e1000_dev_ops,
|
---|
| 2376 | &e1000_nic_iface);
|
---|
[77c2b02] | 2377 |
|
---|
| 2378 | ddf_log_init(NAME, LVL_ERROR);
|
---|
| 2379 | ddf_msg(LVL_NOTE, "HelenOS E1000 driver started");
|
---|
[bf84871] | 2380 | return ddf_driver_main(&e1000_driver);
|
---|
| 2381 | }
|
---|