source: mainline/uspace/drv/infrastructure/rootamdm37x/amdm37x.c@ 878b764

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 878b764 was 7a6d91b, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

rootamdm37x: Reshuffle.

Put device control in its own file.
  • Property mode set to 100644
File size: 14.8 KB
Line 
1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * @defgroup root_amdm37x TI AM/DM37x platform driver.
31 * @brief HelenOS TI AM/DM37x platform driver.
32 * @{
33 */
34
35/** @file
36 */
37
38#include "amdm37x.h"
39
40#include <assert.h>
41#include <ddi.h>
42#include <ddf/log.h>
43#include <errno.h>
44#include <stdio.h>
45
46static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write)
47{
48 printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ",
49 (place - base) + data, place, val);
50}
51
52
53int amdm37x_init(amdm37x_t *device, bool trace)
54{
55 assert(device);
56 int ret = EOK;
57
58 ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE,
59 (void**)&device->cm.usbhost);
60 if (ret != EOK)
61 return ret;
62
63 ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE,
64 (void**)&device->cm.core);
65 if (ret != EOK)
66 return ret;
67
68 ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS,
69 CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks);
70 if (ret != EOK)
71 return ret;
72
73 ret = pio_enable((void*)MPU_CM_BASE_ADDRESS,
74 MPU_CM_SIZE, (void**)&device->cm.mpu);
75 if (ret != EOK)
76 return ret;
77
78 ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS,
79 IVA2_CM_SIZE, (void**)&device->cm.iva2);
80 if (ret != EOK)
81 return ret;
82
83 ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
84 CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
85 if (ret != EOK)
86 return ret;
87
88 ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS,
89 GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global);
90 if (ret != EOK)
91 return ret;
92
93 ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS,
94 AMDM37x_USBTLL_SIZE, (void**)&device->tll);
95 if (ret != EOK)
96 return ret;
97
98 ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS,
99 AMDM37x_UHH_SIZE, (void**)&device->uhh);
100 if (ret != EOK)
101 return ret;
102
103 if (trace) {
104 pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS);
105 pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
106 pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
107 pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS);
108 pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS);
109 pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
110 pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
111 pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS);
112 pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS);
113 }
114 return EOK;
115}
116
117
118/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle.
119 * @param device Register map.
120 *
121 * The idea is to get all DPLLs running and make hw control their power mode,
122 * based on the module requirements (module ICLKs and FCLKs).
123 */
124void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device)
125{
126 assert(device);
127 /* Get SYS_CLK value, it is used as reference clock by all DPLLs,
128 * NFI who sets this or why it is set to specific value. */
129 const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel)
130 & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
131 const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
132 const unsigned base_freq = sys_clk_freq_kHz(osc_clk)
133 / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
134 ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
135 base_freq / 1000, base_freq % 1000);
136
137
138 /* DPLL1 provides MPU(CPU) clock.
139 * It uses SYS_CLK as reference clock and core clock (DPLL3) as
140 * high frequency bypass (MPU then runs on L3 interconnect freq).
141 * It should be setup by fw or u-boot.*/
142 mpu_cm_regs_t *mpu = device->cm.mpu;
143
144 /* Current MPU frequency. */
145 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
146 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
147 /* DPLL active and locked */
148 const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
149 const unsigned multiplier =
150 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
151 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
152 const unsigned divisor =
153 (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK)
154 >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT;
155 const unsigned divisor2 =
156 (pio_read_32(&mpu->clksel2_pll)
157 & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
158 if (multiplier && divisor && divisor2) {
159 /** See AMDM37x TRM p. 300 for the formula */
160 const unsigned freq =
161 ((base_freq * multiplier) / (divisor + 1))
162 / divisor2;
163 ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
164 freq / 1000, freq % 1000);
165 } else {
166 ddf_msg(LVL_WARN, "Frequency divisor and/or "
167 "multiplier value invalid: %d %d %d",
168 multiplier, divisor, divisor2);
169 }
170 } else {
171 /* DPLL in LP bypass mode */
172 const unsigned divisor =
173 MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
174 pio_read_32(&mpu->clksel1_pll));
175 ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
176 " CORE CLK / %d MHz", divisor);
177 }
178 } else {
179 ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
180 }
181 // TODO: Enable this (automatic MPU downclocking):
182#if 0
183 /* Enable low power bypass mode, this will take effect the next lock or
184 * relock sequence. */
185 //TODO: We might need to force re-lock after enabling this
186 pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
187 /* Enable automatic relocking */
188 pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
189#endif
190
191 /* DPLL2 provides IVA(video acceleration) clock.
192 * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
193 * high frequency bypass (IVA runs on L3 freq).
194 */
195 // TODO: We can probably turn this off entirely. IVA is left unused.
196 /* Enable low power bypass mode, this will take effect the next lock or
197 * relock sequence. */
198 //TODO: We might need to force re-lock after enabling this
199 pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
200 /* Enable automatic relocking */
201 pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
202
203 /* DPLL3 provides tons of clocks:
204 * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
205 * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
206 * bypass. It should be setup by fw or u-boot as it controls critical
207 * interconnects.
208 */
209 if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
210 /* DPLL active and locked */
211 const uint32_t reg =
212 pio_read_32(&device->cm.clocks->clksel1_pll);
213 const unsigned multiplier =
214 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
215 const unsigned divisor =
216 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
217 const unsigned divisor2 =
218 CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
219 if (multiplier && divisor && divisor2) {
220 /** See AMDM37x TRM p. 300 for the formula */
221 const unsigned freq =
222 ((base_freq * multiplier) / (divisor + 1)) / divisor2;
223 ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
224 freq / 1000, freq % 1000);
225 const unsigned l3_div =
226 pio_read_32(&device->cm.core->clksel)
227 & CORE_CM_CLKSEL_CLKSEL_L3_MASK;
228 if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
229 l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
230 ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
231 (freq / l3_div) / 1000,
232 (freq / l3_div) % 1000);
233 } else {
234 ddf_msg(LVL_WARN,"L3 interface clock divisor is"
235 " invalid: %d", l3_div);
236 }
237 } else {
238 ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
239 "multiplier value invalid: %d %d %d",
240 multiplier, divisor, divisor2);
241 }
242 } else {
243 ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
244 " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
245 }
246
247 /* Set DPLL3 to automatic to save power */
248 pio_change_32(&device->cm.clocks->autoidle_pll,
249 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC,
250 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
251
252 /* DPLL4 provides peripheral domain clocks:
253 * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
254 * It uses SYS_CLK as reference clock and low frequency bypass.
255 * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so
256 * we can probably turn this off entirely (DSS is still non-functional).
257 */
258 /* Set DPLL4 to automatic to save power */
259 pio_change_32(&device->cm.clocks->autoidle_pll,
260 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
261 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
262
263 /* DPLL5 provide peripheral domain clocks: 120M_FCLK.
264 * It uses SYS_CLK as reference clock and low frequency bypass.
265 * 120M clock is used by HS USB and USB TLL.
266 */
267 // TODO setup DPLL5
268 if ((pio_read_32(&device->cm.clocks->clken2_pll)
269 & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK)
270 != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
271 /* Compute divisors and multiplier
272 * See AMDM37x TRM p. 300 for the formula */
273 assert((base_freq % 100) == 0);
274 const unsigned mult = 1200;
275 const unsigned div = (base_freq / 100) - 1;
276 const unsigned div2 = 1;
277
278 /* Set multiplier */
279 pio_change_32(&device->cm.clocks->clksel4_pll,
280 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult),
281 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10);
282
283 /* Set DPLL divisor */
284 pio_change_32(&device->cm.clocks->clksel4_pll,
285 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div),
286 CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10);
287
288 /* Set output clock divisor */
289 pio_change_32(&device->cm.clocks->clksel5_pll,
290 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2),
291 CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10);
292
293 /* Start DPLL5 */
294 pio_change_32(&device->cm.clocks->clken2_pll,
295 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK,
296 CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10);
297
298 }
299 /* Set DPLL5 to automatic to save power */
300 pio_change_32(&device->cm.clocks->autoidle2_pll,
301 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
302 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5);
303}
304
305/** Enable/disable function and interface clocks for USBTLL and USBHOST.
306 * @param device Register map.
307 * @param on True to switch clocks on.
308 */
309void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled)
310{
311 if (enabled) {
312 /* Enable interface and function clock for USB TLL */
313 pio_set_32(&device->cm.core->fclken3,
314 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
315 pio_set_32(&device->cm.core->iclken3,
316 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
317
318 /* Enable interface and function clock for USB hosts */
319 pio_set_32(&device->cm.usbhost->fclken,
320 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
321 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
322 pio_set_32(&device->cm.usbhost->iclken,
323 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
324#if 0
325 printf("DPLL5 (and everything else) should be on: %"
326 PRIx32" %"PRIx32".\n",
327 pio_read_32(&device->cm.clocks->idlest_ckgen),
328 pio_read_32(&device->cm.clocks->idlest2_ckgen));
329#endif
330 } else {
331 /* Disable interface and function clock for USB hosts */
332 pio_clear_32(&device->cm.usbhost->iclken,
333 USBHOST_CM_ICLKEN_EN_USBHOST, 5);
334 pio_clear_32(&device->cm.usbhost->fclken,
335 USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG |
336 USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5);
337
338 /* Disable interface and function clock for USB TLL */
339 pio_clear_32(&device->cm.core->iclken3,
340 CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5);
341 pio_clear_32(&device->cm.core->fclken3,
342 CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5);
343 }
344}
345
346/** Initialize USB TLL port connections.
347 *
348 * Different modes are on page 3312 of the Manual Figure 22-34.
349 * Select mode than can operate in FS/LS.
350 */
351int amdm37x_usb_tll_init(amdm37x_t *device)
352{
353 /* Check access */
354 if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) {
355 ddf_msg(LVL_ERROR, "USB TLL is not accessible");
356 return EIO;
357 }
358
359 /* Reset USB TLL */
360 pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5);
361 ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset");
362 while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG));
363 ddf_msg(LVL_DEBUG, "USB TLL Reset done.");
364
365 /* Setup idle mode (smart idle) */
366 pio_change_32(&device->tll->sysconfig,
367 TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG |
368 TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5);
369
370 /* Smart idle for UHH */
371 pio_change_32(&device->uhh->sysconfig,
372 UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG |
373 UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
374
375 /* Set all ports to go through TLL(UTMI)
376 * Direct connection can only work in HS mode */
377 pio_set_32(&device->uhh->hostconfig,
378 UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
379 UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG |
380 UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5);
381
382 /* What is this? */
383 pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5);
384
385 for (unsigned i = 0; i < 3; ++i) {
386 /* Serial mode is the only one capable of FS/LS operation.
387 * Select FS/LS mode, no idea what the difference is
388 * one of bidirectional modes might be good choice
389 * 2 = 3pin bidi phy. */
390 pio_change_32(&device->tll->channel_conf[i],
391 TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |
392 TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY,
393 TLL_CHANNEL_CONF_CHANMODE_MASK |
394 TLL_CHANNEL_CONF_FSLSMODE_MASK, 5);
395 }
396 return EOK;
397}
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