source: mainline/uspace/drv/ehci-hcd/pci.c@ 0f3e68c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0f3e68c was 67352d2, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

Debug output fixes and refactoring (less spam, more readability)
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/**
29 * @addtogroup drvusbehci
30 * @{
31 */
32/**
33 * @file
34 * PCI related functions needed by the EHCI driver.
35 */
36#include <errno.h>
37#include <assert.h>
38#include <as.h>
39#include <devman.h>
40#include <ddi.h>
41#include <libarch/ddi.h>
42#include <device/hw_res.h>
43
44#include <usb/debug.h>
45#include <pci_dev_iface.h>
46
47#include "pci.h"
48
49#define PAGE_SIZE_MASK 0xfffff000
50
51#define HCC_PARAMS_OFFSET 0x8
52#define HCC_PARAMS_EECP_MASK 0xff
53#define HCC_PARAMS_EECP_OFFSET 8
54
55#define CMD_OFFSET 0x0
56#define CONFIGFLAG_OFFSET 0x40
57
58#define USBCMD_RUN 1
59
60#define USBLEGSUP_OFFSET 0
61#define USBLEGSUP_BIOS_CONTROL (1 << 16)
62#define USBLEGSUP_OS_CONTROL (1 << 24)
63#define USBLEGCTLSTS_OFFSET 4
64
65#define DEFAULT_WAIT 10000
66#define WAIT_STEP 10
67
68/** Get address of registers and IRQ for given device.
69 *
70 * @param[in] dev Device asking for the addresses.
71 * @param[out] mem_reg_address Base address of the memory range.
72 * @param[out] mem_reg_size Size of the memory range.
73 * @param[out] irq_no IRQ assigned to the device.
74 * @return Error code.
75 */
76int pci_get_my_registers(ddf_dev_t *dev,
77 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no)
78{
79 assert(dev != NULL);
80
81 int parent_phone = devman_parent_device_connect(dev->handle,
82 IPC_FLAG_BLOCKING);
83 if (parent_phone < 0) {
84 return parent_phone;
85 }
86
87 int rc;
88
89 hw_resource_list_t hw_resources;
90 rc = hw_res_get_resource_list(parent_phone, &hw_resources);
91 if (rc != EOK) {
92 async_hangup(parent_phone);
93 return rc;
94 }
95
96 uintptr_t mem_address = 0;
97 size_t mem_size = 0;
98 bool mem_found = false;
99
100 int irq = 0;
101 bool irq_found = false;
102
103 size_t i;
104 for (i = 0; i < hw_resources.count; i++) {
105 hw_resource_t *res = &hw_resources.resources[i];
106 switch (res->type)
107 {
108 case INTERRUPT:
109 irq = res->res.interrupt.irq;
110 irq_found = true;
111 usb_log_debug2("Found interrupt: %d.\n", irq);
112 break;
113
114 case MEM_RANGE:
115 if (res->res.mem_range.address != 0
116 && res->res.mem_range.size != 0 ) {
117 mem_address = res->res.mem_range.address;
118 mem_size = res->res.mem_range.size;
119 usb_log_debug2("Found mem: %llx %zu.\n",
120 mem_address, mem_size);
121 mem_found = true;
122 }
123 default:
124 break;
125 }
126 }
127
128 if (mem_found && irq_found) {
129 *mem_reg_address = mem_address;
130 *mem_reg_size = mem_size;
131 *irq_no = irq;
132 rc = EOK;
133 } else {
134 rc = ENOENT;
135 }
136
137 async_hangup(parent_phone);
138 return rc;
139}
140/*----------------------------------------------------------------------------*/
141/** Calls the PCI driver with a request to enable interrupts
142 *
143 * @param[in] device Device asking for interrupts
144 * @return Error code.
145 */
146int pci_enable_interrupts(ddf_dev_t *device)
147{
148 int parent_phone =
149 devman_parent_device_connect(device->handle, IPC_FLAG_BLOCKING);
150 if (parent_phone < 0) {
151 return parent_phone;
152 }
153 bool enabled = hw_res_enable_interrupt(parent_phone);
154 async_hangup(parent_phone);
155 return enabled ? EOK : EIO;
156}
157/*----------------------------------------------------------------------------*/
158/** Implements BIOS handoff routine as decribed in EHCI spec
159 *
160 * @param[in] device Device asking for interrupts
161 * @return Error code.
162 */
163int pci_disable_legacy(ddf_dev_t *device)
164{
165 assert(device);
166 int parent_phone = devman_parent_device_connect(device->handle,
167 IPC_FLAG_BLOCKING);
168 if (parent_phone < 0) {
169 return parent_phone;
170 }
171
172#define CHECK_RET_HANGUP_RETURN(ret, message...) \
173 if (ret != EOK) { \
174 usb_log_error(message); \
175 async_hangup(parent_phone); \
176 return ret; \
177 } else (void)0
178
179
180 /* read register space BASE BAR */
181 sysarg_t address = 0x10;
182 sysarg_t value;
183
184 int ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
185 IPC_M_CONFIG_SPACE_READ_32, address, &value);
186 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read PCI config space.\n",
187 ret);
188 usb_log_info("Register space BAR at %p:%x.\n", address, value);
189
190 /* clear lower byte, it's not part of the BASE address */
191 uintptr_t registers = (value & 0xffffff00);
192 usb_log_info("Memory registers BASE address:%p.\n", registers);
193
194 /* if nothing setup the hc, we don't need to turn it off */
195 if (registers == 0)
196 return ENOTSUP;
197
198 /* map EHCI registers */
199 void *regs = as_get_mappable_page(4096);
200 ret = physmem_map((void*)(registers & PAGE_SIZE_MASK), regs, 1,
201 AS_AREA_READ | AS_AREA_WRITE);
202 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to map registers %p:%p.\n",
203 ret, regs, registers);
204
205 /* calculate value of BASE */
206 registers = (registers & 0xf00) | (uintptr_t)regs;
207
208 const uint32_t hcc_params =
209 *(uint32_t*)(registers + HCC_PARAMS_OFFSET);
210 usb_log_debug("Value of hcc params register: %x.\n", hcc_params);
211
212 /* Read value of EHCI Extended Capabilities Pointer
213 * (points to PCI config space) */
214 uint32_t eecp =
215 (hcc_params >> HCC_PARAMS_EECP_OFFSET) & HCC_PARAMS_EECP_MASK;
216 usb_log_debug("Value of EECP: %x.\n", eecp);
217
218 /* Read the second EEC. i.e. Legacy Support and Control register */
219 /* TODO: Check capability type here */
220 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
221 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
222 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGCTLSTS.\n", ret);
223 usb_log_debug("USBLEGCTLSTS: %x.\n", value);
224
225 /* Read the first EEC. i.e. Legacy Support register */
226 /* TODO: Check capability type here */
227 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
228 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
229 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
230 usb_log_debug2("USBLEGSUP: %x.\n", value);
231
232 /* Request control from firmware/BIOS, by writing 1 to highest byte.
233 * (OS Control semaphore)*/
234 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
235 IPC_M_CONFIG_SPACE_WRITE_8, eecp + USBLEGSUP_OFFSET + 3, 1);
236 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to request OS EHCI control.\n",
237 ret);
238
239 size_t wait = 0;
240 /* Wait for BIOS to release control. */
241 while ((wait < DEFAULT_WAIT) && (value & USBLEGSUP_BIOS_CONTROL)) {
242 async_usleep(WAIT_STEP);
243 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
244 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
245 wait += WAIT_STEP;
246 }
247
248
249 if ((value & USBLEGSUP_BIOS_CONTROL) == 0) {
250 usb_log_info("BIOS released control after %d usec.\n", wait);
251 } else {
252 /* BIOS failed to hand over control, this should not happen. */
253 usb_log_warning( "BIOS failed to release control after "
254 "%d usecs, force it.\n", wait);
255 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
256 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGSUP_OFFSET,
257 USBLEGSUP_OS_CONTROL);
258 CHECK_RET_HANGUP_RETURN(ret,
259 "Failed(%d) to force OS EHCI control.\n", ret);
260 }
261
262 /* Zero SMI enables in legacy control register.
263 * It would prevent pre-OS code from interfering. */
264 ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
265 IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET, 0);
266 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) zero USBLEGCTLSTS.\n", ret);
267 usb_log_debug("Zeroed USBLEGCTLSTS register.\n");
268
269 /* Read again Legacy Support and Control register */
270 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
271 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGCTLSTS_OFFSET, &value);
272 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGCTLSTS.\n", ret);
273 usb_log_debug2("USBLEGCTLSTS: %x.\n", value);
274
275 /* Read again Legacy Support register */
276 ret = async_req_2_1(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
277 IPC_M_CONFIG_SPACE_READ_32, eecp + USBLEGSUP_OFFSET, &value);
278 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) to read USBLEGSUP.\n", ret);
279 usb_log_debug2("USBLEGSUP: %x.\n", value);
280
281 /*
282 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT
283 */
284
285 /* Get size of capability registers in memory space. */
286 uint8_t operation_offset = *(uint8_t*)registers;
287 usb_log_debug("USBCMD offset: %d.\n", operation_offset);
288
289 /* Zero USBCMD register. */
290 volatile uint32_t *usbcmd =
291 (uint32_t*)((uint8_t*)registers + operation_offset + CMD_OFFSET);
292 volatile uint32_t *usbconfigured =
293 (uint32_t*)((uint8_t*)registers + operation_offset
294 + CONFIGFLAG_OFFSET);
295 usb_log_debug("USBCMD value: %x.\n", *usbcmd);
296 if (*usbcmd & USBCMD_RUN) {
297 *usbcmd = 0;
298 *usbconfigured = 0;
299 usb_log_info("EHCI turned off.\n");
300 } else {
301 usb_log_info("EHCI was not running.\n");
302 }
303
304 async_hangup(parent_phone);
305 return ret;
306#undef CHECK_RET_HANGUP_RETURN
307}
308/*----------------------------------------------------------------------------*/
309/**
310 * @}
311 */
312
313/**
314 * @}
315 */
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