source: mainline/uspace/drv/char/pl050/pl050.c

Last change on this file was 60744cb, checked in by Jiri Svoboda <jiri@…>, 14 months ago

Let driver specify any argument to IRQ handler

This allows the driver to register a single handler for multiple
interrupts and still distinguish between them. It also removes
the extra step of having to get softstate from ddf_dev_t.

  • Property mode set to 100644
File size: 9.3 KB
RevLine 
[312e5ff]1/*
2 * Copyright (c) 2009 Vineeth Pillai
3 * Copyright (c) 2014 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[c8ea6eca]30/** @addtogroup pl050
31 * @{
32 */
33
[312e5ff]34/** @file
35 */
36
37#include <assert.h>
[75fe97b]38#include <bitops.h>
[312e5ff]39#include <stdio.h>
40#include <errno.h>
[c1694b6b]41#include <str_error.h>
[312e5ff]42#include <ddf/driver.h>
43#include <ddf/interrupt.h>
44#include <ddf/log.h>
[d51838f]45#include <device/hw_res.h>
[312e5ff]46#include <device/hw_res_parsed.h>
[75751db6]47#include <io/chardev_srv.h>
[312e5ff]48
[75fe97b]49#include "pl050_hw.h"
[312e5ff]50
[75fe97b]51#define NAME "pl050"
[312e5ff]52
53enum {
54 buffer_size = 64
55};
56
[b7fd2a0]57static errno_t pl050_dev_add(ddf_dev_t *);
58static errno_t pl050_fun_online(ddf_fun_t *);
59static errno_t pl050_fun_offline(ddf_fun_t *);
[984a9ba]60static void pl050_char_conn(ipc_call_t *, void *);
[f2d88f3]61static errno_t pl050_read(chardev_srv_t *, void *, size_t, size_t *,
62 chardev_flags_t);
[b7fd2a0]63static errno_t pl050_write(chardev_srv_t *, const void *, size_t, size_t *);
[312e5ff]64
65static driver_ops_t driver_ops = {
66 .dev_add = &pl050_dev_add,
67 .fun_online = &pl050_fun_online,
68 .fun_offline = &pl050_fun_offline
69};
70
71static driver_t pl050_driver = {
72 .name = NAME,
73 .driver_ops = &driver_ops
74};
75
[75751db6]76static chardev_ops_t pl050_chardev_ops = {
77 .read = pl050_read,
78 .write = pl050_write
79};
80
[312e5ff]81typedef struct {
[75751db6]82 async_sess_t *parent_sess;
[312e5ff]83 ddf_dev_t *dev;
[75fe97b]84 char *name;
[75751db6]85
[312e5ff]86 ddf_fun_t *fun_a;
[75751db6]87 chardev_srvs_t cds;
88
[312e5ff]89 uintptr_t iobase;
90 size_t iosize;
[75fe97b]91 kmi_regs_t *regs;
[312e5ff]92 uint8_t buffer[buffer_size];
93 size_t buf_rp;
94 size_t buf_wp;
95 fibril_condvar_t buf_cv;
96 fibril_mutex_t buf_lock;
97} pl050_t;
98
99static irq_pio_range_t pl050_ranges[] = {
100 {
101 .base = 0,
102 .size = 9,
103 }
104};
105
106static irq_cmd_t pl050_cmds[] = {
107 {
108 .cmd = CMD_PIO_READ_8,
109 .addr = NULL,
110 .dstarg = 1
111 },
112 {
113 .cmd = CMD_AND,
[75fe97b]114 .value = BIT_V(uint8_t, kmi_stat_rxfull),
[312e5ff]115 .srcarg = 1,
116 .dstarg = 3
117 },
118 {
119 .cmd = CMD_PREDICATE,
120 .value = 2,
121 .srcarg = 3
122 },
123 {
124 .cmd = CMD_PIO_READ_8,
125 .addr = NULL, /* Will be patched in run-time */
126 .dstarg = 2
127 },
128 {
129 .cmd = CMD_ACCEPT
130 }
131};
132
133static irq_code_t pl050_irq_code = {
134 sizeof(pl050_ranges) / sizeof(irq_pio_range_t),
135 pl050_ranges,
136 sizeof(pl050_cmds) / sizeof(irq_cmd_t),
137 pl050_cmds
138};
139
140static pl050_t *pl050_from_fun(ddf_fun_t *fun)
141{
142 return (pl050_t *)ddf_dev_data_get(ddf_fun_get_dev(fun));
143}
144
[60744cb]145/** PL050 interrupt handler
146 *
147 * @param call IRQ event notification
148 * @param arg Argument (pl050_t *)
149 */
150static void pl050_interrupt(ipc_call_t *call, void *arg)
[312e5ff]151{
[60744cb]152 pl050_t *pl050 = (pl050_t *)arg;
[312e5ff]153 size_t nidx;
154
155 fibril_mutex_lock(&pl050->buf_lock);
156 nidx = (pl050->buf_wp + 1) % buffer_size;
157 if (nidx == pl050->buf_rp) {
158 /** Buffer overrunt */
159 ddf_msg(LVL_WARN, "Buffer overrun.");
160 fibril_mutex_unlock(&pl050->buf_lock);
161 return;
162 }
163
[fafb8e5]164 pl050->buffer[pl050->buf_wp] = ipc_get_arg2(call);
[312e5ff]165 pl050->buf_wp = nidx;
166 fibril_condvar_broadcast(&pl050->buf_cv);
167 fibril_mutex_unlock(&pl050->buf_lock);
168}
169
[b7fd2a0]170static errno_t pl050_init(pl050_t *pl050)
[312e5ff]171{
172 hw_res_list_parsed_t res;
[75fe97b]173 void *regs;
[b7fd2a0]174 errno_t rc;
[312e5ff]175
176 fibril_mutex_initialize(&pl050->buf_lock);
177 fibril_condvar_initialize(&pl050->buf_cv);
178 pl050->buf_rp = pl050->buf_wp = 0;
179
[2fd26bb]180 pl050->parent_sess = ddf_dev_parent_sess_get(pl050->dev);
[312e5ff]181 if (pl050->parent_sess == NULL) {
182 ddf_msg(LVL_ERROR, "Failed connecitng parent driver.");
183 rc = ENOMEM;
184 goto error;
185 }
186
187 hw_res_list_parsed_init(&res);
188 rc = hw_res_get_list_parsed(pl050->parent_sess, &res, 0);
189 if (rc != EOK) {
190 ddf_msg(LVL_ERROR, "Failed getting resource list.");
191 goto error;
192 }
193
194 if (res.mem_ranges.count != 1) {
195 ddf_msg(LVL_ERROR, "Expected exactly one memory range.");
196 rc = EINVAL;
197 goto error;
198 }
199
200 pl050->iobase = RNGABS(res.mem_ranges.ranges[0]);
201 pl050->iosize = RNGSZ(res.mem_ranges.ranges[0]);
202
203 pl050_irq_code.ranges[0].base = pl050->iobase;
[75fe97b]204 kmi_regs_t *regsphys = (kmi_regs_t *) pl050->iobase;
205 pl050_irq_code.cmds[0].addr = &regsphys->stat;
206 pl050_irq_code.cmds[3].addr = &regsphys->data;
[312e5ff]207
208 if (res.irqs.count != 1) {
209 ddf_msg(LVL_ERROR, "Expected exactly one IRQ.");
210 rc = EINVAL;
211 goto error;
212 }
213
214 ddf_msg(LVL_DEBUG, "iobase=%p irq=%d", (void *)pl050->iobase,
215 res.irqs.irqs[0]);
216
[75fe97b]217 rc = pio_enable((void *)pl050->iobase, sizeof(kmi_regs_t), &regs);
218 if (rc != EOK) {
219 ddf_msg(LVL_ERROR, "Error enabling PIO");
220 goto error;
221 }
222
223 pl050->regs = regs;
224
[eadaeae8]225 cap_irq_handle_t ihandle;
[071a1ddb]226 rc = register_interrupt_handler(pl050->dev,
[60744cb]227 res.irqs.irqs[0], pl050_interrupt, (void *)pl050, &pl050_irq_code,
228 &ihandle);
[071a1ddb]229 if (rc != EOK) {
[dd8ab1c]230 ddf_msg(LVL_ERROR, "Failed registering interrupt handler. (%s)",
231 str_error_name(rc));
[312e5ff]232 goto error;
233 }
234
[d51838f]235 rc = hw_res_enable_interrupt(pl050->parent_sess, res.irqs.irqs[0]);
[75fe97b]236 if (rc != EOK) {
[c1694b6b]237 ddf_msg(LVL_ERROR, "Failed enabling interrupt: %s", str_error(rc));
[75fe97b]238 goto error;
239 }
240
241 pio_write_8(&pl050->regs->cr,
242 BIT_V(uint8_t, kmi_cr_enable) |
243 BIT_V(uint8_t, kmi_cr_rxintr));
244
[312e5ff]245 return EOK;
246error:
247 return rc;
248}
249
[b7fd2a0]250static errno_t pl050_read(chardev_srv_t *srv, void *buffer, size_t size,
[f2d88f3]251 size_t *nread, chardev_flags_t flags)
[312e5ff]252{
[75751db6]253 pl050_t *pl050 = (pl050_t *)srv->srvs->sarg;
[312e5ff]254 uint8_t *bp = buffer;
[75751db6]255 size_t left;
[75fe97b]256
[312e5ff]257 fibril_mutex_lock(&pl050->buf_lock);
258
[75751db6]259 left = size;
260 while (left > 0) {
[f2d88f3]261 while ((flags & chardev_f_nonblock) == 0 &&
262 left == size && pl050->buf_rp == pl050->buf_wp)
[312e5ff]263 fibril_condvar_wait(&pl050->buf_cv, &pl050->buf_lock);
[c657bd7]264 if (pl050->buf_rp == pl050->buf_wp)
265 break;
[312e5ff]266 *bp++ = pl050->buffer[pl050->buf_rp];
[75751db6]267 --left;
[312e5ff]268 pl050->buf_rp = (pl050->buf_rp + 1) % buffer_size;
269 }
270
271 fibril_mutex_unlock(&pl050->buf_lock);
272
[677cad5]273 *nread = size - left;
274 return EOK;
[312e5ff]275}
276
[b7fd2a0]277static errno_t pl050_write(chardev_srv_t *srv, const void *data, size_t size,
[677cad5]278 size_t *nwritten)
[312e5ff]279{
[75fe97b]280 pl050_t *pl050 = (pl050_t *)srv->srvs->sarg;
281 uint8_t *dp = (uint8_t *)data;
282 uint8_t status;
283 size_t i;
284
285 ddf_msg(LVL_NOTE, "%s/pl050_write(%zu bytes)", pl050->name, size);
286 for (i = 0; i < size; i++) {
287 while (true) {
288 status = pio_read_8(&pl050->regs->stat);
289 if ((status & BIT_V(uint8_t, kmi_stat_txempty)) != 0)
290 break;
291 }
292 pio_write_8(&pl050->regs->data, dp[i]);
293 }
294 ddf_msg(LVL_NOTE, "%s/pl050_write() success", pl050->name);
295
[677cad5]296 *nwritten = size;
297 return EOK;
[312e5ff]298}
299
[984a9ba]300void pl050_char_conn(ipc_call_t *icall, void *arg)
[312e5ff]301{
302 pl050_t *pl050 = pl050_from_fun((ddf_fun_t *)arg);
303
[984a9ba]304 chardev_conn(icall, &pl050->cds);
[312e5ff]305}
306
307/** Add device. */
[b7fd2a0]308static errno_t pl050_dev_add(ddf_dev_t *dev)
[312e5ff]309{
310 ddf_fun_t *fun_a;
[75fe97b]311 pl050_t *pl050 = NULL;
312 const char *mname;
[b7fd2a0]313 errno_t rc;
[312e5ff]314
[af0a2c7]315 ddf_msg(LVL_DEBUG, "pl050_dev_add()");
[312e5ff]316
317 pl050 = ddf_dev_data_alloc(dev, sizeof(pl050_t));
318 if (pl050 == NULL) {
319 ddf_msg(LVL_ERROR, "Failed allocating soft state.\n");
320 rc = ENOMEM;
321 goto error;
322 }
323
[75fe97b]324 pl050->name = (char *)ddf_dev_get_name(dev);
325 if (pl050->name == NULL) {
326 rc = ENOMEM;
327 goto error;
328 }
329
[312e5ff]330 fun_a = ddf_fun_create(dev, fun_inner, "a");
331 if (fun_a == NULL) {
332 ddf_msg(LVL_ERROR, "Failed creating function 'a'.");
333 rc = ENOMEM;
334 goto error;
335 }
336
337 pl050->fun_a = fun_a;
338 pl050->dev = dev;
339
340 rc = pl050_init(pl050);
341 if (rc != EOK)
342 goto error;
[af0a2c7]343
[75fe97b]344 if (str_cmp(pl050->name, "kbd") == 0)
[5012203]345 mname = "char/atkbd";
[75fe97b]346 else
347 mname = "char/ps2mouse";
348
349 rc = ddf_fun_add_match_id(fun_a, mname, 10);
[312e5ff]350 if (rc != EOK) {
351 ddf_msg(LVL_ERROR, "Failed adding match IDs to function %s",
352 "char/xtkbd");
353 goto error;
354 }
355
[75751db6]356 chardev_srvs_init(&pl050->cds);
357 pl050->cds.ops = &pl050_chardev_ops;
358 pl050->cds.sarg = pl050;
[312e5ff]359
[75751db6]360 ddf_fun_set_conn_handler(fun_a, pl050_char_conn);
[af0a2c7]361
[312e5ff]362 rc = ddf_fun_bind(fun_a);
363 if (rc != EOK) {
[c1694b6b]364 ddf_msg(LVL_ERROR, "Failed binding function 'a': %s", str_error(rc));
[312e5ff]365 ddf_fun_destroy(fun_a);
366 goto error;
367 }
368
369 ddf_msg(LVL_DEBUG, "Device added.");
370 return EOK;
371error:
[75fe97b]372 if (pl050 != NULL)
373 free(pl050->name);
[312e5ff]374 return rc;
375}
376
[b7fd2a0]377static errno_t pl050_fun_online(ddf_fun_t *fun)
[312e5ff]378{
379 ddf_msg(LVL_DEBUG, "pl050_fun_online()");
380 return ddf_fun_online(fun);
381}
382
[b7fd2a0]383static errno_t pl050_fun_offline(ddf_fun_t *fun)
[312e5ff]384{
385 ddf_msg(LVL_DEBUG, "pl050_fun_offline()");
386 return ddf_fun_offline(fun);
387}
388
389int main(int argc, char *argv[])
390{
[b7fd2a0]391 errno_t rc;
[312e5ff]392
393 printf(NAME ": HelenOS pl050 serial device driver\n");
394 rc = ddf_log_init(NAME);
395 if (rc != EOK) {
396 printf(NAME ": Error connecting logging service.");
397 return 1;
398 }
399
400 return ddf_driver_main(&pl050_driver);
401}
402
[c8ea6eca]403/** @}
404 */
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