1 | /*
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2 | * Copyright (c) 2017 Michal Staruch
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup drvusbxhci
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30 | * @{
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31 | */
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32 | /** @file
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33 | * @brief The host controller transfer ring management
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34 | */
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35 |
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36 | #include <usb/host/utils/malloc32.h>
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37 | #include <usb/debug.h>
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38 | #include "endpoint.h"
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39 | #include "hc.h"
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40 | #include "hw_struct/trb.h"
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41 | #include "transfers.h"
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42 | #include "trb_ring.h"
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43 |
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44 | static inline uint8_t get_transfer_type(xhci_trb_t* trb, uint8_t bmRequestType, uint16_t wLength)
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45 | {
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46 | /* See Table 7 of xHCI specification */
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47 | if (bmRequestType & 0x80) {
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48 | /* Device-to-host transfer */
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49 | if (wLength) {
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50 | /* IN data stage */
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51 | return 3;
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52 | }
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53 | else {
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54 | /* No data stage */
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55 | return 0;
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56 | }
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57 | }
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58 | else {
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59 | /* Host-to-device transfer */
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60 | if (wLength) {
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61 | /* OUT data stage */
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62 | return 2;
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63 | }
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64 | else {
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65 | /* No data stage */
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66 | return 0;
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67 | }
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68 | }
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69 | }
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70 |
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71 | static inline uint8_t get_data_direction(xhci_trb_t* trb, uint8_t bmRequestType, uint16_t wLength)
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72 | {
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73 | /* See Table 7 of xHCI specification */
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74 | if (bmRequestType & 0x80) {
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75 | /* Device-to-host transfer */
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76 | return 1;
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77 | }
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78 | else {
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79 | /* Host-to-device transfer */
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80 | return 0;
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81 | }
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82 | }
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83 |
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84 | static inline uint8_t get_status_direction(xhci_trb_t* trb, uint8_t bmRequestType, uint16_t wLength)
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85 | {
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86 | /* See Table 7 of xHCI specification */
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87 | if (bmRequestType & 0x80) {
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88 | /* Device-to-host transfer */
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89 | if (wLength) {
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90 | /* Out direction */
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91 | return 0;
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92 | }
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93 | else {
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94 | /* In direction */
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95 | return 1;
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96 | }
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97 | }
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98 | else {
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99 | /* Host-to-device transfer, always IN direction */
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100 | return 1;
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101 | }
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102 | }
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103 |
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104 | int xhci_init_transfers(xhci_hc_t *hc)
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105 | {
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106 | assert(hc);
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107 |
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108 | list_initialize(&hc->transfers);
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109 | return EOK;
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110 | }
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111 |
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112 | void xhci_fini_transfers(xhci_hc_t *hc)
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113 | {
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114 | // Note: Untested.
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115 | assert(hc);
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116 | }
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117 |
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118 | xhci_transfer_t* xhci_transfer_alloc(usb_transfer_batch_t* batch) {
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119 | xhci_transfer_t* transfer = malloc(sizeof(xhci_transfer_t));
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120 | if (!transfer)
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121 | return NULL;
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122 |
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123 | memset(transfer, 0, sizeof(xhci_transfer_t));
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124 | transfer->batch = batch;
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125 | link_initialize(&transfer->link);
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126 | transfer->hc_buffer = malloc32(batch->buffer_size);
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127 |
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128 | return transfer;
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129 | }
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130 |
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131 | void xhci_transfer_fini(xhci_transfer_t* transfer) {
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132 | if (transfer) {
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133 | free32(transfer->hc_buffer);
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134 | free(transfer);
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135 | }
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136 | }
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137 |
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138 | int xhci_schedule_control_transfer(xhci_hc_t* hc, usb_transfer_batch_t* batch)
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139 | {
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140 | if (!batch->setup_size) {
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141 | usb_log_error("Missing setup packet for the control transfer.");
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142 | return EINVAL;
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143 | }
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144 | if (batch->ep->target.endpoint != 0 || batch->ep->transfer_type != USB_TRANSFER_CONTROL) {
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145 | /* This method only works for control transfers. */
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146 | usb_log_error("Attempted to schedule control transfer to non 0 endpoint.");
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147 | return EINVAL;
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148 | }
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149 |
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150 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(batch->ep);
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151 |
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152 | uint8_t slot_id = xhci_ep->slot_id;
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153 | xhci_trb_ring_t* ring = hc->dcbaa_virt[slot_id].trs[0];
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154 |
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155 | usb_device_request_setup_packet_t* setup =
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156 | (usb_device_request_setup_packet_t*) batch->setup_buffer;
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157 |
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158 | /* For the TRB formats, see xHCI specification 6.4.1.2 */
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159 | xhci_transfer_t *transfer = xhci_transfer_alloc(batch);
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160 | memcpy(transfer->hc_buffer, batch->buffer, batch->buffer_size);
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161 |
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162 | xhci_trb_t trb_setup;
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163 | memset(&trb_setup, 0, sizeof(xhci_trb_t));
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164 |
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165 | TRB_CTRL_SET_SETUP_WVALUE(trb_setup, setup->value);
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166 | TRB_CTRL_SET_SETUP_WLENGTH(trb_setup, setup->length);
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167 | TRB_CTRL_SET_SETUP_WINDEX(trb_setup, setup->index);
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168 | TRB_CTRL_SET_SETUP_BREQ(trb_setup, setup->request);
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169 | TRB_CTRL_SET_SETUP_BMREQTYPE(trb_setup, setup->request_type);
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170 |
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171 | /* Size of the setup packet is always 8 */
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172 | TRB_CTRL_SET_XFER_LEN(trb_setup, 8);
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173 | // if we want an interrupt after this td is done, use
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174 | // TRB_CTRL_SET_IOC(trb_setup, 1);
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175 |
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176 | /* Immediate data */
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177 | TRB_CTRL_SET_IDT(trb_setup, 1);
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178 | TRB_CTRL_SET_TRB_TYPE(trb_setup, XHCI_TRB_TYPE_SETUP_STAGE);
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179 | TRB_CTRL_SET_TRT(trb_setup, get_transfer_type(&trb_setup, setup->request_type, setup->length));
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180 |
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181 | /* Data stage */
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182 | xhci_trb_t trb_data;
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183 | memset(&trb_data, 0, sizeof(xhci_trb_t));
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184 |
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185 | if (setup->length > 0) {
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186 | trb_data.parameter = addr_to_phys(transfer->hc_buffer);
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187 |
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188 | // data size (sent for OUT, or buffer size)
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189 | TRB_CTRL_SET_XFER_LEN(trb_data, batch->buffer_size);
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190 | // FIXME: TD size 4.11.2.4
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191 | TRB_CTRL_SET_TD_SIZE(trb_data, 1);
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192 |
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193 | // if we want an interrupt after this td is done, use
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194 | // TRB_CTRL_SET_IOC(trb_data, 1);
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195 |
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196 | // Some more fields here, no idea what they mean
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197 | TRB_CTRL_SET_TRB_TYPE(trb_data, XHCI_TRB_TYPE_DATA_STAGE);
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198 |
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199 | transfer->direction = get_data_direction(&trb_setup, setup->request_type, setup->length);
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200 | TRB_CTRL_SET_DIR(trb_data, transfer->direction);
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201 | }
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202 |
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203 | /* Status stage */
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204 | xhci_trb_t trb_status;
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205 | memset(&trb_status, 0, sizeof(xhci_trb_t));
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206 |
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207 | // FIXME: Evaluate next TRB? 4.12.3
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208 | // TRB_CTRL_SET_ENT(trb_status, 1);
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209 |
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210 | // if we want an interrupt after this td is done, use
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211 | TRB_CTRL_SET_IOC(trb_status, 1);
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212 |
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213 | TRB_CTRL_SET_TRB_TYPE(trb_status, XHCI_TRB_TYPE_STATUS_STAGE);
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214 | TRB_CTRL_SET_DIR(trb_status, get_status_direction(&trb_setup, setup->request_type, setup->length));
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215 |
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216 | uintptr_t dummy = 0;
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217 | xhci_trb_ring_enqueue(ring, &trb_setup, &dummy);
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218 | if (setup->length > 0) {
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219 | xhci_trb_ring_enqueue(ring, &trb_data, &dummy);
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220 | }
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221 | xhci_trb_ring_enqueue(ring, &trb_status, &transfer->interrupt_trb_phys);
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222 |
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223 | list_append(&transfer->link, &hc->transfers);
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224 |
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225 | /* For control transfers, the target is always 1. */
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226 | hc_ring_doorbell(hc, slot_id, 1);
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227 | return EOK;
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228 | }
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229 |
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230 | int xhci_schedule_bulk_transfer(xhci_hc_t* hc, usb_transfer_batch_t* batch) {
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231 | if (batch->setup_size) {
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232 | usb_log_warning("Setup packet present for a bulk transfer.");
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233 | }
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234 |
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235 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(batch->ep);
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236 | uint8_t slot_id = xhci_ep->slot_id;
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237 | xhci_trb_ring_t* ring = hc->dcbaa_virt[slot_id].trs[batch->ep->target.endpoint];
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238 |
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239 | xhci_transfer_t *transfer = xhci_transfer_alloc(batch);
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240 | memcpy(transfer->hc_buffer, batch->buffer, batch->buffer_size);
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241 |
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242 | xhci_trb_t trb;
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243 | memset(&trb, 0, sizeof(xhci_trb_t));
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244 | trb.parameter = addr_to_phys(transfer->hc_buffer);
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245 |
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246 | // data size (sent for OUT, or buffer size)
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247 | TRB_CTRL_SET_XFER_LEN(trb, batch->buffer_size);
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248 | // FIXME: TD size 4.11.2.4
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249 | TRB_CTRL_SET_TD_SIZE(trb, 1);
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250 |
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251 | // we want an interrupt after this td is done
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252 | TRB_CTRL_SET_IOC(trb, 1);
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253 |
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254 | TRB_CTRL_SET_TRB_TYPE(trb, XHCI_TRB_TYPE_NORMAL);
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255 |
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256 | xhci_trb_ring_enqueue(ring, &trb, &transfer->interrupt_trb_phys);
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257 | list_append(&transfer->link, &hc->transfers);
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258 |
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259 | // TODO: target = endpoint | stream_id << 16
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260 | hc_ring_doorbell(hc, slot_id, xhci_ep->base->target->endpoint);
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261 | return EOK;
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262 | }
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263 |
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264 | int xhci_handle_transfer_event(xhci_hc_t* hc, xhci_trb_t* trb)
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265 | {
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266 | uintptr_t addr = trb->parameter;
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267 | xhci_transfer_t *transfer = NULL;
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268 |
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269 | link_t *transfer_link = list_first(&hc->transfers);
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270 | while (transfer_link) {
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271 | transfer = list_get_instance(transfer_link, xhci_transfer_t, link);
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272 |
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273 | if (transfer->interrupt_trb_phys == addr)
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274 | break;
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275 |
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276 | transfer_link = list_next(transfer_link, &hc->transfers);
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277 | }
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278 |
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279 | if (!transfer_link) {
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280 | usb_log_warning("Transfer not found.");
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281 | return ENOENT;
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282 | }
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283 |
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284 | list_remove(transfer_link);
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285 | usb_transfer_batch_t *batch = transfer->batch;
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286 |
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287 | batch->error = (TRB_COMPLETION_CODE(*trb) == XHCI_TRBC_SUCCESS) ? EOK : ENAK;
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288 | batch->transfered_size = batch->buffer_size - TRB_TRANSFER_LENGTH(*trb);
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289 | if (transfer->direction) {
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290 | /* Device-to-host, IN */
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291 | if (batch->callback_in)
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292 | batch->callback_in(batch->error, batch->transfered_size, batch->arg);
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293 | }
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294 | else {
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295 | /* Host-to-device, OUT */
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296 | if (batch->callback_out)
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297 | batch->callback_out(batch->error, batch->arg);
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298 | }
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299 |
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300 | xhci_transfer_fini(transfer);
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301 | return EOK;
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302 | }
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