1 | /*
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2 | * Copyright (c) 2018 Michal Staruch, Ondrej Hlavaty, Petr Manek, Jan Hrach
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 |
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29 | /** @addtogroup drvusbxhci
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30 | * @{
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31 | */
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32 | /** @file
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33 | * @brief The host controller transfer ring management
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34 | */
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35 |
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36 | #include <usb/debug.h>
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37 | #include <usb/request.h>
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38 | #include "endpoint.h"
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39 | #include "hc.h"
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40 | #include "hw_struct/trb.h"
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41 | #include "streams.h"
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42 | #include "transfers.h"
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43 | #include "trb_ring.h"
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44 |
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45 | typedef enum {
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46 | STAGE_OUT,
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47 | STAGE_IN,
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48 | } stage_dir_flag_t;
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49 |
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50 | /** Get direction flag of data stage.
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51 | * See Table 7 of xHCI specification.
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52 | */
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53 | static inline stage_dir_flag_t get_status_direction_flag(xhci_trb_t *trb,
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54 | uint8_t bmRequestType, uint16_t wLength)
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55 | {
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56 | /* See Table 7 of xHCI specification */
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57 | return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) && (wLength > 0) ?
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58 | STAGE_OUT :
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59 | STAGE_IN;
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60 | }
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61 |
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62 | typedef enum {
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63 | DATA_STAGE_NO = 0,
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64 | DATA_STAGE_OUT = 2,
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65 | DATA_STAGE_IN = 3,
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66 | } data_stage_type_t;
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67 |
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68 | /** Get transfer type flag.
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69 | * See Table 8 of xHCI specification.
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70 | */
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71 | static inline data_stage_type_t get_transfer_type(xhci_trb_t *trb, uint8_t
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72 | bmRequestType, uint16_t wLength)
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73 | {
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74 | if (wLength == 0)
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75 | return DATA_STAGE_NO;
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76 |
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77 | /* See Table 7 of xHCI specification */
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78 | return SETUP_REQUEST_TYPE_IS_DEVICE_TO_HOST(bmRequestType) ?
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79 | DATA_STAGE_IN :
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80 | DATA_STAGE_NO;
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81 | }
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82 |
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83 | static inline bool configure_endpoint_needed(usb_device_request_setup_packet_t *setup)
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84 | {
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85 | usb_request_type_t request_type = SETUP_REQUEST_TYPE_GET_TYPE(setup->request_type);
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86 |
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87 | return request_type == USB_REQUEST_TYPE_STANDARD &&
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88 | (setup->request == USB_DEVREQ_SET_CONFIGURATION ||
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89 | setup->request == USB_DEVREQ_SET_INTERFACE);
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90 | }
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91 |
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92 | /**
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93 | * Create a xHCI-specific transfer batch.
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94 | *
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95 | * Bus callback.
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96 | */
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97 | usb_transfer_batch_t *xhci_transfer_create(endpoint_t *ep)
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98 | {
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99 | xhci_transfer_t *transfer = calloc(1, sizeof(xhci_transfer_t));
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100 | if (!transfer)
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101 | return NULL;
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102 |
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103 | usb_transfer_batch_init(&transfer->batch, ep);
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104 | return &transfer->batch;
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105 | }
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106 |
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107 | /**
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108 | * Destroy a xHCI transfer.
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109 | */
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110 | void xhci_transfer_destroy(usb_transfer_batch_t *batch)
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111 | {
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112 | xhci_transfer_t *transfer = xhci_transfer_from_batch(batch);
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113 | free(transfer);
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114 | }
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115 |
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116 | static xhci_trb_ring_t *get_ring(xhci_transfer_t *transfer)
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117 | {
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118 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(transfer->batch.ep);
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119 | return xhci_endpoint_get_ring(xhci_ep, transfer->batch.target.stream);
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120 | }
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121 |
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122 | #define MAX_CHUNK_SIZE (1 << 16)
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123 |
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124 | typedef struct {
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125 | /* Input parameters */
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126 | dma_buffer_t buf;
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127 | size_t chunk_size, packet_count, mps, max_trb_count;
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128 |
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129 | /* Changing at runtime */
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130 | size_t transferred, remaining;
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131 | void *pos;
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132 | } trb_splitter_t;
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133 |
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134 | static void trb_splitter_init(trb_splitter_t *ts, xhci_transfer_t *transfer)
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135 | {
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136 | ts->buf = transfer->batch.dma_buffer;
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137 |
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138 | const size_t chunk_mask = dma_policy_chunk_mask(ts->buf.policy);
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139 | ts->chunk_size = (chunk_mask > MAX_CHUNK_SIZE + 1) ?
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140 | MAX_CHUNK_SIZE : (chunk_mask + 1);
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141 |
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142 | ts->remaining = transfer->batch.size;
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143 | ts->max_trb_count = (ts->remaining + ts->chunk_size - 1) / ts->chunk_size + 1;
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144 | ts->mps = transfer->batch.ep->max_packet_size;
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145 | ts->packet_count = (ts->remaining + ts->mps - 1) / ts->mps;
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146 |
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147 | ts->transferred = 0;
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148 | ts->pos = ts->buf.virt + transfer->batch.offset;
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149 | }
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150 |
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151 | static void trb_split_next(xhci_trb_t *trb, trb_splitter_t *ts)
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152 | {
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153 | xhci_trb_clean(trb);
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154 |
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155 | size_t size = min(ts->remaining, ts->chunk_size);
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156 |
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157 | /* First TRB might be misaligned */
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158 | if (ts->transferred == 0) {
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159 | const size_t offset = (ts->pos - ts->buf.virt) % ts->chunk_size;
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160 | size = min(size, ts->chunk_size - offset);
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161 | }
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162 |
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163 | ts->transferred += size;
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164 | ts->remaining -= size;
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165 |
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166 | const size_t tx_packets = (ts->transferred + ts->mps - 1) / ts->mps;
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167 | const unsigned td_size = min(31, ts->packet_count - tx_packets);
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168 |
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169 | /* Last TRB must have TD Size = 0 */
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170 | assert(ts->remaining > 0 || td_size == 0);
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171 |
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172 | uintptr_t phys = dma_buffer_phys(&ts->buf, ts->pos);
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173 |
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174 | trb->parameter = host2xhci(64, phys);
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175 | TRB_CTRL_SET_TD_SIZE(*trb, td_size);
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176 | TRB_CTRL_SET_XFER_LEN(*trb, size);
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177 | TRB_CTRL_SET_TRB_TYPE(*trb, XHCI_TRB_TYPE_NORMAL);
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178 |
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179 | if (ts->remaining)
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180 | TRB_CTRL_SET_CHAIN(*trb, 1);
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181 |
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182 | ts->pos += size;
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183 | }
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184 |
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185 | static errno_t schedule_control(xhci_hc_t *hc, xhci_transfer_t *transfer)
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186 | {
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187 | usb_transfer_batch_t *batch = &transfer->batch;
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188 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(transfer->batch.ep);
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189 |
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190 | usb_device_request_setup_packet_t *setup = &batch->setup.packet;
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191 |
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192 | trb_splitter_t splitter;
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193 | trb_splitter_init(&splitter, transfer);
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194 |
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195 | xhci_trb_t trbs[splitter.max_trb_count + 2];
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196 | size_t trbs_used = 0;
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197 |
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198 | xhci_trb_t *trb_setup = &trbs[trbs_used++];
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199 | xhci_trb_clean(trb_setup);
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200 |
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201 | trb_setup->parameter = batch->setup.packed;
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202 |
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203 | /* Size of the setup packet is always 8 */
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204 | TRB_CTRL_SET_XFER_LEN(*trb_setup, 8);
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205 |
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206 | /* Immediate data */
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207 | TRB_CTRL_SET_IDT(*trb_setup, 1);
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208 | TRB_CTRL_SET_TRB_TYPE(*trb_setup, XHCI_TRB_TYPE_SETUP_STAGE);
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209 | TRB_CTRL_SET_TRT(*trb_setup,
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210 | get_transfer_type(trb_setup, setup->request_type, setup->length));
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211 |
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212 | stage_dir_flag_t stage_dir = (transfer->batch.dir == USB_DIRECTION_IN) ?
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213 | STAGE_IN : STAGE_OUT;
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214 |
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215 | /* Data stage - first TRB is special */
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216 | if (splitter.remaining > 0) {
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217 | xhci_trb_t *trb = &trbs[trbs_used++];
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218 | trb_split_next(trb, &splitter);
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219 | TRB_CTRL_SET_TRB_TYPE(*trb, XHCI_TRB_TYPE_DATA_STAGE);
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220 | TRB_CTRL_SET_DIR(*trb, stage_dir);
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221 | }
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222 | while (splitter.remaining > 0)
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223 | trb_split_next(&trbs[trbs_used++], &splitter);
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224 |
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225 | /* Status stage */
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226 | xhci_trb_t *trb_status = &trbs[trbs_used++];
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227 | xhci_trb_clean(trb_status);
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228 |
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229 | TRB_CTRL_SET_IOC(*trb_status, 1);
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230 | TRB_CTRL_SET_TRB_TYPE(*trb_status, XHCI_TRB_TYPE_STATUS_STAGE);
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231 | TRB_CTRL_SET_DIR(*trb_status, get_status_direction_flag(trb_setup,
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232 | setup->request_type, setup->length));
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233 |
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234 | // Issue a Configure Endpoint command, if needed.
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235 | if (configure_endpoint_needed(setup)) {
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236 | const errno_t err = hc_configure_device(xhci_ep_to_dev(xhci_ep));
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237 | if (err)
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238 | return err;
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239 | }
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240 |
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241 | return xhci_trb_ring_enqueue_multiple(get_ring(transfer), trbs,
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242 | trbs_used, &transfer->interrupt_trb_phys);
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243 | }
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244 |
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245 | static errno_t schedule_bulk_intr(xhci_hc_t *hc, xhci_transfer_t *transfer)
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246 | {
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247 | xhci_trb_ring_t *const ring = get_ring(transfer);
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248 | if (!ring)
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249 | return EINVAL;
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250 |
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251 | /* The stream-enabled endpoints need to chain ED trb */
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252 | xhci_endpoint_t *ep = xhci_endpoint_get(transfer->batch.ep);
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253 | const bool use_streams = !!ep->primary_stream_data_size;
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254 |
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255 | trb_splitter_t splitter;
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256 | trb_splitter_init(&splitter, transfer);
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257 |
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258 | const size_t trb_count = splitter.max_trb_count + use_streams;
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259 | xhci_trb_t trbs[trb_count];
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260 | size_t trbs_used = 0;
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261 |
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262 | while (splitter.remaining > 0)
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263 | trb_split_next(&trbs[trbs_used++], &splitter);
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264 |
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265 | if (!use_streams) {
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266 | /* Set the interrupt bit for last TRB */
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267 | TRB_CTRL_SET_IOC(trbs[trbs_used - 1], 1);
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268 | } else {
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269 | /* Clear the chain bit on the last TRB */
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270 | TRB_CTRL_SET_CHAIN(trbs[trbs_used - 1], 1);
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271 | TRB_CTRL_SET_ENT(trbs[trbs_used - 1], 1);
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272 |
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273 | xhci_trb_t *ed = &trbs[trbs_used++];
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274 | xhci_trb_clean(ed);
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275 | ed->parameter = host2xhci(64, (uintptr_t) transfer);
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276 | TRB_CTRL_SET_TRB_TYPE(*ed, XHCI_TRB_TYPE_EVENT_DATA);
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277 | TRB_CTRL_SET_IOC(*ed, 1);
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278 | }
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279 |
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280 | return xhci_trb_ring_enqueue_multiple(ring, trbs, trbs_used,
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281 | &transfer->interrupt_trb_phys);
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282 | }
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283 |
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284 | static int schedule_isochronous(xhci_transfer_t *transfer)
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285 | {
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286 | endpoint_t *ep = transfer->batch.ep;
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287 |
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288 | return ep->direction == USB_DIRECTION_OUT ?
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289 | isoch_schedule_out(transfer) :
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290 | isoch_schedule_in(transfer);
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291 | }
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292 |
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293 | errno_t xhci_handle_transfer_event(xhci_hc_t *hc, xhci_trb_t *trb)
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294 | {
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295 | uintptr_t addr = trb->parameter;
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296 | const unsigned slot_id = XHCI_DWORD_EXTRACT(trb->control, 31, 24);
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297 | const unsigned ep_dci = XHCI_DWORD_EXTRACT(trb->control, 20, 16);
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298 |
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299 | xhci_device_t *dev = hc->bus.devices_by_slot[slot_id];
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300 | if (!dev) {
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301 | usb_log_error("Transfer event on disabled slot %u", slot_id);
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302 | return ENOENT;
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303 | }
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304 |
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305 | const usb_endpoint_t ep_num = ep_dci / 2;
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306 | const usb_endpoint_t dir = ep_dci % 2 ? USB_DIRECTION_IN : USB_DIRECTION_OUT;
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307 | /* Creating temporary reference */
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308 | endpoint_t *ep_base = bus_find_endpoint(&dev->base, ep_num, dir);
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309 | if (!ep_base) {
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310 | usb_log_error("Transfer event on dropped endpoint %u %s of device "
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311 | XHCI_DEV_FMT, ep_num, usb_str_direction(dir), XHCI_DEV_ARGS(*dev));
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312 | return ENOENT;
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313 | }
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314 | xhci_endpoint_t *ep = xhci_endpoint_get(ep_base);
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315 |
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316 | usb_transfer_batch_t *batch;
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317 | xhci_transfer_t *transfer;
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318 |
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319 | if (TRB_EVENT_DATA(*trb)) {
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320 | /* We schedule those only when streams are involved */
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321 | assert(ep->primary_stream_ctx_array != NULL);
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322 |
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323 | /* We are received transfer pointer instead - work with that */
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324 | transfer = (xhci_transfer_t *) addr;
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325 | xhci_trb_ring_update_dequeue(get_ring(transfer),
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326 | transfer->interrupt_trb_phys);
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327 | batch = &transfer->batch;
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328 | } else {
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329 | xhci_trb_ring_update_dequeue(&ep->ring, addr);
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330 |
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331 | if (ep->base.transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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332 | isoch_handle_transfer_event(hc, ep, trb);
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333 | /* Dropping temporary reference */
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334 | endpoint_del_ref(&ep->base);
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335 | return EOK;
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336 | }
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337 |
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338 | fibril_mutex_lock(&ep->guard);
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339 | batch = ep->base.active_batch;
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340 | endpoint_deactivate_locked(&ep->base);
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341 | fibril_mutex_unlock(&ep->guard);
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342 |
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343 | if (!batch) {
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344 | /* Dropping temporary reference */
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345 | endpoint_del_ref(&ep->base);
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346 | return ENOENT;
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347 | }
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348 |
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349 | transfer = xhci_transfer_from_batch(batch);
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350 | }
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351 |
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352 | const xhci_trb_completion_code_t completion_code = TRB_COMPLETION_CODE(*trb);
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353 | switch (completion_code) {
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354 | case XHCI_TRBC_SHORT_PACKET:
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355 | case XHCI_TRBC_SUCCESS:
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356 | batch->error = EOK;
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357 | batch->transferred_size = batch->size - TRB_TRANSFER_LENGTH(*trb);
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358 | break;
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359 |
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360 | case XHCI_TRBC_DATA_BUFFER_ERROR:
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361 | usb_log_warning("Transfer ended with data buffer error.");
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362 | batch->error = EAGAIN;
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363 | batch->transferred_size = 0;
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364 | break;
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365 |
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366 | case XHCI_TRBC_BABBLE_DETECTED_ERROR:
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367 | usb_log_warning("Babble detected during the transfer.");
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368 | batch->error = EAGAIN;
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369 | batch->transferred_size = 0;
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370 | break;
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371 |
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372 | case XHCI_TRBC_USB_TRANSACTION_ERROR:
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373 | usb_log_warning("USB Transaction error.");
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374 | batch->error = EAGAIN;
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375 | batch->transferred_size = 0;
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376 | break;
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377 |
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378 | case XHCI_TRBC_TRB_ERROR:
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379 | usb_log_error("Invalid transfer parameters.");
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380 | batch->error = EINVAL;
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381 | batch->transferred_size = 0;
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382 | break;
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383 |
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384 | case XHCI_TRBC_STALL_ERROR:
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385 | usb_log_warning("Stall condition detected.");
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386 | batch->error = ESTALL;
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387 | batch->transferred_size = 0;
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388 | break;
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389 |
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390 | case XHCI_TRBC_SPLIT_TRANSACTION_ERROR:
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391 | usb_log_error("Split transcation error detected.");
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392 | batch->error = EAGAIN;
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393 | batch->transferred_size = 0;
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394 | break;
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395 |
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396 | default:
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397 | usb_log_warning("Transfer not successfull: %u", completion_code);
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398 | batch->error = EIO;
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399 | }
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400 |
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401 | assert(batch->transferred_size <= batch->size);
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402 |
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403 | usb_transfer_batch_finish(batch);
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404 | /* Dropping temporary reference */
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405 | endpoint_del_ref(&ep->base);
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406 | return EOK;
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407 | }
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408 |
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409 | typedef errno_t (*transfer_handler)(xhci_hc_t *, xhci_transfer_t *);
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410 |
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411 | static const transfer_handler transfer_handlers[] = {
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412 | [USB_TRANSFER_CONTROL] = schedule_control,
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413 | [USB_TRANSFER_ISOCHRONOUS] = NULL,
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414 | [USB_TRANSFER_BULK] = schedule_bulk_intr,
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415 | [USB_TRANSFER_INTERRUPT] = schedule_bulk_intr,
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416 | };
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417 |
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418 | /**
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419 | * Schedule a batch for xHC.
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420 | *
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421 | * Bus callback.
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422 | */
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423 | errno_t xhci_transfer_schedule(usb_transfer_batch_t *batch)
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424 | {
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425 | endpoint_t *ep = batch->ep;
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426 |
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427 | xhci_hc_t *hc = bus_to_hc(endpoint_get_bus(batch->ep));
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428 | xhci_transfer_t *transfer = xhci_transfer_from_batch(batch);
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429 | xhci_endpoint_t *xhci_ep = xhci_endpoint_get(ep);
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430 | xhci_device_t *xhci_dev = xhci_ep_to_dev(xhci_ep);
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431 |
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432 | if (!batch->target.address) {
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433 | usb_log_error("Attempted to schedule transfer to address 0.");
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434 | return EINVAL;
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435 | }
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436 |
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437 | // FIXME: find a better way to check if the ring is not initialized
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438 | if (!xhci_ep->ring.segment_count) {
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439 | usb_log_error("Ring not initialized for endpoint " XHCI_EP_FMT,
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440 | XHCI_EP_ARGS(*xhci_ep));
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441 | return EINVAL;
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442 | }
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443 |
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444 | // Isochronous transfer needs to be handled differently
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445 | if (batch->ep->transfer_type == USB_TRANSFER_ISOCHRONOUS) {
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446 | return schedule_isochronous(transfer);
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447 | }
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448 |
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449 | const usb_transfer_type_t type = batch->ep->transfer_type;
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450 | assert(transfer_handlers[type]);
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451 |
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452 | /*
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453 | * If this is a ClearFeature(ENDPOINT_HALT) request, we have to issue
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454 | * the Reset Endpoint command.
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455 | */
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456 | if (batch->ep->transfer_type == USB_TRANSFER_CONTROL &&
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457 | batch->dir == USB_DIRECTION_OUT) {
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458 | const usb_device_request_setup_packet_t *request = &batch->setup.packet;
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459 | if (request->request == USB_DEVREQ_CLEAR_FEATURE &&
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460 | request->request_type == USB_REQUEST_RECIPIENT_ENDPOINT &&
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461 | request->value == USB_FEATURE_ENDPOINT_HALT) {
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462 | const uint16_t index = uint16_usb2host(request->index);
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463 | const usb_endpoint_t ep_num = index & 0xf;
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464 | const usb_direction_t dir = (index >> 7) ?
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465 | USB_DIRECTION_IN :
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466 | USB_DIRECTION_OUT;
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467 | endpoint_t *halted_ep = bus_find_endpoint(&xhci_dev->base, ep_num, dir);
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468 | if (halted_ep) {
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469 | /*
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470 | * TODO: Find out how to come up with stream_id. It might be
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471 | * possible that we have to clear all of them.
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472 | */
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473 | const errno_t err = xhci_endpoint_clear_halt(xhci_endpoint_get(halted_ep), 0);
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474 | endpoint_del_ref(halted_ep);
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475 | if (err) {
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476 | /*
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477 | * The endpoint halt condition failed to be cleared in HC.
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478 | * As it does not make sense to send the reset to the device
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479 | * itself, return as unschedulable answer.
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480 | *
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481 | * Furthermore, if this is a request to clear EP 0 stall, it
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482 | * would be gone forever, as the endpoint is halted.
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483 | */
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484 | return err;
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485 | }
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486 | } else {
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487 | usb_log_warning("Device(%u): Resetting unregistered endpoint"
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488 | " %u %s.", xhci_dev->base.address, ep_num,
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489 | usb_str_direction(dir));
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490 | }
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491 | }
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492 | }
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493 |
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494 | errno_t err;
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495 | fibril_mutex_lock(&xhci_ep->guard);
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496 |
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497 | if ((err = endpoint_activate_locked(ep, batch))) {
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498 | fibril_mutex_unlock(&xhci_ep->guard);
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499 | return err;
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500 | }
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501 |
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502 | if ((err = transfer_handlers[batch->ep->transfer_type](hc, transfer))) {
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503 | endpoint_deactivate_locked(ep);
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504 | fibril_mutex_unlock(&xhci_ep->guard);
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505 | return err;
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506 | }
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507 |
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508 | hc_ring_ep_doorbell(xhci_ep, batch->target.stream);
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509 | fibril_mutex_unlock(&xhci_ep->guard);
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510 | return EOK;
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511 | }
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