source: mainline/uspace/drv/bus/usb/xhci/rh.c@ 9f5b613

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9f5b613 was 66dcc24, checked in by Jaroslav Jindrak <dzejrou@…>, 8 years ago

Fixed port regs reading on port change event, new devices are now properly detected! Good old off by one errors.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 * Copyright (c) 2017 Michal Staruch
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup drvusbxhci
30 * @{
31 */
32/** @file
33 * @brief The roothub structures abstraction.
34 */
35
36#include <errno.h>
37#include <str_error.h>
38#include <usb/debug.h>
39#include "debug.h"
40#include "hc.h"
41#include "hw_struct/trb.h"
42#include "rh.h"
43
44static int handle_connected_device(xhci_hc_t* hc, xhci_port_regs_t* regs, uint8_t port_id)
45{
46 uint8_t link_state = XHCI_REG_RD(regs, XHCI_PORT_PLS);
47 if (link_state == 0) {
48 // USB3 is automatically advance to enabled
49 uint8_t port_speed = XHCI_REG_RD(regs, XHCI_PORT_PS);
50 usb_log_debug2("Detected new device on port %u, port speed id %u.", port_id, port_speed);
51 // TODO: Assign device slot (specification 4.3.2)
52 } else if (link_state == 5) {
53 // USB 3 failed to enable
54 usb_log_debug("USB 3 port couldn't be enabled.");
55 } else if (link_state == 7) {
56 usb_log_debug("USB 2 device attached, issuing reset.");
57 xhci_reset_hub_port(hc, port_id);
58 }
59
60 return EOK;
61}
62
63int xhci_handle_port_status_change_event(xhci_hc_t *hc, xhci_trb_t *trb)
64{
65 uint8_t port_id = xhci_get_hub_port(trb);
66 usb_log_debug("Port status change event detected for port %u.", port_id);
67 xhci_port_regs_t* regs = &hc->op_regs->portrs[port_id - 1];
68
69 // Port reset change
70 if (XHCI_REG_RD(regs, XHCI_PORT_PRC)) {
71 // Clear the flag
72 XHCI_REG_WR(regs, XHCI_PORT_PRC, 1);
73
74 uint8_t port_speed = XHCI_REG_RD(regs, XHCI_PORT_PS);
75 usb_log_debug2("Detected port reset on port %u, port speed id %u.", port_id, port_speed);
76 // TODO: Assign device slot (specification 4.3.2)
77 }
78
79 // Connection status change
80 if (XHCI_REG_RD(regs, XHCI_PORT_CSC)) {
81 XHCI_REG_WR(regs, XHCI_PORT_CSC, 1);
82
83 if (XHCI_REG_RD(regs, XHCI_PORT_CCS) == 1) {
84 handle_connected_device(hc, regs, port_id);
85 } else {
86 // Device disconnected
87 }
88 }
89
90 return EOK;
91}
92
93int xhci_get_hub_port(xhci_trb_t *trb)
94{
95 assert(trb);
96 uint8_t port_id = XHCI_QWORD_EXTRACT(trb->parameter, 31, 24);
97
98 return port_id;
99}
100
101int xhci_reset_hub_port(xhci_hc_t* hc, uint8_t port)
102{
103 usb_log_debug2("Resetting port %u.", port);
104 xhci_port_regs_t regs = hc->op_regs->portrs[port];
105 XHCI_REG_WR(&regs, XHCI_PORT_PR, 1);
106
107 return EOK;
108}
109
110
111/**
112 * @}
113 */
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